cpuconf.h revision 1.14
1 /* $NetBSD: cpuconf.h,v 1.14 2008/04/27 18:58:44 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 46 #define __CPU_XSCALE_PXA2XX 47 #endif 48 49 #ifdef CPU_XSCALE_PXA2X0 50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 51 #endif 52 53 /* 54 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 55 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 56 * YOU ARE ADDING SUPPORT FOR. 57 */ 58 59 #if 0 60 /* 61 * Step 1: Count the number of CPU types configured into the kernel. 62 */ 63 #if defined(_KERNEL_OPT) 64 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 65 defined(CPU_ARM3) + \ 66 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 67 defined(CPU_ARM7TDMI) + \ 68 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 69 defined(CPU_ARM9E) + \ 70 defined(CPU_ARM10) + \ 71 defined(CPU_ARM11) + \ 72 defined(CPU_ARM1136) + \ 73 defined(CPU_ARM1176) + \ 74 defined(CPU_SA110) + defined(CPU_SA1100) + \ 75 defined(CPU_SA1110) + \ 76 defined(CPU_IXP12X0) + \ 77 defined(CPU_XSCALE_80200) + \ 78 defined(CPU_XSCALE_80321) + \ 79 defined(__CPU_XSCALE_PXA2XX) + \ 80 defined(CPU_XSCALE_IXP425)) 81 #else 82 #define CPU_NTYPES 2 83 #endif /* _KERNEL_OPT */ 84 #endif 85 86 /* 87 * Step 2: Determine which ARM architecture versions are configured. 88 */ 89 #if !defined(_KERNEL_OPT) || \ 90 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 91 #define ARM_ARCH_2 1 92 #else 93 #define ARM_ARCH_2 0 94 #endif 95 96 #if !defined(_KERNEL_OPT) || \ 97 (defined(CPU_ARM6) || defined(CPU_ARM7)) 98 #define ARM_ARCH_3 1 99 #else 100 #define ARM_ARCH_3 0 101 #endif 102 103 #if !defined(_KERNEL_OPT) || \ 104 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 105 defined(CPU_SA110) || defined(CPU_SA1100) || \ 106 defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 107 #define ARM_ARCH_4 1 108 #else 109 #define ARM_ARCH_4 0 110 #endif 111 112 #if !defined(_KERNEL_OPT) || \ 113 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 114 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 115 defined(__CPU_XSCALE_PXA2XX)) 116 #define ARM_ARCH_5 1 117 #else 118 #define ARM_ARCH_5 0 119 #endif 120 121 #if defined(CPU_ARM11) 122 #define ARM_ARCH_6 1 123 #else 124 #define ARM_ARCH_6 0 125 #endif 126 127 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 128 ARM_ARCH_5 + ARM_ARCH_6) 129 #if ARM_NARCH == 0 130 #error ARM_NARCH is 0 131 #endif 132 133 #if ARM_ARCH_5 || ARM_ARCH_6 134 /* 135 * We could support Thumb code on v4T, but the lack of clean interworking 136 * makes that hard. 137 */ 138 #define THUMB_CODE 139 #endif 140 141 /* 142 * Step 3: Define which MMU classes are configured: 143 * 144 * ARM_MMU_MEMC Prehistoric, external memory controller 145 * and MMU for ARMv2 CPUs. 146 * 147 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 148 * 149 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 150 * ARM MMU, but has no write-through cache mode. 151 * 152 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 153 * MMU, but also has several extensions which 154 * require different PTE layout to use. 155 * 156 * ARM_MMU_V6 ARM v6 MMU. Compatible with generic ARM 157 * MMU, but also has several extensions which 158 * require different PTE layouts to use. 159 */ 160 #if !defined(_KERNEL_OPT) || \ 161 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 162 #define ARM_MMU_MEMC 1 163 #else 164 #define ARM_MMU_MEMC 0 165 #endif 166 167 #if !defined(_KERNEL_OPT) || \ 168 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 169 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 170 defined(CPU_ARM10)) 171 #define ARM_MMU_GENERIC 1 172 #else 173 #define ARM_MMU_GENERIC 0 174 #endif 175 176 #if !defined(_KERNEL_OPT) || \ 177 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 178 defined(CPU_IXP12X0)) 179 #define ARM_MMU_SA1 1 180 #else 181 #define ARM_MMU_SA1 0 182 #endif 183 184 #if !defined(_KERNEL_OPT) || \ 185 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 186 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 187 #define ARM_MMU_XSCALE 1 188 #else 189 #define ARM_MMU_XSCALE 0 190 #endif 191 192 #if !defined(_KERNEL_OPT) || \ 193 defined(CPU_ARM11) 194 #define ARM_MMU_V6 1 195 #else 196 #define ARM_MMU_V6 0 197 #endif 198 199 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 200 ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V6) 201 #if ARM_NMMUS == 0 202 #error ARM_NMMUS is 0 203 #endif 204 205 /* 206 * Step 4: Define features that may be present on a subset of CPUs 207 * 208 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 209 */ 210 211 #if !defined(_KERNEL_OPT) || \ 212 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 213 #define ARM_XSCALE_PMU 1 214 #else 215 #define ARM_XSCALE_PMU 0 216 #endif 217 218 #endif /* _ARM_CPUCONF_H_ */ 219
Indexes created Tue Sep 23 23:09:58 GMT 2025