cpuconf.h revision 1.16.2.1
1 /* $NetBSD: cpuconf.h,v 1.16.2.1 2010/08/17 06:44:04 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 46 #define __CPU_XSCALE_PXA2XX 47 #endif 48 49 #ifdef CPU_XSCALE_PXA2X0 50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 51 #endif 52 53 /* 54 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 55 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 56 * YOU ARE ADDING SUPPORT FOR. 57 */ 58 59 #if 0 60 /* 61 * Step 1: Count the number of CPU types configured into the kernel. 62 */ 63 #if defined(_KERNEL_OPT) 64 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 65 defined(CPU_ARM3) + \ 66 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 67 defined(CPU_ARM7TDMI) + \ 68 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 69 defined(CPU_ARM9E) + \ 70 defined(CPU_ARM10) + \ 71 defined(CPU_ARM11) + \ 72 defined(CPU_ARM1136) + \ 73 defined(CPU_ARM1176) + \ 74 defined(CPU_CORTEX) + \ 75 defined(CPU_CORTEXA8) + \ 76 defined(CPU_CORTEXA9) + \ 77 defined(CPU_SA110) + defined(CPU_SA1100) + \ 78 defined(CPU_SA1110) + \ 79 defined(CPU_FA526) + \ 80 defined(CPU_IXP12X0) + \ 81 defined(CPU_XSCALE_80200) + \ 82 defined(CPU_XSCALE_80321) + \ 83 defined(__CPU_XSCALE_PXA2XX) + \ 84 defined(CPU_XSCALE_IXP425)) 85 #else 86 #define CPU_NTYPES 2 87 #endif /* _KERNEL_OPT */ 88 #endif 89 90 /* 91 * Step 2: Determine which ARM architecture versions are configured. 92 */ 93 #if !defined(_KERNEL_OPT) || \ 94 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 95 #define ARM_ARCH_2 1 96 #else 97 #define ARM_ARCH_2 0 98 #endif 99 100 #if !defined(_KERNEL_OPT) || \ 101 (defined(CPU_ARM6) || defined(CPU_ARM7)) 102 #define ARM_ARCH_3 1 103 #else 104 #define ARM_ARCH_3 0 105 #endif 106 107 #if !defined(_KERNEL_OPT) || \ 108 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 109 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \ 110 defined(CPU_SA1110) || defined(CPU_IXP12X0)) 111 #define ARM_ARCH_4 1 112 #else 113 #define ARM_ARCH_4 0 114 #endif 115 116 #if !defined(_KERNEL_OPT) || \ 117 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 118 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 119 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 120 #define ARM_ARCH_5 1 121 #else 122 #define ARM_ARCH_5 0 123 #endif 124 125 #if defined(CPU_ARM11) || defined(CPU_CORTEXA8) 126 #define ARM_ARCH_6 1 127 #else 128 #define ARM_ARCH_6 0 129 #endif 130 131 #if defined(CPU_CORTEX) 132 #define ARM_ARCH_7 1 133 #else 134 #define ARM_ARCH_7 0 135 #endif 136 137 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 138 ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) 139 #if ARM_NARCH == 0 140 #error ARM_NARCH is 0 141 #endif 142 143 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7 144 /* 145 * We could support Thumb code on v4T, but the lack of clean interworking 146 * makes that hard. 147 */ 148 #define THUMB_CODE 149 #endif 150 151 /* 152 * Step 3: Define which MMU classes are configured: 153 * 154 * ARM_MMU_MEMC Prehistoric, external memory controller 155 * and MMU for ARMv2 CPUs. 156 * 157 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 158 * 159 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 160 * ARM MMU, but has no write-through cache mode. 161 * 162 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 163 * MMU, but also has several extensions which 164 * require different PTE layout to use. 165 * 166 * ARM_MMU_V6 ARM v6 MMU. Compatible with generic ARM 167 * MMU, but also has several extensions which 168 * require different PTE layouts to use. 169 */ 170 #if !defined(_KERNEL_OPT) || \ 171 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 172 #define ARM_MMU_MEMC 1 173 #else 174 #define ARM_MMU_MEMC 0 175 #endif 176 177 #if !defined(_KERNEL_OPT) || \ 178 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 179 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 180 defined(CPU_ARM10) || defined(CPU_FA526)) 181 #define ARM_MMU_GENERIC 1 182 #else 183 #define ARM_MMU_GENERIC 0 184 #endif 185 186 #if !defined(_KERNEL_OPT) || \ 187 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 188 defined(CPU_IXP12X0)) 189 #define ARM_MMU_SA1 1 190 #else 191 #define ARM_MMU_SA1 0 192 #endif 193 194 #if !defined(_KERNEL_OPT) || \ 195 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 196 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 197 #define ARM_MMU_XSCALE 1 198 #else 199 #define ARM_MMU_XSCALE 0 200 #endif 201 202 #if !defined(_KERNEL_OPT) || \ 203 defined(CPU_ARM11) 204 #define ARM_MMU_V6 1 205 #else 206 #define ARM_MMU_V6 0 207 #endif 208 209 #if !defined(_KERNEL_OPT) || \ 210 defined(CPU_CORTEX) 211 #define ARM_MMU_V7 1 212 #else 213 #define ARM_MMU_V7 0 214 #endif 215 216 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 217 ARM_MMU_SA1 + ARM_MMU_XSCALE + \ 218 ARM_MMU_V6 + ARM_MMU_V7) 219 #if ARM_NMMUS == 0 220 #error ARM_NMMUS is 0 221 #endif 222 223 /* 224 * Step 4: Define features that may be present on a subset of CPUs 225 * 226 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 227 */ 228 229 #if !defined(_KERNEL_OPT) || \ 230 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 231 #define ARM_XSCALE_PMU 1 232 #else 233 #define ARM_XSCALE_PMU 0 234 #endif 235 236 #endif /* _ARM_CPUCONF_H_ */ 237
Indexes created Sun Oct 19 02:09:48 GMT 2025