cpuconf.h revision 1.27
1 /* $NetBSD: cpuconf.h,v 1.27 2018/08/10 16:17:30 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #include "opt_cpuoptions.h" 44 #endif /* _KERNEL_OPT */ 45 46 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 47 #define __CPU_XSCALE_PXA2XX 48 #endif 49 50 #ifdef CPU_XSCALE_PXA2X0 51 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 52 #endif 53 54 /* 55 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 56 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 57 * YOU ARE ADDING SUPPORT FOR. 58 */ 59 60 #if 0 61 /* 62 * Step 1: Count the number of CPU types configured into the kernel. 63 */ 64 #if defined(_KERNEL_OPT) 65 #define CPU_NTYPES (defined(CPU_ARM6) + defined(CPU_ARM7) + \ 66 defined(CPU_ARM7TDMI) + \ 67 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 68 defined(CPU_ARM9E) + \ 69 defined(CPU_ARM10) + \ 70 defined(CPU_ARM11) + \ 71 defined(CPU_ARM1136) + \ 72 defined(CPU_ARM1176) + \ 73 defined(CPU_ARM11MPCORE) + \ 74 defined(CPU_CORTEX) + \ 75 defined(CPU_CORTEXA8) + \ 76 defined(CPU_CORTEXA9) + \ 77 defined(CPU_SA110) + defined(CPU_SA1100) + \ 78 defined(CPU_SA1110) + \ 79 defined(CPU_FA526) + \ 80 defined(CPU_IXP12X0) + \ 81 defined(CPU_XSCALE) + \ 82 defined(CPU_SHEEVA)) 83 #else 84 #define CPU_NTYPES 2 85 #endif /* _KERNEL_OPT */ 86 #endif 87 88 /* 89 * Step 2: Determine which ARM architecture versions are configured. 90 */ 91 #if !defined(_KERNEL_OPT) 92 #define ARM_ARCH_2 1 93 #else 94 #define ARM_ARCH_2 0 95 #endif 96 97 #if !defined(_KERNEL_OPT) || \ 98 (defined(CPU_ARM6) || defined(CPU_ARM7)) 99 #define ARM_ARCH_3 1 100 #else 101 #define ARM_ARCH_3 0 102 #endif 103 104 #if !defined(_KERNEL_OPT) || \ 105 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 106 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \ 107 defined(CPU_SA1110) || defined(CPU_IXP12X0)) 108 #define ARM_ARCH_4 1 109 #else 110 #define ARM_ARCH_4 0 111 #endif 112 113 #if !defined(_KERNEL_OPT) || \ 114 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 115 defined(CPU_XSCALE) || defined(CPU_SHEEVA)) 116 #define ARM_ARCH_5 1 117 #else 118 #define ARM_ARCH_5 0 119 #endif 120 121 #if defined(CPU_ARM11) || defined(CPU_ARM11MPCORE) 122 #define ARM_ARCH_6 1 123 #else 124 #define ARM_ARCH_6 0 125 #endif 126 127 #if defined(CPU_CORTEX) || defined(CPU_PJ4B) 128 #define ARM_ARCH_7 1 129 #else 130 #define ARM_ARCH_7 0 131 #endif 132 133 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 134 ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) 135 #if ARM_NARCH == 0 136 #error ARM_NARCH is 0 137 #endif 138 139 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7 140 /* 141 * We could support Thumb code on v4T, but the lack of clean interworking 142 * makes that hard. 143 */ 144 #define THUMB_CODE 145 #endif 146 147 /* 148 * Step 3: Define which MMU classes are configured: 149 * 150 * ARM_MMU_MEMC Prehistoric, external memory controller 151 * and MMU for ARMv2 CPUs. 152 * 153 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 154 * 155 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 156 * ARM MMU, but has no write-through cache mode. 157 * 158 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 159 * MMU, but also has several extensions which 160 * require different PTE layout to use. 161 * 162 * ARM_MMU_V6C ARM v6 MMU in backward compatible mode. 163 * Compatible with generic ARM MMU, but 164 * also has several extensions which 165 * require different PTE layouts to use. 166 * XP bit in CP15 control reg is cleared. 167 * 168 * ARM_MMU_V6N ARM v6 MMU with XP bit of CP15 control reg 169 * set. New features such as shared-bit 170 * and excute-never bit are available. 171 * Multiprocessor support needs this mode. 172 * 173 * ARM_MMU_V7 ARM v7 MMU. 174 */ 175 #if !defined(_KERNEL_OPT) 176 #define ARM_MMU_MEMC 1 177 #else 178 #define ARM_MMU_MEMC 0 179 #endif 180 181 #if !defined(_KERNEL_OPT) || \ 182 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 183 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 184 defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA) 185 #define ARM_MMU_GENERIC 1 186 #else 187 #define ARM_MMU_GENERIC 0 188 #endif 189 190 #if !defined(_KERNEL_OPT) || \ 191 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 192 defined(CPU_IXP12X0)) 193 #define ARM_MMU_SA1 1 194 #else 195 #define ARM_MMU_SA1 0 196 #endif 197 198 #if !defined(_KERNEL_OPT) || \ 199 defined(CPU_XSCALE) 200 #define ARM_MMU_XSCALE 1 201 #else 202 #define ARM_MMU_XSCALE 0 203 #endif 204 205 #if !defined(_KERNEL_OPT) || \ 206 (defined(CPU_ARM11) && defined(ARM11_COMPAT_MMU)) 207 #define ARM_MMU_V6C 1 208 #else 209 #define ARM_MMU_V6C 0 210 #endif 211 212 #if !defined(_KERNEL_OPT) || \ 213 (defined(CPU_ARM11) && !defined(ARM11_COMPAT_MMU)) 214 #define ARM_MMU_V6N 1 215 #else 216 #define ARM_MMU_V6N 0 217 #endif 218 219 #define ARM_MMU_V6 (ARM_MMU_V6C + ARM_MMU_V6N) 220 221 #if !defined(_KERNEL_OPT) || \ 222 defined(CPU_ARMV7) 223 #define ARM_MMU_V7 1 224 #else 225 #define ARM_MMU_V7 0 226 #endif 227 228 #if !defined(_KERNEL_OPT) || \ 229 defined(CPU_ARMV8) 230 #define ARM_MMU_V8 1 231 #else 232 #define ARM_MMU_V8 0 233 #endif 234 235 /* 236 * Can we use the ASID support in armv6+ MMUs? 237 */ 238 #if !defined(_LOCORE) 239 #define ARM_MMU_EXTENDED \ 240 ((ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_XSCALE + \ 241 ARM_MMU_V6C) == 0 && \ 242 (ARM_MMU_V6N + ARM_MMU_V7 + ARM_MMU_V8) > 0) 243 #if ARM_MMU_EXTENDED == 0 244 #undef ARM_MMU_EXTENDED 245 #endif 246 #endif 247 248 #define ARM_NMMUS \ 249 (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_XSCALE + \ 250 ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7 + ARM_MMU_V8) 251 #if ARM_NMMUS == 0 252 #error ARM_NMMUS is 0 253 #endif 254 255 /* 256 * Step 4: Define features that may be present on a subset of CPUs 257 * 258 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 259 */ 260 261 #if !defined(_KERNEL_OPT) || \ 262 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 263 #define ARM_XSCALE_PMU 1 264 #else 265 #define ARM_XSCALE_PMU 0 266 #endif 267 268 #endif /* _ARM_CPUCONF_H_ */ 269
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