cpuconf.h revision 1.7
1 /* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 /* 46 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 47 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 48 * YOU ARE ADDING SUPPORT FOR. 49 */ 50 51 /* 52 * Step 1: Count the number of CPU types configured into the kernel. 53 */ 54 #if defined(_KERNEL_OPT) 55 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 56 defined(CPU_ARM3) + \ 57 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 58 defined(CPU_ARM7TDMI) + \ 59 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 60 defined(CPU_SA110) + defined(CPU_SA1100) + \ 61 defined(CPU_SA1110) + \ 62 defined(CPU_IXP12X0) + \ 63 defined(CPU_XSCALE_80200) + \ 64 defined(CPU_XSCALE_80321) + \ 65 defined(CPU_XSCALE_PXA2X0) + \ 66 defined(CPU_XSCALE_IXP425)) 67 #else 68 #define CPU_NTYPES 2 69 #endif /* _KERNEL_OPT */ 70 71 /* 72 * Step 2: Determine which ARM architecture versions are configured. 73 */ 74 #if !defined(_KERNEL_OPT) || \ 75 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 76 #define ARM_ARCH_2 1 77 #else 78 #define ARM_ARCH_2 0 79 #endif 80 81 #if !defined(_KERNEL_OPT) || \ 82 (defined(CPU_ARM6) || defined(CPU_ARM7)) 83 #define ARM_ARCH_3 1 84 #else 85 #define ARM_ARCH_3 0 86 #endif 87 88 #if !defined(_KERNEL_OPT) || \ 89 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 90 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 91 defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 92 #define ARM_ARCH_4 1 93 #else 94 #define ARM_ARCH_4 0 95 #endif 96 97 #if !defined(_KERNEL_OPT) || \ 98 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 99 defined(CPU_XSCALE_PXA2X0)) 100 #define ARM_ARCH_5 1 101 #else 102 #define ARM_ARCH_5 0 103 #endif 104 105 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) 106 #if ARM_NARCH == 0 107 #error ARM_NARCH is 0 108 #endif 109 110 /* 111 * Step 3: Define which MMU classes are configured: 112 * 113 * ARM_MMU_MEMC Prehistoric, external memory controller 114 * and MMU for ARMv2 CPUs. 115 * 116 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 117 * 118 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 119 * ARM MMU, but has no write-through cache mode. 120 * 121 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 122 * MMU, but also has several extensions which 123 * require different PTE layout to use. 124 */ 125 #if !defined(_KERNEL_OPT) || \ 126 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 127 #define ARM_MMU_MEMC 1 128 #else 129 #define ARM_MMU_MEMC 0 130 #endif 131 132 #if !defined(_KERNEL_OPT) || \ 133 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 134 defined(CPU_ARM8) || defined(CPU_ARM9)) 135 #define ARM_MMU_GENERIC 1 136 #else 137 #define ARM_MMU_GENERIC 0 138 #endif 139 140 #if !defined(_KERNEL_OPT) || \ 141 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 142 defined(CPU_IXP12X0)) 143 #define ARM_MMU_SA1 1 144 #else 145 #define ARM_MMU_SA1 0 146 #endif 147 148 #if !defined(_KERNEL_OPT) || \ 149 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 150 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) 151 #define ARM_MMU_XSCALE 1 152 #else 153 #define ARM_MMU_XSCALE 0 154 #endif 155 156 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 157 ARM_MMU_SA1 + ARM_MMU_XSCALE) 158 #if ARM_NMMUS == 0 159 #error ARM_NMMUS is 0 160 #endif 161 162 /* 163 * Step 4: Define features that may be present on a subset of CPUs 164 * 165 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 166 */ 167 168 #if !defined(_KERNEL_OPT) || \ 169 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 170 #define ARM_XSCALE_PMU 1 171 #else 172 #define ARM_XSCALE_PMU 0 173 #endif 174 175 #endif /* _ARM_CPUCONF_H_ */ 176
Indexes created Wed Sep 24 15:09:51 GMT 2025