cpuconf.h revision 1.7.2.4
1 /* $NetBSD: cpuconf.h,v 1.7.2.4 2004/09/21 13:13:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 /* 46 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 47 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 48 * YOU ARE ADDING SUPPORT FOR. 49 */ 50 51 /* 52 * Step 1: Count the number of CPU types configured into the kernel. 53 */ 54 #if defined(_KERNEL_OPT) 55 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 56 defined(CPU_ARM3) + \ 57 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 58 defined(CPU_ARM7TDMI) + \ 59 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 60 defined(CPU_ARM10) + \ 61 defined(CPU_SA110) + defined(CPU_SA1100) + \ 62 defined(CPU_SA1110) + \ 63 defined(CPU_IXP12X0) + \ 64 defined(CPU_XSCALE_80200) + \ 65 defined(CPU_XSCALE_80321) + \ 66 defined(CPU_XSCALE_PXA2X0) + \ 67 defined(CPU_XSCALE_IXP425)) 68 #else 69 #define CPU_NTYPES 2 70 #endif /* _KERNEL_OPT */ 71 72 /* 73 * Step 2: Determine which ARM architecture versions are configured. 74 */ 75 #if !defined(_KERNEL_OPT) || \ 76 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 77 #define ARM_ARCH_2 1 78 #else 79 #define ARM_ARCH_2 0 80 #endif 81 82 #if !defined(_KERNEL_OPT) || \ 83 (defined(CPU_ARM6) || defined(CPU_ARM7)) 84 #define ARM_ARCH_3 1 85 #else 86 #define ARM_ARCH_3 0 87 #endif 88 89 #if !defined(_KERNEL_OPT) || \ 90 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 91 defined(CPU_SA110) || defined(CPU_SA1100) || \ 92 defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 93 #define ARM_ARCH_4 1 94 #else 95 #define ARM_ARCH_4 0 96 #endif 97 98 #if !defined(_KERNEL_OPT) || \ 99 (defined(CPU_ARM10) || defined(CPU_XSCALE_80200) || \ 100 defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)) 101 #define ARM_ARCH_5 1 102 #else 103 #define ARM_ARCH_5 0 104 #endif 105 106 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) 107 #if ARM_NARCH == 0 108 #error ARM_NARCH is 0 109 #endif 110 111 #if ARM_ARCH_5 112 /* 113 * We could support Thumb code on v4T, but the lack of clean interworking 114 * makes that hard. 115 */ 116 #define THUMB_CODE 117 #endif 118 119 /* 120 * Step 3: Define which MMU classes are configured: 121 * 122 * ARM_MMU_MEMC Prehistoric, external memory controller 123 * and MMU for ARMv2 CPUs. 124 * 125 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 126 * 127 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 128 * ARM MMU, but has no write-through cache mode. 129 * 130 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 131 * MMU, but also has several extensions which 132 * require different PTE layout to use. 133 */ 134 #if !defined(_KERNEL_OPT) || \ 135 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 136 #define ARM_MMU_MEMC 1 137 #else 138 #define ARM_MMU_MEMC 0 139 #endif 140 141 #if !defined(_KERNEL_OPT) || \ 142 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 143 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10)) 144 #define ARM_MMU_GENERIC 1 145 #else 146 #define ARM_MMU_GENERIC 0 147 #endif 148 149 #if !defined(_KERNEL_OPT) || \ 150 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 151 defined(CPU_IXP12X0)) 152 #define ARM_MMU_SA1 1 153 #else 154 #define ARM_MMU_SA1 0 155 #endif 156 157 #if !defined(_KERNEL_OPT) || \ 158 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 159 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) 160 #define ARM_MMU_XSCALE 1 161 #else 162 #define ARM_MMU_XSCALE 0 163 #endif 164 165 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 166 ARM_MMU_SA1 + ARM_MMU_XSCALE) 167 #if ARM_NMMUS == 0 168 #error ARM_NMMUS is 0 169 #endif 170 171 /* 172 * Step 4: Define features that may be present on a subset of CPUs 173 * 174 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 175 */ 176 177 #if !defined(_KERNEL_OPT) || \ 178 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 179 #define ARM_XSCALE_PMU 1 180 #else 181 #define ARM_XSCALE_PMU 0 182 #endif 183 184 #endif /* _ARM_CPUCONF_H_ */ 185
Indexes created Sat Oct 18 08:10:09 GMT 2025