cpufunc.h revision 1.10
1 /* $NetBSD: cpufunc.h,v 1.10 2001/10/18 14:10:07 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #include <sys/types.h> 46 47 #ifdef _KERNEL 48 #ifndef _LKM 49 #include "opt_cputypes.h" 50 #endif 51 52 struct cpu_functions { 53 54 /* CPU functions */ 55 56 u_int (*cf_id) __P((void)); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) __P((u_int bic, u_int eor)); 61 void (*cf_domains) __P((u_int domains)); 62 void (*cf_setttb) __P((u_int ttb)); 63 u_int (*cf_faultstatus) __P((void)); 64 u_int (*cf_faultaddress) __P((void)); 65 66 /* TLB functions */ 67 68 void (*cf_tlb_flushID) __P((void)); 69 void (*cf_tlb_flushID_SE) __P((u_int va)); 70 void (*cf_tlb_flushI) __P((void)); 71 void (*cf_tlb_flushI_SE) __P((u_int va)); 72 void (*cf_tlb_flushD) __P((void)); 73 void (*cf_tlb_flushD_SE) __P((u_int va)); 74 75 /* Cache functions */ 76 77 void (*cf_cache_flushID) __P((void)); 78 void (*cf_cache_flushID_SE) __P((u_int va)); 79 void (*cf_cache_flushI) __P((void)); 80 void (*cf_cache_flushI_SE) __P((u_int va)); 81 void (*cf_cache_flushD) __P((void)); 82 void (*cf_cache_flushD_SE) __P((u_int va)); 83 84 void (*cf_cache_cleanID) __P((void)); 85 void (*cf_cache_cleanID_E) __P((u_int imp)); 86 void (*cf_cache_cleanD) __P((void)); 87 void (*cf_cache_cleanD_E) __P((u_int imp)); 88 89 void (*cf_cache_purgeID) __P((void)); 90 void (*cf_cache_purgeID_E) __P((u_int imp)); 91 void (*cf_cache_purgeD) __P((void)); 92 void (*cf_cache_purgeD_E) __P((u_int imp)); 93 94 /* Other functions */ 95 96 void (*cf_flush_prefetchbuf) __P((void)); 97 void (*cf_drain_writebuf) __P((void)); 98 void (*cf_flush_brnchtgt_C) __P((void)); 99 void (*cf_flush_brnchtgt_E) __P((u_int va)); 100 101 void (*cf_sleep) __P((int mode)); 102 103 /* Soft functions */ 104 105 void (*cf_cache_syncI) __P((void)); 106 void (*cf_cache_cleanID_rng) __P((u_int start, u_int len)); 107 void (*cf_cache_cleanD_rng) __P((u_int start, u_int len)); 108 void (*cf_cache_purgeID_rng) __P((u_int start, u_int len)); 109 void (*cf_cache_purgeD_rng) __P((u_int start, u_int len)); 110 void (*cf_cache_syncI_rng) __P((u_int start, u_int len)); 111 112 int (*cf_dataabt_fixup) __P((void *arg)); 113 int (*cf_prefetchabt_fixup) __P((void *arg)); 114 115 void (*cf_context_switch) __P((void)); 116 117 void (*cf_setup) __P((char *string)); 118 }; 119 120 extern struct cpu_functions cpufuncs; 121 extern u_int cputype; 122 123 #define cpu_id() cpufuncs.cf_id() 124 125 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 126 #define cpu_domains(d) cpufuncs.cf_domains(d) 127 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 128 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 129 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 130 131 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 132 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 133 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 134 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 135 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 136 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 137 138 #define cpu_cache_flushID() cpufuncs.cf_cache_flushID() 139 #define cpu_cache_flushID_SE(e) cpufuncs.cf_cache_flushID_SE(e) 140 #define cpu_cache_flushI() cpufuncs.cf_cache_flushI() 141 #define cpu_cache_flushI_SE(e) cpufuncs.cf_cache_flushI_SE(e) 142 #define cpu_cache_flushD() cpufuncs.cf_cache_flushD() 143 #define cpu_cache_flushD_SE(e) cpufuncs.cf_cache_flushD_SE(e) 144 #define cpu_cache_cleanID() cpufuncs.cf_cache_cleanID() 145 #define cpu_cache_cleanID_E(e) cpufuncs.cf_cache_cleanID_E(e) 146 #define cpu_cache_cleanD() cpufuncs.cf_cache_cleanD() 147 #define cpu_cache_cleanD_E(e) cpufuncs.cf_cache_cleanD_E(e) 148 #define cpu_cache_purgeID() cpufuncs.cf_cache_purgeID() 149 #define cpu_cache_purgeID_E(e) cpufuncs.cf_cache_purgeID_E(e) 150 #define cpu_cache_purgeD() cpufuncs.cf_cache_purgeD() 151 #define cpu_cache_purgeD_E(e) cpufuncs.cf_cache_purgeD_E(e) 152 153 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 154 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 155 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 156 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 157 158 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 159 160 #define cpu_cache_syncI() cpufuncs.cf_cache_syncI() 161 #define cpu_cache_cleanID_rng(s,l) cpufuncs.cf_cache_cleanID_rng(s,l) 162 #define cpu_cache_cleanD_rng(s,l) cpufuncs.cf_cache_cleanD_rng(s,l) 163 #define cpu_cache_purgeID_rng(s,l) cpufuncs.cf_cache_purgeID_rng(s,l) 164 #define cpu_cache_purgeD_rng(s,l) cpufuncs.cf_cache_purgeD_rng(s,l) 165 #define cpu_cache_syncI_rng(s,l) cpufuncs.cf_cache_syncI_rng(s,l) 166 167 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 168 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 169 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 170 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 171 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 172 173 #define cpu_setup(a) cpufuncs.cf_setup(a) 174 175 int set_cpufuncs __P((void)); 176 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 177 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 178 179 void cpufunc_nullop __P((void)); 180 int cpufunc_null_fixup __P((void *)); 181 int early_abort_fixup __P((void *)); 182 int late_abort_fixup __P((void *)); 183 u_int cpufunc_id __P((void)); 184 u_int cpufunc_control __P((u_int clear, u_int bic)); 185 void cpufunc_domains __P((u_int domains)); 186 u_int cpufunc_faultstatus __P((void)); 187 u_int cpufunc_faultaddress __P((void)); 188 189 #ifdef CPU_ARM3 190 u_int arm3_control __P((u_int clear, u_int bic)); 191 void arm3_cache_flush __P((void)); 192 #endif /* CPU_ARM3 */ 193 194 #if defined(CPU_ARM6) || defined(CPU_ARM7) 195 void arm67_setttb __P((u_int ttb)); 196 void arm67_tlb_flush __P((void)); 197 void arm67_tlb_purge __P((u_int va)); 198 void arm67_cache_flush __P((void)); 199 void arm67_context_switch __P((void)); 200 #endif /* CPU_ARM6 || CPU_ARM7 */ 201 202 #ifdef CPU_ARM6 203 void arm6_setup __P((char *string)); 204 #endif /* CPU_ARM6 */ 205 206 #ifdef CPU_ARM7 207 void arm7_setup __P((char *string)); 208 #endif /* CPU_ARM7 */ 209 210 #ifdef CPU_ARM7TDMI 211 int arm7_dataabt_fixup __P((void *arg)); 212 void arm7tdmi_setup __P((char *string)); 213 void arm7tdmi_setttb __P((u_int ttb)); 214 void arm7tdmi_tlb_flushID __P((void)); 215 void arm7tdmi_tlb_flushID_SE __P((u_int va)); 216 void arm7tdmi_cache_flushID __P((void)); 217 void arm7tdmi_context_switch __P((void)); 218 #endif /* CPU_ARM7TDMI */ 219 220 #ifdef CPU_ARM8 221 void arm8_setttb __P((u_int ttb)); 222 void arm8_tlb_flushID __P((void)); 223 void arm8_tlb_flushID_SE __P((u_int va)); 224 void arm8_cache_flushID __P((void)); 225 void arm8_cache_flushID_E __P((u_int entry)); 226 void arm8_cache_cleanID __P((void)); 227 void arm8_cache_cleanID_E __P((u_int entry)); 228 void arm8_cache_purgeID __P((void)); 229 void arm8_cache_purgeID_E __P((u_int entry)); 230 231 void arm8_cache_syncI __P((void)); 232 void arm8_cache_cleanID_rng __P((u_int start, u_int end)); 233 void arm8_cache_cleanD_rng __P((u_int start, u_int end)); 234 void arm8_cache_purgeID_rng __P((u_int start, u_int end)); 235 void arm8_cache_purgeD_rng __P((u_int start, u_int end)); 236 void arm8_cache_syncI_rng __P((u_int start, u_int end)); 237 238 void arm8_context_switch __P((void)); 239 240 void arm8_setup __P((char *string)); 241 242 u_int arm8_clock_config __P((u_int, u_int)); 243 #endif 244 245 #ifdef CPU_ARM9 246 void arm9_setttb __P((u_int)); 247 248 void arm9_tlb_flushID_SE __P((u_int va)); 249 250 void arm9_cache_flushID __P((void)); 251 void arm9_cache_flushID_SE __P((u_int)); 252 void arm9_cache_flushI __P((void)); 253 void arm9_cache_flushI_SE __P((u_int)); 254 void arm9_cache_flushD __P((void)); 255 void arm9_cache_flushD_SE __P((u_int)); 256 257 void arm9_cache_cleanID __P((void)); 258 259 void arm9_cache_syncI __P((void)); 260 void arm9_cache_flushID_rng __P((u_int, u_int)); 261 void arm9_cache_flushD_rng __P((u_int, u_int)); 262 void arm9_cache_syncI_rng __P((u_int, u_int)); 263 264 void arm9_context_switch __P((void)); 265 266 void arm9_setup __P((char *string)); 267 #endif 268 269 #if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE) 270 void armv4_tlb_flushID __P((void)); 271 void armv4_tlb_flushI __P((void)); 272 void armv4_tlb_flushD __P((void)); 273 void armv4_tlb_flushD_SE __P((u_int va)); 274 275 void armv4_drain_writebuf __P((void)); 276 #endif 277 278 #ifdef CPU_SA110 279 void sa110_setttb __P((u_int ttb)); 280 281 void sa110_tlb_flushID_SE __P((u_int va)); 282 283 void sa110_cache_flushID __P((void)); 284 void sa110_cache_flushI __P((void)); 285 void sa110_cache_flushD __P((void)); 286 void sa110_cache_flushD_SE __P((u_int entry)); 287 288 void sa110_cache_cleanID __P((void)); 289 void sa110_cache_cleanD __P((void)); 290 void sa110_cache_cleanD_E __P((u_int entry)); 291 292 void sa110_cache_purgeID __P((void)); 293 void sa110_cache_purgeID_E __P((u_int entry)); 294 void sa110_cache_purgeD __P((void)); 295 void sa110_cache_purgeD_E __P((u_int entry)); 296 297 void sa110_cache_syncI __P((void)); 298 void sa110_cache_cleanID_rng __P((u_int start, u_int end)); 299 void sa110_cache_cleanD_rng __P((u_int start, u_int end)); 300 void sa110_cache_purgeID_rng __P((u_int start, u_int end)); 301 void sa110_cache_purgeD_rng __P((u_int start, u_int end)); 302 void sa110_cache_syncI_rng __P((u_int start, u_int end)); 303 304 void sa110_context_switch __P((void)); 305 306 void sa110_setup __P((char *string)); 307 #endif /* CPU_SA110 */ 308 309 #ifdef CPU_XSCALE 310 void xscale_setttb __P((u_int ttb)); 311 312 void xscale_tlb_flushID_SE __P((u_int va)); 313 314 void xscale_cache_flushID __P((void)); 315 void xscale_cache_flushI __P((void)); 316 void xscale_cache_flushD __P((void)); 317 void xscale_cache_flushD_SE __P((u_int entry)); 318 319 void xscale_cache_cleanID __P((void)); 320 void xscale_cache_cleanD __P((void)); 321 void xscale_cache_cleanD_E __P((u_int entry)); 322 323 void xscale_cache_purgeID __P((void)); 324 void xscale_cache_purgeID_E __P((u_int entry)); 325 void xscale_cache_purgeD __P((void)); 326 void xscale_cache_purgeD_E __P((u_int entry)); 327 328 void xscale_cache_syncI __P((void)); 329 void xscale_cache_cleanID_rng __P((u_int start, u_int end)); 330 void xscale_cache_cleanD_rng __P((u_int start, u_int end)); 331 void xscale_cache_purgeID_rng __P((u_int start, u_int end)); 332 void xscale_cache_purgeD_rng __P((u_int start, u_int end)); 333 void xscale_cache_syncI_rng __P((u_int start, u_int end)); 334 335 void xscale_context_switch __P((void)); 336 337 void xscale_setup __P((char *string)); 338 #endif /* CPU_XSCALE */ 339 340 #define tlb_flush cpu_tlb_flushID 341 #define setttb cpu_setttb 342 #define cache_clean cpu_cache_purgeID 343 #define sync_caches cpu_cache_syncI 344 #define sync_icache cpu_cache_syncI 345 #define drain_writebuf cpu_drain_writebuf 346 347 /* 348 * Macros for manipulating CPU interrupts 349 */ 350 351 #define disable_interrupts(mask) \ 352 (SetCPSR((mask) & (I32_bit | F32_bit), (mask) & (I32_bit | F32_bit))) 353 354 #define enable_interrupts(mask) \ 355 (SetCPSR((mask) & (I32_bit | F32_bit), 0)) 356 357 #define restore_interrupts(old_cpsr) \ 358 (SetCPSR((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 359 360 /* 361 * Functions to manipulate the CPSR 362 * (in arm/arm32/setcpsr.S) 363 */ 364 365 u_int SetCPSR __P((u_int bic, u_int eor)); 366 u_int GetCPSR __P((void)); 367 368 /* 369 * Functions to manipulate cpu r13 370 * (in arm/arm32/setstack.S) 371 */ 372 373 void set_stackptr __P((u_int mode, u_int address)); 374 u_int get_stackptr __P((u_int mode)); 375 376 /* 377 * Miscellany 378 */ 379 380 int get_pc_str_offset __P((void)); 381 382 /* 383 * CPU functions from locore.S 384 */ 385 386 void cpu_reset __P((void)) __attribute__((__noreturn__)); 387 388 #endif /* _KERNEL */ 389 #endif /* _ARM32_CPUFUNC_H_ */ 390 391 /* End of cpufunc.h */ 392
Indexes created Thu Sep 25 16:09:42 GMT 2025