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History log of /src/sys/arch/arm/include/cpufunc.h
RevisionDateAuthorComments
 1.93  09-Oct-2025  rin arm/cpufunc.h: Fix RCSID, NFC
 1.92  26-Sep-2025  skrll arm: Adjust barriers issued in bus_dmamap_sync for the coherent case.

PR/59654

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.

These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

A new indrection is introduced to deal with the differencs in barrier
(dsb) options between Arm V8 and V7, the lack of options in Arm V6,
and the need to use cpu_drain_writebuf for all other earlier versions.

The Arm V8 Net change is:

op old new
 1.91  25-Sep-2025  skrll #define<tab> and other <tab> consistency
 1.90  28-Apr-2022  skrll branches: 1.90.4; 1.90.12;
G/C
 1.89  01-Nov-2021  skrll Move arm_cache_info from cpufunc.h to cpu.h
 1.88  01-Mar-2021  jmcneill Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUPT() but also returns
the previous state.

Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.
 1.87  07-Feb-2021  jmcneill Add ENABLE_INTERRUPT() / DISABLE_INTERRUPT() macros for compatibility
with aarch64.
 1.86  03-Dec-2020  skrll Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.
 1.85  31-Oct-2020  skrll branches: 1.85.2;
Fix armv6 builds by providing an armv6 is macro
 1.84  29-Sep-2020  skrll Fix RPI (armv6) build
 1.83  26-Sep-2020  skrll Define isb(), dsb(option), and dmb(option)

Catch up with vchiq upstream to allow this.
 1.82  11-Dec-2018  alnsn Don't exclude code from rump kernel build.
 1.81  20-Oct-2018  skrll Clean up around cpu_ttb and fix a bunch of builds
 1.80  29-Aug-2018  skrll Whitespace
 1.79  01-Apr-2018  ryo branches: 1.79.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
 1.78  24-Jan-2018  skrll branches: 1.78.2;
Remove port-acorn26

OK core@
 1.77  16-Jul-2016  mrg apply some #if (ARM_MMU_V6 + ARM_MMU_V7) != 0.
now this builds on pre v6-only.
 1.76  23-Jan-2016  christos branches: 1.76.2;
Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.
 1.75  17-Oct-2015  jmcneill remove tlb_flush define and change callers to use cpu_tlb_flushID directly, ok matt@
 1.74  20-Apr-2014  christos branches: 1.74.4;
include cpufunc_proto.h since things need it.
 1.73  19-Apr-2014  matt Move xscale cpu_cpwait back from cpufunc_proto.ht to cpufunc.h
 1.72  14-Apr-2014  matt Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.
 1.71  07-Apr-2014  matt Declare armv7 routines if CPU_ARMV7 is defined.
Rearrange in less random manner.
 1.70  29-Mar-2014  matt branches: 1.70.2;
cortex doesn't need xscale_setup
use arm11_setttb for arm11x6.
 1.69  28-Mar-2014  matt Use cpsie/cpsid if possible.
change cache_type to uint8_t
more ARM_MMU_EXTENDED support (ASID)
 1.68  22-Feb-2014  matt Add way_size to arm_cache_info
Fix arm67_tlb_purge prototype
 1.67  20-Feb-2014  matt Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
 1.66  20-Feb-2014  matt Make the tlb_flush*SE take a vaddr_t, not a u_int.
 1.65  29-Jan-2014  matt Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).
 1.64  12-Jun-2013  matt branches: 1.64.2;
Nuke cpu_pfr, just use the armreg_pfr?_read inlines
 1.63  19-May-2013  rkujawa Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.
 1.62  12-Nov-2012  skrll C99 types
 1.61  19-Oct-2012  matt Add armv7_drain_writebuf (which is just a dsb).
 1.60  22-Sep-2012  matt Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
 1.59  11-Sep-2012  matt branches: 1.59.2;
Add secondary cache range ops
 1.58  07-Sep-2012  matt Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
 1.57  21-Jul-2012  skrll Add support for the ARM1176JZS
 1.56  14-Jul-2012  hans Support cpu_sleep() on Sheeva CPUs.
 1.55  16-Feb-2012  christos expose functions needed to compute stack traces to kmemuser
 1.54  11-Dec-2011  kiyohara branches: 1.54.2;
Require arm3_cache_flush for ARM2/ARM250.
 1.53  10-Mar-2011  bsh branches: 1.53.4; 1.53.8;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.
 1.52  02-Oct-2010  kiyohara branches: 1.52.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
 1.51  19-Jun-2010  matt Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
 1.50  16-Jun-2010  jmcneill PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt
 1.49  21-Oct-2008  matt branches: 1.49.12; 1.49.14; 1.49.16;
Use #ifdef, not #if
 1.48  17-Oct-2008  cliff use generic enable_interrupts() and disable_interrupts() instead of
armv6-specific interrupt control ops when _ARM_ARCH_6 not defined
 1.47  15-Oct-2008  matt Add fa526_flush_prefetchbuf
 1.46  14-Oct-2008  matt Add FA526 support (compile tested only)
 1.45  27-Apr-2008  matt branches: 1.45.6;
Merge kernel changes in matt-armv6 to HEAD.
 1.44  25-Feb-2008  dogcow branches: 1.44.2; 1.44.4;
we need I32_bit, so #include <arm/armreg.h>
 1.43  24-Feb-2008  chris Micro-optimizations for arm.

Make enable and disable interrupts one instruction shorter.

Make cpu_cpwait() do nothing on anything other than an xscale, where it
will still call via the cpufuncs table.

This avoids loading a function from cpufuncs and then branching into it. On
older hardware the function does nothing, so this is just a waste of CPU
cycles.
 1.42  17-Oct-2007  garbled branches: 1.42.12; 1.42.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.41  15-Sep-2007  scw ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.
 1.40  04-Mar-2007  bjh21 branches: 1.40.2; 1.40.10; 1.40.16; 1.40.18; 1.40.20; 1.40.22;
Finally make cpufuncs work properly on acorn26, since something seems to be
using it. This entailed adding support for ARM2 and ARM2as, and allowing
for getting CPU IDs other than from CP15, since ARM2(as) doesn't have CP15.
 1.39  04-Mar-2007  bjh21 Un-__P.
 1.38  06-Jan-2007  christos branches: 1.38.2;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.37  28-Dec-2005  perry branches: 1.37.20; 1.37.24;
inline -> __inline
 1.36  24-Dec-2005  perry Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.35  11-Dec-2005  christos merge ktrace-lwp.
 1.34  04-Jul-2005  bsh branches: 1.34.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.
 1.33  03-Jun-2005  rearnsha Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.
 1.32  02-Jun-2005  uwe Drop parameter names from prototypes to avoid shadowing warnings.
 1.31  07-Aug-2004  rearnsha Changing the interrupt mask is a scheduling barrier.
 1.30  26-Jan-2004  rearnsha Switch the ARM9 to using the Dcache in write-back mode. Avoid an
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).

When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).
 1.29  06-Sep-2003  rearnsha Add processor-specific declarations for ARM10 class processors.
 1.28  06-Sep-2003  rearnsha Fix declarations of primary cache variables, so that they are
declarations, not definitions.
 1.27  23-May-2003  ichiro branches: 1.27.2;
support IXP425 Intel Network Processor
running on BigEndian
 1.26  14-Aug-2002  thorpej Garbage-collect some unused routines.
 1.25  14-Aug-2002  briggs Inline SetCPSR calls where it seems prudent to do so. This avoids two
branches and allows the compiler to better utilize registers around
calls to disable/enable/restore_interrupts().
 1.24  15-Jul-2002  ichiro add support for ixp12x0
 1.23  03-May-2002  rjs branches: 1.23.2; 1.23.4;
Use processor specific versions of ARM cache control functions for SA1100
and SA1110 instead of using SA110 ones.

Rename common StrongARM functions from sa110_* to sa1_*.

Reviewed by Jason Thorpe.
 1.22  03-May-2002  thorpej Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
 1.21  12-Apr-2002  thorpej Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.
 1.20  09-Apr-2002  thorpej * Move the code that cleans the XScale mini-data cache into its
own function.
* Add a new function which sets up the mini-data cache clean area
properly.
 1.19  26-Mar-2002  thorpej Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.
 1.18  30-Jan-2002  thorpej Add prototype for sa11x0_cpu_sleep().
 1.17  25-Jan-2002  thorpej Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.
 1.16  24-Jan-2002  briggs Two changes for XScale:
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.
 1.15  20-Dec-2001  thorpej * Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.
 1.14  29-Nov-2001  thorpej Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.
 1.13  28-Nov-2001  thorpej Add prototypes for new XScale write-through cache routines.
 1.12  19-Nov-2001  thorpej Add a "cpwait" cpufunc, currently a nullop on all but XScale.
"cpwait" ensures that all coprocessor operations have completed
before returning.
 1.11  14-Nov-2001  thorpej branches: 1.11.2;
* Give the XScale its own cpu_control() entry point; we have to flush
the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
manual (section 5.1, Branch Target Buffer Operation) notes that
manual software management of the BTB is unnecessary; it is flushed
implicitly when:
* processor resets
* FCSE process ID is written
* I-cache is invalidated
 1.10  18-Oct-2001  rearnsha Add support calls for ARM9.

Where ARM9, StrongARM and XScale share the same function, rename it
as armv4_XXX.
 1.9  14-Oct-2001  bjh21 Make the declaration of get_pc_str_offset() into a prototype.
 1.8  26-Aug-2001  matt Add xscale cpu functions
 1.7  20-Aug-2001  wiz Fix typo in comment (suceed).
 1.6  05-Jun-2001  bjh21 branches: 1.6.2;
Add get_pc_str_offset(), which returns the offset between the address of an
instruction that stores the program counter and the value of PC that's stored.
This can vary between ARM implementations, but is guaranteed to be constant on
a given one.
 1.5  03-Jun-2001  chris Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.
 1.4  02-Jun-2001  bjh21 Replace arm6_dataabt_fixup() and arm7_dataabt_fixup() with early_abort_fixup()
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type. This cleans up the code and makes it smaller. Only tested on an
ARM6 -- I can't find my ARM710a card right now.
 1.3  02-Jun-2001  bjh21 Initial cpufunc operations for ARM3. Not actually used yet.
 1.2  06-Mar-2001  bjh21 branches: 1.2.2;
Create cpufunc_null_fixup() to replace all the CPU-specific abort-fixup
routines that did nothing.
 1.1  23-Feb-2001  reinoud branches: 1.1.2;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.
 1.1.2.2  21-Jun-2001  nathanw Catch up to -current.
 1.1.2.1  09-Apr-2001  nathanw Catch up with -current.
 1.2.2.2  12-Mar-2001  bouyer Sync with HEAD.
 1.2.2.1  06-Mar-2001  bouyer file cpufunc.h was added on branch thorpej_scsipi on 2001-03-12 13:27:21 +0000
 1.6.2.6  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.6.2.5  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.6.2.4  11-Feb-2002  jdolecek Sync w/ -current.
 1.6.2.3  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.6.2.2  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.6.2.1  25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.11.2.8  19-Aug-2002  thorpej Partial (ARM only) sync with trunk -- significant performance improvements
for XScale-based systems.
 1.11.2.7  01-Aug-2002  nathanw Catch up to -current.
 1.11.2.6  20-Jun-2002  nathanw Catch up to -current.
 1.11.2.5  17-Apr-2002  nathanw Catch up to -current.
 1.11.2.4  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.11.2.3  28-Feb-2002  nathanw Catch up to -current.
 1.11.2.2  08-Jan-2002  nathanw Catch up to -current.
 1.11.2.1  14-Nov-2001  nathanw file cpufunc.h was added on branch nathanw_sa on 2002-01-08 00:23:11 +0000
 1.23.4.1  18-Nov-2002  he Pull up revision 1.26 (requested by thorpej in ticket #682):
Garbage-collect some unused routines.
 1.23.2.2  30-Aug-2002  gehenna catch up with -current.
 1.23.2.1  21-Jul-2002  gehenna catch up with -current.
 1.27.2.5  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.27.2.4  21-Sep-2004  skrll Fix the sync with head I botched.
 1.27.2.3  18-Sep-2004  skrll Sync with HEAD.
 1.27.2.2  12-Aug-2004  skrll Sync with HEAD.
 1.27.2.1  03-Aug-2004  skrll Sync with HEAD
 1.34.2.5  27-Feb-2008  yamt sync with head.
 1.34.2.4  27-Oct-2007  yamt sync with head.
 1.34.2.3  03-Sep-2007  yamt sync with head.
 1.34.2.2  26-Feb-2007  yamt sync with head.
 1.34.2.1  21-Jun-2006  yamt sync with head.
 1.37.24.1  21-Feb-2007  snj branches: 1.37.24.1.4;
Pull up following revision(s) (requested by matt in ticket #457):
sys/arch/arm/include/cpufunc.h: revision 1.38
sys/arch/arm/arm/cpufunc.c: revision 1.78
sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
sys/arch/arm/include/armreg.h: revision 1.37
sys/arch/arm/arm32/cpu.c: revision 1.64
sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
sys/arch/arm/include/cpuconf.h: revision 1.13
sys/arch/arm/conf/files.arm: revision 1.82
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.37.24.1.4.1  10-Nov-2007  matt Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc
 1.37.20.1  12-Jan-2007  ad Sync with head.
 1.38.2.1  12-Mar-2007  rmind Sync with HEAD.
 1.40.22.5  23-Mar-2008  matt sync with HEAD
 1.40.22.4  08-Nov-2007  matt sync with -HEAD
 1.40.22.3  06-Nov-2007  matt sync with HEAD
 1.40.22.2  12-Oct-2007  matt Import TI OMAP 2430 and ARM11/ARMv6 support. Now on ARMv6, the cache is
no longer purged on context switches.
 1.40.22.1  29-Aug-2007  matt Make arm11 use the armv6 cpufuncs.
 1.40.20.3  21-Mar-2008  chris Sync with head.
 1.40.20.2  20-Jan-2008  chris Sync to HEAD.
 1.40.20.1  01-Jan-2008  chris Sync with HEAD.
 1.40.18.1  02-Oct-2007  joerg Sync with HEAD.
 1.40.16.2  28-Feb-2008  rjs Sync with HEAD.
 1.40.16.1  01-Nov-2007  rjs Sync with HEAD.
 1.40.10.1  03-Oct-2007  garbled Sync with HEAD
 1.40.2.1  09-Oct-2007  ad Sync with head.
 1.42.16.3  17-Jan-2009  mjf Sync with HEAD.
 1.42.16.2  02-Jun-2008  mjf Sync with HEAD.
 1.42.16.1  03-Apr-2008  mjf Sync with HEAD.
 1.42.12.1  24-Mar-2008  keiichi sync with head.
 1.44.4.4  09-Oct-2010  yamt sync with head
 1.44.4.3  11-Aug-2010  yamt sync with head.
 1.44.4.2  04-May-2009  yamt sync with head.
 1.44.4.1  16-May-2008  yamt sync with head.
 1.44.2.1  18-May-2008  yamt sync with head.
 1.45.6.2  13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.45.6.1  19-Oct-2008  haad Sync with HEAD.
 1.49.16.3  21-Apr-2011  rmind sync with head
 1.49.16.2  05-Mar-2011  rmind sync with head
 1.49.16.1  03-Jul-2010  rmind sync with head
 1.49.14.2  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.49.14.1  17-Aug-2010  uebayasi Sync with HEAD.
 1.49.12.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.52.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.53.8.1  18-Feb-2012  mrg merge to -current.
 1.53.4.4  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.53.4.3  16-Jan-2013  yamt sync with (a bit old) head
 1.53.4.2  30-Oct-2012  yamt sync with head
 1.53.4.1  17-Apr-2012  yamt sync with head
 1.54.2.1  09-Aug-2012  jdc branches: 1.54.2.1.2;
Pull up revisions:
src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
src/sys/arch/arm/arm32/cpu.c revision 1.79
src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
src/sys/arch/arm/arm32/pmap.c revision 1.229
src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
src/sys/arch/arm/include/cpu.h revision 1.64
src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
src/sys/arch/arm/conf/files.arm revision 1.106
src/sys/arch/arm/include/cpufunc.h revision 1.57
src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
src/sys/arch/evbarm/Makefile revision 1.9
src/sys/arch/evbarm/conf/RPI revision 1.1
src/sys/arch/evbarm/conf/files.rpi revision 1.1
src/sys/arch/evbarm/conf/mk.rpi revision 1.1
src/sys/arch/evbarm/conf/std.rpi revision 1.1
src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
src/sys/arch/evbarm/rpi/rpi.h revision 1.1
src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t. Update the locking to match
com(4) in the few places it didn't already.

DOH. Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.
 1.54.2.1.2.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.59.2.4  03-Dec-2017  jdolecek update from HEAD
 1.59.2.3  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.59.2.2  23-Jun-2013  tls resync from head
 1.59.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.64.2.1  18-May-2014  rmind sync with head
 1.70.2.1  10-Aug-2014  tls Rebase.
 1.74.4.3  05-Oct-2016  skrll Sync with HEAD
 1.74.4.2  19-Mar-2016  skrll Sync with HEAD
 1.74.4.1  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.76.2.1  26-Jul-2016  pgoyette Sync with HEAD
 1.78.2.4  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.78.2.3  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.78.2.2  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.78.2.1  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.79.2.1  10-Jun-2019  christos Sync with HEAD
 1.85.2.2  03-Apr-2021  thorpej Sync with HEAD.
 1.85.2.1  14-Dec-2020  thorpej Sync w/ HEAD.
 1.90.12.1  01-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #40):

sys/arch/arm/include/cpufunc.h: revision 1.92
sys/arch/arm/arm32/bus_dma.c: revision 1.150

arm: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59654

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

A new indrection is introduced to deal with the differencs in barrier
(dsb) options between Arm V8 and V7, the lack of options in Arm V6,
and the need to use cpu_drain_writebuf for all other earlier versions.

The Arm V8 Net change is:
op old new
 1.90.4.1  01-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #1166):

sys/arch/arm/arm32/bus_dma.c: revision 1.142
sys/arch/arm/include/cpufunc.h: revision 1.92
sys/arch/arm/arm32/bus_dma.c: revision 1.150

More KNF


arm: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59654

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.

These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

A new indrection is introduced to deal with the differencs in barrier
(dsb) options between Arm V8 and V7, the lack of options in Arm V6,
and the need to use cpu_drain_writebuf for all other earlier versions.

The Arm V8 Net change is:
op old new

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