cpufunc.h revision 1.18
1 /* $NetBSD: cpufunc.h,v 1.18 2002/01/30 00:36:32 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #include <sys/types.h> 46 47 #ifdef _KERNEL 48 #ifndef _LKM 49 #include "opt_cputypes.h" 50 #endif 51 52 struct cpu_functions { 53 54 /* CPU functions */ 55 56 u_int (*cf_id) __P((void)); 57 void (*cf_cpwait) __P((void)); 58 59 /* MMU functions */ 60 61 u_int (*cf_control) __P((u_int bic, u_int eor)); 62 void (*cf_domains) __P((u_int domains)); 63 void (*cf_setttb) __P((u_int ttb)); 64 u_int (*cf_faultstatus) __P((void)); 65 u_int (*cf_faultaddress) __P((void)); 66 67 /* TLB functions */ 68 69 void (*cf_tlb_flushID) __P((void)); 70 void (*cf_tlb_flushID_SE) __P((u_int va)); 71 void (*cf_tlb_flushI) __P((void)); 72 void (*cf_tlb_flushI_SE) __P((u_int va)); 73 void (*cf_tlb_flushD) __P((void)); 74 void (*cf_tlb_flushD_SE) __P((u_int va)); 75 76 /* 77 * Cache operations: 78 * 79 * We define the following primitives: 80 * 81 * icache_sync_all Synchronize I-cache 82 * icache_sync_range Synchronize I-cache range 83 * 84 * dcache_wbinv_all Write-back and Invalidate D-cache 85 * dcache_wbinv_range Write-back and Invalidate D-cache range 86 * dcache_inv_range Invalidate D-cache range 87 * dcache_wb_range Write-back D-cache range 88 * 89 * idcache_wbinv_all Write-back and Invalidate D-cache, 90 * Invalidate I-cache 91 * idcache_wbinv_range Write-back and Invalidate D-cache, 92 * Invalidate I-cache range 93 * 94 * Note that the ARM term for "write-back" is "clean". We use 95 * the term "write-back" since it's a more common way to describe 96 * the operation. 97 * 98 * There are some rules that must be followed: 99 * 100 * I-cache Synch (all or range): 101 * The goal is to synchronize the instruction stream, 102 * so you may beed to write-back dirty D-cache blocks 103 * first. If a range is requested, and you can't 104 * synchronize just a range, you have to hit the whole 105 * thing. 106 * 107 * D-cache Write-Back and Invalidate range: 108 * If you can't WB-Inv a range, you must WB-Inv the 109 * entire D-cache. 110 * 111 * D-cache Invalidate: 112 * If you can't Inv the D-cache, you must Write-Back 113 * and Invalidate. Code that uses this operation 114 * MUST NOT assume that the D-cache will not be written 115 * back to memory. 116 * 117 * D-cache Write-Back: 118 * If you can't Write-back without doing an Inv, 119 * that's fine. Then treat this as a WB-Inv. 120 * Skipping the invalidate is merely an optimization. 121 * 122 * All operations: 123 * Valid virtual addresses must be passed to each 124 * cache operation. 125 */ 126 void (*cf_icache_sync_all) __P((void)); 127 void (*cf_icache_sync_range) __P((vaddr_t, vsize_t)); 128 129 void (*cf_dcache_wbinv_all) __P((void)); 130 void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t)); 131 void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t)); 132 void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t)); 133 134 void (*cf_idcache_wbinv_all) __P((void)); 135 void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t)); 136 137 /* Other functions */ 138 139 void (*cf_flush_prefetchbuf) __P((void)); 140 void (*cf_drain_writebuf) __P((void)); 141 void (*cf_flush_brnchtgt_C) __P((void)); 142 void (*cf_flush_brnchtgt_E) __P((u_int va)); 143 144 void (*cf_sleep) __P((int mode)); 145 146 /* Soft functions */ 147 148 int (*cf_dataabt_fixup) __P((void *arg)); 149 int (*cf_prefetchabt_fixup) __P((void *arg)); 150 151 void (*cf_context_switch) __P((void)); 152 153 void (*cf_setup) __P((char *string)); 154 }; 155 156 extern struct cpu_functions cpufuncs; 157 extern u_int cputype; 158 159 #define cpu_id() cpufuncs.cf_id() 160 #define cpu_cpwait() cpufuncs.cf_cpwait() 161 162 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 163 #define cpu_domains(d) cpufuncs.cf_domains(d) 164 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 165 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 166 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 167 168 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 169 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 170 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 171 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 172 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 173 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 174 175 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 176 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 177 178 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 179 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 180 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 181 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 182 183 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 184 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 185 186 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 187 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 188 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 189 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 190 191 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 192 193 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 194 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 195 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 196 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 197 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 198 199 #define cpu_setup(a) cpufuncs.cf_setup(a) 200 201 int set_cpufuncs __P((void)); 202 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205 void cpufunc_nullop __P((void)); 206 int cpufunc_null_fixup __P((void *)); 207 int early_abort_fixup __P((void *)); 208 int late_abort_fixup __P((void *)); 209 u_int cpufunc_id __P((void)); 210 u_int cpufunc_control __P((u_int clear, u_int bic)); 211 void cpufunc_domains __P((u_int domains)); 212 u_int cpufunc_faultstatus __P((void)); 213 u_int cpufunc_faultaddress __P((void)); 214 215 #ifdef CPU_ARM3 216 u_int arm3_control __P((u_int clear, u_int bic)); 217 void arm3_cache_flush __P((void)); 218 #endif /* CPU_ARM3 */ 219 220 #if defined(CPU_ARM6) || defined(CPU_ARM7) 221 void arm67_setttb __P((u_int ttb)); 222 void arm67_tlb_flush __P((void)); 223 void arm67_tlb_purge __P((u_int va)); 224 void arm67_cache_flush __P((void)); 225 void arm67_context_switch __P((void)); 226 #endif /* CPU_ARM6 || CPU_ARM7 */ 227 228 #ifdef CPU_ARM6 229 void arm6_setup __P((char *string)); 230 #endif /* CPU_ARM6 */ 231 232 #ifdef CPU_ARM7 233 void arm7_setup __P((char *string)); 234 #endif /* CPU_ARM7 */ 235 236 #ifdef CPU_ARM7TDMI 237 int arm7_dataabt_fixup __P((void *arg)); 238 void arm7tdmi_setup __P((char *string)); 239 void arm7tdmi_setttb __P((u_int ttb)); 240 void arm7tdmi_tlb_flushID __P((void)); 241 void arm7tdmi_tlb_flushID_SE __P((u_int va)); 242 void arm7tdmi_cache_flushID __P((void)); 243 void arm7tdmi_context_switch __P((void)); 244 #endif /* CPU_ARM7TDMI */ 245 246 #ifdef CPU_ARM8 247 void arm8_setttb __P((u_int ttb)); 248 void arm8_tlb_flushID __P((void)); 249 void arm8_tlb_flushID_SE __P((u_int va)); 250 void arm8_cache_flushID __P((void)); 251 void arm8_cache_flushID_E __P((u_int entry)); 252 void arm8_cache_cleanID __P((void)); 253 void arm8_cache_cleanID_E __P((u_int entry)); 254 void arm8_cache_purgeID __P((void)); 255 void arm8_cache_purgeID_E __P((u_int entry)); 256 257 void arm8_cache_syncI __P((void)); 258 void arm8_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); 259 void arm8_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); 260 void arm8_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); 261 void arm8_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); 262 void arm8_cache_syncI_rng __P((vaddr_t start, vsize_t end)); 263 264 void arm8_context_switch __P((void)); 265 266 void arm8_setup __P((char *string)); 267 268 u_int arm8_clock_config __P((u_int, u_int)); 269 #endif 270 271 #ifdef CPU_ARM9 272 void arm9_setttb __P((u_int)); 273 274 void arm9_tlb_flushID_SE __P((u_int va)); 275 276 void arm9_cache_flushID __P((void)); 277 void arm9_cache_flushID_SE __P((u_int)); 278 void arm9_cache_flushI __P((void)); 279 void arm9_cache_flushI_SE __P((u_int)); 280 void arm9_cache_flushD __P((void)); 281 void arm9_cache_flushD_SE __P((u_int)); 282 283 void arm9_cache_cleanID __P((void)); 284 285 void arm9_cache_syncI __P((void)); 286 void arm9_cache_flushID_rng __P((vaddr_t, vsize_t)); 287 void arm9_cache_flushD_rng __P((vaddr_t, vsize_t)); 288 void arm9_cache_syncI_rng __P((vaddr_t, vsize_t)); 289 290 void arm9_context_switch __P((void)); 291 292 void arm9_setup __P((char *string)); 293 #endif 294 295 #if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE) 296 void armv4_tlb_flushID __P((void)); 297 void armv4_tlb_flushI __P((void)); 298 void armv4_tlb_flushD __P((void)); 299 void armv4_tlb_flushD_SE __P((u_int va)); 300 301 void armv4_drain_writebuf __P((void)); 302 #endif 303 304 #ifdef CPU_SA110 305 void sa110_setttb __P((u_int ttb)); 306 307 void sa11x0_cpu_sleep __P((int mode)); 308 309 void sa110_tlb_flushID_SE __P((u_int va)); 310 311 void sa110_cache_flushID __P((void)); 312 void sa110_cache_flushI __P((void)); 313 void sa110_cache_flushD __P((void)); 314 void sa110_cache_flushD_SE __P((u_int entry)); 315 316 void sa110_cache_cleanID __P((void)); 317 void sa110_cache_cleanD __P((void)); 318 void sa110_cache_cleanD_E __P((u_int entry)); 319 320 void sa110_cache_purgeID __P((void)); 321 void sa110_cache_purgeID_E __P((u_int entry)); 322 void sa110_cache_purgeD __P((void)); 323 void sa110_cache_purgeD_E __P((u_int entry)); 324 325 void sa110_cache_syncI __P((void)); 326 void sa110_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); 327 void sa110_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); 328 void sa110_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); 329 void sa110_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); 330 void sa110_cache_syncI_rng __P((vaddr_t start, vsize_t end)); 331 332 void sa110_context_switch __P((void)); 333 334 void sa110_setup __P((char *string)); 335 #endif /* CPU_SA110 */ 336 337 #ifdef CPU_XSCALE 338 void xscale_cpwait __P((void)); 339 340 void xscale_cpu_sleep __P((int mode)); 341 342 u_int xscale_control __P((u_int clear, u_int bic)); 343 344 void xscale_setttb __P((u_int ttb)); 345 346 void xscale_tlb_flushID_SE __P((u_int va)); 347 348 void xscale_cache_flushID __P((void)); 349 void xscale_cache_flushI __P((void)); 350 void xscale_cache_flushD __P((void)); 351 void xscale_cache_flushD_SE __P((u_int entry)); 352 353 void xscale_cache_cleanID __P((void)); 354 void xscale_cache_cleanD __P((void)); 355 void xscale_cache_cleanD_E __P((u_int entry)); 356 357 void xscale_cache_purgeID __P((void)); 358 void xscale_cache_purgeID_E __P((u_int entry)); 359 void xscale_cache_purgeD __P((void)); 360 void xscale_cache_purgeD_E __P((u_int entry)); 361 362 void xscale_cache_syncI __P((void)); 363 void xscale_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); 364 void xscale_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); 365 void xscale_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); 366 void xscale_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); 367 void xscale_cache_syncI_rng __P((vaddr_t start, vsize_t end)); 368 369 /* Used in write-through mode. */ 370 void xscale_cache_flushID_rng __P((vaddr_t start, vsize_t end)); 371 void xscale_cache_flushD_rng __P((vaddr_t start, vsize_t end)); 372 void xscale_cache_flushI_rng __P((vaddr_t start, vsize_t end)); 373 374 void xscale_context_switch __P((void)); 375 376 void xscale_setup __P((char *string)); 377 #endif /* CPU_XSCALE */ 378 379 #define tlb_flush cpu_tlb_flushID 380 #define setttb cpu_setttb 381 #define drain_writebuf cpu_drain_writebuf 382 383 /* 384 * Macros for manipulating CPU interrupts 385 */ 386 #ifdef __PROG32 387 #define disable_interrupts(mask) \ 388 (SetCPSR((mask) & (I32_bit | F32_bit), (mask) & (I32_bit | F32_bit))) 389 390 #define enable_interrupts(mask) \ 391 (SetCPSR((mask) & (I32_bit | F32_bit), 0)) 392 393 #define restore_interrupts(old_cpsr) \ 394 (SetCPSR((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 395 #else /* ! __PROG32 */ 396 #define disable_interrupts(mask) \ 397 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 398 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 399 400 #define enable_interrupts(mask) \ 401 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 402 403 #define restore_interrupts(old_r15) \ 404 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 405 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 406 #endif /* __PROG32 */ 407 408 #ifdef __PROG32 409 /* Functions to manipulate the CPSR. */ 410 u_int SetCPSR(u_int bic, u_int eor); 411 u_int GetCPSR(void); 412 #else 413 /* Functions to manipulate the processor control bits in r15. */ 414 u_int set_r15(u_int bic, u_int eor); 415 u_int get_r15(void); 416 #endif /* __PROG32 */ 417 418 /* 419 * Functions to manipulate cpu r13 420 * (in arm/arm32/setstack.S) 421 */ 422 423 void set_stackptr __P((u_int mode, u_int address)); 424 u_int get_stackptr __P((u_int mode)); 425 426 /* 427 * Miscellany 428 */ 429 430 int get_pc_str_offset __P((void)); 431 432 /* 433 * CPU functions from locore.S 434 */ 435 436 void cpu_reset __P((void)) __attribute__((__noreturn__)); 437 438 /* 439 * Cache info variables. 440 */ 441 442 /* PRIMARY CACHE VARIABLES */ 443 int arm_picache_size; 444 int arm_picache_line_size; 445 int arm_picache_ways; 446 447 int arm_pdcache_size; /* and unified */ 448 int arm_pdcache_line_size; 449 int arm_pdcache_ways; 450 451 int arm_pcache_type; 452 int arm_pcache_unified; 453 454 int arm_dcache_align; 455 int arm_dcache_align_mask; 456 457 #endif /* _KERNEL */ 458 #endif /* _ARM32_CPUFUNC_H_ */ 459 460 /* End of cpufunc.h */ 461
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