cpufunc.h revision 1.40
1 /* $NetBSD: cpufunc.h,v 1.40 2007/03/04 14:47:18 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #ifdef _KERNEL 46 47 #include <sys/types.h> 48 #include <arm/cpuconf.h> 49 50 struct cpu_functions { 51 52 /* CPU functions */ 53 54 u_int (*cf_id) (void); 55 void (*cf_cpwait) (void); 56 57 /* MMU functions */ 58 59 u_int (*cf_control) (u_int, u_int); 60 void (*cf_domains) (u_int); 61 void (*cf_setttb) (u_int); 62 u_int (*cf_faultstatus) (void); 63 u_int (*cf_faultaddress) (void); 64 65 /* TLB functions */ 66 67 void (*cf_tlb_flushID) (void); 68 void (*cf_tlb_flushID_SE) (u_int); 69 void (*cf_tlb_flushI) (void); 70 void (*cf_tlb_flushI_SE) (u_int); 71 void (*cf_tlb_flushD) (void); 72 void (*cf_tlb_flushD_SE) (u_int); 73 74 /* 75 * Cache operations: 76 * 77 * We define the following primitives: 78 * 79 * icache_sync_all Synchronize I-cache 80 * icache_sync_range Synchronize I-cache range 81 * 82 * dcache_wbinv_all Write-back and Invalidate D-cache 83 * dcache_wbinv_range Write-back and Invalidate D-cache range 84 * dcache_inv_range Invalidate D-cache range 85 * dcache_wb_range Write-back D-cache range 86 * 87 * idcache_wbinv_all Write-back and Invalidate D-cache, 88 * Invalidate I-cache 89 * idcache_wbinv_range Write-back and Invalidate D-cache, 90 * Invalidate I-cache range 91 * 92 * Note that the ARM term for "write-back" is "clean". We use 93 * the term "write-back" since it's a more common way to describe 94 * the operation. 95 * 96 * There are some rules that must be followed: 97 * 98 * I-cache Synch (all or range): 99 * The goal is to synchronize the instruction stream, 100 * so you may beed to write-back dirty D-cache blocks 101 * first. If a range is requested, and you can't 102 * synchronize just a range, you have to hit the whole 103 * thing. 104 * 105 * D-cache Write-Back and Invalidate range: 106 * If you can't WB-Inv a range, you must WB-Inv the 107 * entire D-cache. 108 * 109 * D-cache Invalidate: 110 * If you can't Inv the D-cache, you must Write-Back 111 * and Invalidate. Code that uses this operation 112 * MUST NOT assume that the D-cache will not be written 113 * back to memory. 114 * 115 * D-cache Write-Back: 116 * If you can't Write-back without doing an Inv, 117 * that's fine. Then treat this as a WB-Inv. 118 * Skipping the invalidate is merely an optimization. 119 * 120 * All operations: 121 * Valid virtual addresses must be passed to each 122 * cache operation. 123 */ 124 void (*cf_icache_sync_all) (void); 125 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 126 127 void (*cf_dcache_wbinv_all) (void); 128 void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t); 129 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 130 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 131 132 void (*cf_idcache_wbinv_all) (void); 133 void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t); 134 135 /* Other functions */ 136 137 void (*cf_flush_prefetchbuf) (void); 138 void (*cf_drain_writebuf) (void); 139 void (*cf_flush_brnchtgt_C) (void); 140 void (*cf_flush_brnchtgt_E) (u_int); 141 142 void (*cf_sleep) (int mode); 143 144 /* Soft functions */ 145 146 int (*cf_dataabt_fixup) (void *); 147 int (*cf_prefetchabt_fixup) (void *); 148 149 void (*cf_context_switch) (void); 150 151 void (*cf_setup) (char *); 152 }; 153 154 extern struct cpu_functions cpufuncs; 155 extern u_int cputype; 156 157 #define cpu_id() cpufuncs.cf_id() 158 #define cpu_cpwait() cpufuncs.cf_cpwait() 159 160 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 161 #define cpu_domains(d) cpufuncs.cf_domains(d) 162 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 163 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 164 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 165 166 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 167 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 168 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 169 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 170 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 171 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 172 173 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 174 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 175 176 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 177 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 178 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 179 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 180 181 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 182 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 183 184 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 185 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 186 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 187 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 188 189 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 190 191 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 192 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 193 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 194 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 195 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 196 197 #define cpu_setup(a) cpufuncs.cf_setup(a) 198 199 int set_cpufuncs (void); 200 int set_cpufuncs_id (u_int); 201 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 202 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 203 204 void cpufunc_nullop (void); 205 int cpufunc_null_fixup (void *); 206 int early_abort_fixup (void *); 207 int late_abort_fixup (void *); 208 u_int cpufunc_id (void); 209 u_int cpufunc_control (u_int, u_int); 210 void cpufunc_domains (u_int); 211 u_int cpufunc_faultstatus (void); 212 u_int cpufunc_faultaddress (void); 213 214 #ifdef CPU_ARM2 215 u_int arm2_id (void); 216 #endif /* CPU_ARM2 */ 217 218 #ifdef CPU_ARM250 219 u_int arm250_id (void); 220 #endif 221 222 #ifdef CPU_ARM3 223 u_int arm3_control (u_int, u_int); 224 void arm3_cache_flush (void); 225 #endif /* CPU_ARM3 */ 226 227 #if defined(CPU_ARM6) || defined(CPU_ARM7) 228 void arm67_setttb (u_int); 229 void arm67_tlb_flush (void); 230 void arm67_tlb_purge (u_int); 231 void arm67_cache_flush (void); 232 void arm67_context_switch (void); 233 #endif /* CPU_ARM6 || CPU_ARM7 */ 234 235 #ifdef CPU_ARM6 236 void arm6_setup (char *); 237 #endif /* CPU_ARM6 */ 238 239 #ifdef CPU_ARM7 240 void arm7_setup (char *); 241 #endif /* CPU_ARM7 */ 242 243 #ifdef CPU_ARM7TDMI 244 int arm7_dataabt_fixup (void *); 245 void arm7tdmi_setup (char *); 246 void arm7tdmi_setttb (u_int); 247 void arm7tdmi_tlb_flushID (void); 248 void arm7tdmi_tlb_flushID_SE (u_int); 249 void arm7tdmi_cache_flushID (void); 250 void arm7tdmi_context_switch (void); 251 #endif /* CPU_ARM7TDMI */ 252 253 #ifdef CPU_ARM8 254 void arm8_setttb (u_int); 255 void arm8_tlb_flushID (void); 256 void arm8_tlb_flushID_SE (u_int); 257 void arm8_cache_flushID (void); 258 void arm8_cache_flushID_E (u_int); 259 void arm8_cache_cleanID (void); 260 void arm8_cache_cleanID_E (u_int); 261 void arm8_cache_purgeID (void); 262 void arm8_cache_purgeID_E (u_int entry); 263 264 void arm8_cache_syncI (void); 265 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 266 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 267 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 268 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 269 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 270 271 void arm8_context_switch (void); 272 273 void arm8_setup (char *); 274 275 u_int arm8_clock_config (u_int, u_int); 276 #endif 277 278 #ifdef CPU_SA110 279 void sa110_setup (char *); 280 void sa110_context_switch (void); 281 #endif /* CPU_SA110 */ 282 283 #if defined(CPU_SA1100) || defined(CPU_SA1110) 284 void sa11x0_drain_readbuf (void); 285 286 void sa11x0_context_switch (void); 287 void sa11x0_cpu_sleep (int); 288 289 void sa11x0_setup (char *); 290 #endif 291 292 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 293 void sa1_setttb (u_int); 294 295 void sa1_tlb_flushID_SE (u_int); 296 297 void sa1_cache_flushID (void); 298 void sa1_cache_flushI (void); 299 void sa1_cache_flushD (void); 300 void sa1_cache_flushD_SE (u_int); 301 302 void sa1_cache_cleanID (void); 303 void sa1_cache_cleanD (void); 304 void sa1_cache_cleanD_E (u_int); 305 306 void sa1_cache_purgeID (void); 307 void sa1_cache_purgeID_E (u_int); 308 void sa1_cache_purgeD (void); 309 void sa1_cache_purgeD_E (u_int); 310 311 void sa1_cache_syncI (void); 312 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 313 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 314 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 315 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 316 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 317 318 #endif 319 320 #ifdef CPU_ARM9 321 void arm9_setttb (u_int); 322 323 void arm9_tlb_flushID_SE (u_int); 324 325 void arm9_icache_sync_all (void); 326 void arm9_icache_sync_range (vaddr_t, vsize_t); 327 328 void arm9_dcache_wbinv_all (void); 329 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 330 void arm9_dcache_inv_range (vaddr_t, vsize_t); 331 void arm9_dcache_wb_range (vaddr_t, vsize_t); 332 333 void arm9_idcache_wbinv_all (void); 334 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 335 336 void arm9_context_switch (void); 337 338 void arm9_setup (char *); 339 340 extern unsigned arm9_dcache_sets_max; 341 extern unsigned arm9_dcache_sets_inc; 342 extern unsigned arm9_dcache_index_max; 343 extern unsigned arm9_dcache_index_inc; 344 #endif 345 346 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 347 void arm10_tlb_flushID_SE (u_int); 348 void arm10_tlb_flushI_SE (u_int); 349 350 void arm10_context_switch (void); 351 352 void arm10_setup (char *); 353 #endif 354 355 #ifdef CPU_ARM11 356 void arm11_setttb (u_int); 357 358 void arm11_tlb_flushID_SE (u_int); 359 void arm11_tlb_flushI_SE (u_int); 360 361 void arm11_context_switch (void); 362 363 void arm11_setup (char *string); 364 void arm11_tlb_flushID (void); 365 void arm11_tlb_flushI (void); 366 void arm11_tlb_flushD (void); 367 void arm11_tlb_flushD_SE (u_int va); 368 369 void arm11_drain_writebuf (void); 370 #endif 371 372 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 373 void armv5_ec_setttb (u_int); 374 375 void armv5_ec_icache_sync_all (void); 376 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 377 378 void armv5_ec_dcache_wbinv_all (void); 379 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 380 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 381 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 382 383 void armv5_ec_idcache_wbinv_all (void); 384 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 385 #endif 386 387 #if defined (CPU_ARM10) || defined (CPU_ARM11) 388 void armv5_setttb (u_int); 389 390 void armv5_icache_sync_all (void); 391 void armv5_icache_sync_range (vaddr_t, vsize_t); 392 393 void armv5_dcache_wbinv_all (void); 394 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 395 void armv5_dcache_inv_range (vaddr_t, vsize_t); 396 void armv5_dcache_wb_range (vaddr_t, vsize_t); 397 398 void armv5_idcache_wbinv_all (void); 399 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 400 401 extern unsigned armv5_dcache_sets_max; 402 extern unsigned armv5_dcache_sets_inc; 403 extern unsigned armv5_dcache_index_max; 404 extern unsigned armv5_dcache_index_inc; 405 #endif 406 407 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 408 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 409 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 410 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 411 412 void armv4_tlb_flushID (void); 413 void armv4_tlb_flushI (void); 414 void armv4_tlb_flushD (void); 415 void armv4_tlb_flushD_SE (u_int); 416 417 void armv4_drain_writebuf (void); 418 #endif 419 420 #if defined(CPU_IXP12X0) 421 void ixp12x0_drain_readbuf (void); 422 void ixp12x0_context_switch (void); 423 void ixp12x0_setup (char *); 424 #endif 425 426 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 427 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 428 void xscale_cpwait (void); 429 430 void xscale_cpu_sleep (int); 431 432 u_int xscale_control (u_int, u_int); 433 434 void xscale_setttb (u_int); 435 436 void xscale_tlb_flushID_SE (u_int); 437 438 void xscale_cache_flushID (void); 439 void xscale_cache_flushI (void); 440 void xscale_cache_flushD (void); 441 void xscale_cache_flushD_SE (u_int); 442 443 void xscale_cache_cleanID (void); 444 void xscale_cache_cleanD (void); 445 void xscale_cache_cleanD_E (u_int); 446 447 void xscale_cache_clean_minidata (void); 448 449 void xscale_cache_purgeID (void); 450 void xscale_cache_purgeID_E (u_int); 451 void xscale_cache_purgeD (void); 452 void xscale_cache_purgeD_E (u_int); 453 454 void xscale_cache_syncI (void); 455 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 456 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 457 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 458 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 459 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 460 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 461 462 void xscale_context_switch (void); 463 464 void xscale_setup (char *); 465 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */ 466 467 #define tlb_flush cpu_tlb_flushID 468 #define setttb cpu_setttb 469 #define drain_writebuf cpu_drain_writebuf 470 471 /* 472 * Macros for manipulating CPU interrupts 473 */ 474 #ifdef __PROG32 475 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 476 477 static __inline u_int32_t 478 __set_cpsr_c(u_int bic, u_int eor) 479 { 480 u_int32_t tmp, ret; 481 482 __asm volatile( 483 "mrs %0, cpsr\n" /* Get the CPSR */ 484 "bic %1, %0, %2\n" /* Clear bits */ 485 "eor %1, %1, %3\n" /* XOR bits */ 486 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 487 : "=&r" (ret), "=&r" (tmp) 488 : "r" (bic), "r" (eor) : "memory"); 489 490 return ret; 491 } 492 493 #define disable_interrupts(mask) \ 494 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 495 (mask) & (I32_bit | F32_bit))) 496 497 #define enable_interrupts(mask) \ 498 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 499 500 #define restore_interrupts(old_cpsr) \ 501 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 502 #else /* ! __PROG32 */ 503 #define disable_interrupts(mask) \ 504 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 505 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 506 507 #define enable_interrupts(mask) \ 508 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 509 510 #define restore_interrupts(old_r15) \ 511 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 512 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 513 #endif /* __PROG32 */ 514 515 #ifdef __PROG32 516 /* Functions to manipulate the CPSR. */ 517 u_int SetCPSR(u_int, u_int); 518 u_int GetCPSR(void); 519 #else 520 /* Functions to manipulate the processor control bits in r15. */ 521 u_int set_r15(u_int, u_int); 522 u_int get_r15(void); 523 #endif /* __PROG32 */ 524 525 /* 526 * Functions to manipulate cpu r13 527 * (in arm/arm32/setstack.S) 528 */ 529 530 void set_stackptr (u_int, u_int); 531 u_int get_stackptr (u_int); 532 533 /* 534 * Miscellany 535 */ 536 537 int get_pc_str_offset (void); 538 539 /* 540 * CPU functions from locore.S 541 */ 542 543 void cpu_reset (void) __attribute__((__noreturn__)); 544 545 /* 546 * Cache info variables. 547 */ 548 549 /* PRIMARY CACHE VARIABLES */ 550 extern int arm_picache_size; 551 extern int arm_picache_line_size; 552 extern int arm_picache_ways; 553 554 extern int arm_pdcache_size; /* and unified */ 555 extern int arm_pdcache_line_size; 556 extern int arm_pdcache_ways; 557 558 extern int arm_pcache_type; 559 extern int arm_pcache_unified; 560 561 extern int arm_dcache_align; 562 extern int arm_dcache_align_mask; 563 564 #endif /* _KERNEL */ 565 #endif /* _ARM32_CPUFUNC_H_ */ 566 567 /* End of cpufunc.h */ 568
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