cpufunc.h revision 1.44
1 /* $NetBSD: cpufunc.h,v 1.44 2008/02/25 06:32:29 dogcow Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #ifdef _KERNEL 46 47 #include <sys/types.h> 48 #include <arm/cpuconf.h> 49 #include <arm/armreg.h> 50 51 struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int, u_int); 61 void (*cf_domains) (u_int); 62 void (*cf_setttb) (u_int); 63 u_int (*cf_faultstatus) (void); 64 u_int (*cf_faultaddress) (void); 65 66 /* TLB functions */ 67 68 void (*cf_tlb_flushID) (void); 69 void (*cf_tlb_flushID_SE) (u_int); 70 void (*cf_tlb_flushI) (void); 71 void (*cf_tlb_flushI_SE) (u_int); 72 void (*cf_tlb_flushD) (void); 73 void (*cf_tlb_flushD_SE) (u_int); 74 75 /* 76 * Cache operations: 77 * 78 * We define the following primitives: 79 * 80 * icache_sync_all Synchronize I-cache 81 * icache_sync_range Synchronize I-cache range 82 * 83 * dcache_wbinv_all Write-back and Invalidate D-cache 84 * dcache_wbinv_range Write-back and Invalidate D-cache range 85 * dcache_inv_range Invalidate D-cache range 86 * dcache_wb_range Write-back D-cache range 87 * 88 * idcache_wbinv_all Write-back and Invalidate D-cache, 89 * Invalidate I-cache 90 * idcache_wbinv_range Write-back and Invalidate D-cache, 91 * Invalidate I-cache range 92 * 93 * Note that the ARM term for "write-back" is "clean". We use 94 * the term "write-back" since it's a more common way to describe 95 * the operation. 96 * 97 * There are some rules that must be followed: 98 * 99 * I-cache Synch (all or range): 100 * The goal is to synchronize the instruction stream, 101 * so you may beed to write-back dirty D-cache blocks 102 * first. If a range is requested, and you can't 103 * synchronize just a range, you have to hit the whole 104 * thing. 105 * 106 * D-cache Write-Back and Invalidate range: 107 * If you can't WB-Inv a range, you must WB-Inv the 108 * entire D-cache. 109 * 110 * D-cache Invalidate: 111 * If you can't Inv the D-cache, you must Write-Back 112 * and Invalidate. Code that uses this operation 113 * MUST NOT assume that the D-cache will not be written 114 * back to memory. 115 * 116 * D-cache Write-Back: 117 * If you can't Write-back without doing an Inv, 118 * that's fine. Then treat this as a WB-Inv. 119 * Skipping the invalidate is merely an optimization. 120 * 121 * All operations: 122 * Valid virtual addresses must be passed to each 123 * cache operation. 124 */ 125 void (*cf_icache_sync_all) (void); 126 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 127 128 void (*cf_dcache_wbinv_all) (void); 129 void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t); 130 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 131 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 132 133 void (*cf_idcache_wbinv_all) (void); 134 void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t); 135 136 /* Other functions */ 137 138 void (*cf_flush_prefetchbuf) (void); 139 void (*cf_drain_writebuf) (void); 140 void (*cf_flush_brnchtgt_C) (void); 141 void (*cf_flush_brnchtgt_E) (u_int); 142 143 void (*cf_sleep) (int mode); 144 145 /* Soft functions */ 146 147 int (*cf_dataabt_fixup) (void *); 148 int (*cf_prefetchabt_fixup) (void *); 149 150 void (*cf_context_switch) (u_int); 151 152 void (*cf_setup) (char *); 153 }; 154 155 extern struct cpu_functions cpufuncs; 156 extern u_int cputype; 157 158 #define cpu_id() cpufuncs.cf_id() 159 160 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 161 #define cpu_domains(d) cpufuncs.cf_domains(d) 162 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 163 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 164 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 165 166 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 167 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 168 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 169 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 170 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 171 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 172 173 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 174 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 175 176 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 177 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 178 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 179 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 180 181 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 182 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 183 184 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 185 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 186 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 187 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 188 189 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 190 191 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 192 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 193 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 194 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 195 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 196 197 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 198 #define cpu_setup(a) cpufuncs.cf_setup(a) 199 200 int set_cpufuncs (void); 201 int set_cpufuncs_id (u_int); 202 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205 void cpufunc_nullop (void); 206 int cpufunc_null_fixup (void *); 207 int early_abort_fixup (void *); 208 int late_abort_fixup (void *); 209 u_int cpufunc_id (void); 210 u_int cpufunc_control (u_int, u_int); 211 void cpufunc_domains (u_int); 212 u_int cpufunc_faultstatus (void); 213 u_int cpufunc_faultaddress (void); 214 215 #ifdef CPU_ARM2 216 u_int arm2_id (void); 217 #endif /* CPU_ARM2 */ 218 219 #ifdef CPU_ARM250 220 u_int arm250_id (void); 221 #endif 222 223 #ifdef CPU_ARM3 224 u_int arm3_control (u_int, u_int); 225 void arm3_cache_flush (void); 226 #endif /* CPU_ARM3 */ 227 228 #if defined(CPU_ARM6) || defined(CPU_ARM7) 229 void arm67_setttb (u_int); 230 void arm67_tlb_flush (void); 231 void arm67_tlb_purge (u_int); 232 void arm67_cache_flush (void); 233 void arm67_context_switch (u_int); 234 #endif /* CPU_ARM6 || CPU_ARM7 */ 235 236 #ifdef CPU_ARM6 237 void arm6_setup (char *); 238 #endif /* CPU_ARM6 */ 239 240 #ifdef CPU_ARM7 241 void arm7_setup (char *); 242 #endif /* CPU_ARM7 */ 243 244 #ifdef CPU_ARM7TDMI 245 int arm7_dataabt_fixup (void *); 246 void arm7tdmi_setup (char *); 247 void arm7tdmi_setttb (u_int); 248 void arm7tdmi_tlb_flushID (void); 249 void arm7tdmi_tlb_flushID_SE (u_int); 250 void arm7tdmi_cache_flushID (void); 251 void arm7tdmi_context_switch (u_int); 252 #endif /* CPU_ARM7TDMI */ 253 254 #ifdef CPU_ARM8 255 void arm8_setttb (u_int); 256 void arm8_tlb_flushID (void); 257 void arm8_tlb_flushID_SE (u_int); 258 void arm8_cache_flushID (void); 259 void arm8_cache_flushID_E (u_int); 260 void arm8_cache_cleanID (void); 261 void arm8_cache_cleanID_E (u_int); 262 void arm8_cache_purgeID (void); 263 void arm8_cache_purgeID_E (u_int entry); 264 265 void arm8_cache_syncI (void); 266 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 267 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 268 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 269 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 270 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 271 272 void arm8_context_switch (u_int); 273 274 void arm8_setup (char *); 275 276 u_int arm8_clock_config (u_int, u_int); 277 #endif 278 279 #ifdef CPU_SA110 280 void sa110_setup (char *); 281 void sa110_context_switch (u_int); 282 #endif /* CPU_SA110 */ 283 284 #if defined(CPU_SA1100) || defined(CPU_SA1110) 285 void sa11x0_drain_readbuf (void); 286 287 void sa11x0_context_switch (u_int); 288 void sa11x0_cpu_sleep (int); 289 290 void sa11x0_setup (char *); 291 #endif 292 293 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 294 void sa1_setttb (u_int); 295 296 void sa1_tlb_flushID_SE (u_int); 297 298 void sa1_cache_flushID (void); 299 void sa1_cache_flushI (void); 300 void sa1_cache_flushD (void); 301 void sa1_cache_flushD_SE (u_int); 302 303 void sa1_cache_cleanID (void); 304 void sa1_cache_cleanD (void); 305 void sa1_cache_cleanD_E (u_int); 306 307 void sa1_cache_purgeID (void); 308 void sa1_cache_purgeID_E (u_int); 309 void sa1_cache_purgeD (void); 310 void sa1_cache_purgeD_E (u_int); 311 312 void sa1_cache_syncI (void); 313 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 314 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 315 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 316 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 317 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 318 319 #endif 320 321 #ifdef CPU_ARM9 322 void arm9_setttb (u_int); 323 324 void arm9_tlb_flushID_SE (u_int); 325 326 void arm9_icache_sync_all (void); 327 void arm9_icache_sync_range (vaddr_t, vsize_t); 328 329 void arm9_dcache_wbinv_all (void); 330 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 331 void arm9_dcache_inv_range (vaddr_t, vsize_t); 332 void arm9_dcache_wb_range (vaddr_t, vsize_t); 333 334 void arm9_idcache_wbinv_all (void); 335 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 336 337 void arm9_context_switch (u_int); 338 339 void arm9_setup (char *); 340 341 extern unsigned arm9_dcache_sets_max; 342 extern unsigned arm9_dcache_sets_inc; 343 extern unsigned arm9_dcache_index_max; 344 extern unsigned arm9_dcache_index_inc; 345 #endif 346 347 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 348 void arm10_tlb_flushID_SE (u_int); 349 void arm10_tlb_flushI_SE (u_int); 350 351 void arm10_context_switch (u_int); 352 353 void arm10_setup (char *); 354 #endif 355 356 #ifdef CPU_ARM11 357 void arm11_setttb (u_int); 358 359 void arm11_tlb_flushID_SE (u_int); 360 void arm11_tlb_flushI_SE (u_int); 361 362 void arm11_context_switch (u_int); 363 364 void arm11_setup (char *string); 365 void arm11_tlb_flushID (void); 366 void arm11_tlb_flushI (void); 367 void arm11_tlb_flushD (void); 368 void arm11_tlb_flushD_SE (u_int va); 369 370 void arm11_drain_writebuf (void); 371 #endif 372 373 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 374 void armv5_ec_setttb (u_int); 375 376 void armv5_ec_icache_sync_all (void); 377 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 378 379 void armv5_ec_dcache_wbinv_all (void); 380 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 381 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 382 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 383 384 void armv5_ec_idcache_wbinv_all (void); 385 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 386 #endif 387 388 #if defined (CPU_ARM10) || defined (CPU_ARM11) 389 void armv5_setttb (u_int); 390 391 void armv5_icache_sync_all (void); 392 void armv5_icache_sync_range (vaddr_t, vsize_t); 393 394 void armv5_dcache_wbinv_all (void); 395 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 396 void armv5_dcache_inv_range (vaddr_t, vsize_t); 397 void armv5_dcache_wb_range (vaddr_t, vsize_t); 398 399 void armv5_idcache_wbinv_all (void); 400 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 401 402 extern unsigned armv5_dcache_sets_max; 403 extern unsigned armv5_dcache_sets_inc; 404 extern unsigned armv5_dcache_index_max; 405 extern unsigned armv5_dcache_index_inc; 406 #endif 407 408 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 409 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 410 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 411 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 412 413 void armv4_tlb_flushID (void); 414 void armv4_tlb_flushI (void); 415 void armv4_tlb_flushD (void); 416 void armv4_tlb_flushD_SE (u_int); 417 418 void armv4_drain_writebuf (void); 419 #endif 420 421 #if defined(CPU_IXP12X0) 422 void ixp12x0_drain_readbuf (void); 423 void ixp12x0_context_switch (u_int); 424 void ixp12x0_setup (char *); 425 #endif 426 427 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 428 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 429 430 void xscale_cpwait (void); 431 #define cpu_cpwait() cpufuncs.cf_cpwait() 432 433 void xscale_cpu_sleep (int); 434 435 u_int xscale_control (u_int, u_int); 436 437 void xscale_setttb (u_int); 438 439 void xscale_tlb_flushID_SE (u_int); 440 441 void xscale_cache_flushID (void); 442 void xscale_cache_flushI (void); 443 void xscale_cache_flushD (void); 444 void xscale_cache_flushD_SE (u_int); 445 446 void xscale_cache_cleanID (void); 447 void xscale_cache_cleanD (void); 448 void xscale_cache_cleanD_E (u_int); 449 450 void xscale_cache_clean_minidata (void); 451 452 void xscale_cache_purgeID (void); 453 void xscale_cache_purgeID_E (u_int); 454 void xscale_cache_purgeD (void); 455 void xscale_cache_purgeD_E (u_int); 456 457 void xscale_cache_syncI (void); 458 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 459 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 460 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 461 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 462 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 463 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 464 465 void xscale_context_switch (u_int); 466 467 void xscale_setup (char *); 468 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */ 469 470 #define tlb_flush cpu_tlb_flushID 471 #define setttb cpu_setttb 472 #define drain_writebuf cpu_drain_writebuf 473 474 #ifndef cpu_cpwait 475 #define cpu_cpwait() 476 #endif 477 478 /* 479 * Macros for manipulating CPU interrupts 480 */ 481 #ifdef __PROG32 482 static __inline u_int32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__)); 483 static __inline u_int32_t disable_interrupts(uint32_t mask) __attribute__((__unused__)); 484 static __inline u_int32_t enable_interrupts(uint32_t mask) __attribute__((__unused__)); 485 486 static __inline uint32_t 487 __set_cpsr_c(uint32_t bic, uint32_t eor) 488 { 489 uint32_t tmp, ret; 490 491 __asm volatile( 492 "mrs %0, cpsr\n" /* Get the CPSR */ 493 "bic %1, %0, %2\n" /* Clear bits */ 494 "eor %1, %1, %3\n" /* XOR bits */ 495 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 496 : "=&r" (ret), "=&r" (tmp) 497 : "r" (bic), "r" (eor) : "memory"); 498 499 return ret; 500 } 501 502 static __inline uint32_t 503 disable_interrupts(uint32_t mask) 504 { 505 uint32_t tmp, ret; 506 mask &= (I32_bit | F32_bit); 507 508 __asm volatile( 509 "mrs %0, cpsr\n" /* Get the CPSR */ 510 "orr %1, %0, %2\n" /* set bits */ 511 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 512 : "=&r" (ret), "=&r" (tmp) 513 : "r" (mask) 514 : "memory"); 515 516 return ret; 517 } 518 519 static __inline uint32_t 520 enable_interrupts(uint32_t mask) 521 { 522 uint32_t ret, tmp; 523 mask &= (I32_bit | F32_bit); 524 525 __asm volatile( 526 "mrs %0, cpsr\n" /* Get the CPSR */ 527 "bic %1, %0, %2\n" /* Clear bits */ 528 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 529 : "=&r" (ret), "=&r" (tmp) 530 : "r" (mask) 531 : "memory"); 532 533 return ret; 534 } 535 536 #define restore_interrupts(old_cpsr) \ 537 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 538 #else /* ! __PROG32 */ 539 #define disable_interrupts(mask) \ 540 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 541 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 542 543 #define enable_interrupts(mask) \ 544 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 545 546 #define restore_interrupts(old_r15) \ 547 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 548 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 549 #endif /* __PROG32 */ 550 551 #ifdef __PROG32 552 /* Functions to manipulate the CPSR. */ 553 u_int SetCPSR(u_int, u_int); 554 u_int GetCPSR(void); 555 #else 556 /* Functions to manipulate the processor control bits in r15. */ 557 u_int set_r15(u_int, u_int); 558 u_int get_r15(void); 559 #endif /* __PROG32 */ 560 561 /* 562 * Functions to manipulate cpu r13 563 * (in arm/arm32/setstack.S) 564 */ 565 566 void set_stackptr (u_int, u_int); 567 u_int get_stackptr (u_int); 568 569 /* 570 * Miscellany 571 */ 572 573 int get_pc_str_offset (void); 574 575 /* 576 * CPU functions from locore.S 577 */ 578 579 void cpu_reset (void) __attribute__((__noreturn__)); 580 581 /* 582 * Cache info variables. 583 */ 584 585 /* PRIMARY CACHE VARIABLES */ 586 extern int arm_picache_size; 587 extern int arm_picache_line_size; 588 extern int arm_picache_ways; 589 590 extern int arm_pdcache_size; /* and unified */ 591 extern int arm_pdcache_line_size; 592 extern int arm_pdcache_ways; 593 594 extern int arm_pcache_type; 595 extern int arm_pcache_unified; 596 597 extern int arm_dcache_align; 598 extern int arm_dcache_align_mask; 599 600 #endif /* _KERNEL */ 601 #endif /* _ARM32_CPUFUNC_H_ */ 602 603 /* End of cpufunc.h */ 604
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