cpufunc.h revision 1.50
1 /* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #ifdef _KERNEL 46 47 #include <sys/types.h> 48 #include <arm/armreg.h> 49 #include <arm/cpuconf.h> 50 #include <arm/armreg.h> 51 52 struct cpu_functions { 53 54 /* CPU functions */ 55 56 u_int (*cf_id) (void); 57 void (*cf_cpwait) (void); 58 59 /* MMU functions */ 60 61 u_int (*cf_control) (u_int, u_int); 62 void (*cf_domains) (u_int); 63 void (*cf_setttb) (u_int); 64 u_int (*cf_faultstatus) (void); 65 u_int (*cf_faultaddress) (void); 66 67 /* TLB functions */ 68 69 void (*cf_tlb_flushID) (void); 70 void (*cf_tlb_flushID_SE) (u_int); 71 void (*cf_tlb_flushI) (void); 72 void (*cf_tlb_flushI_SE) (u_int); 73 void (*cf_tlb_flushD) (void); 74 void (*cf_tlb_flushD_SE) (u_int); 75 76 /* 77 * Cache operations: 78 * 79 * We define the following primitives: 80 * 81 * icache_sync_all Synchronize I-cache 82 * icache_sync_range Synchronize I-cache range 83 * 84 * dcache_wbinv_all Write-back and Invalidate D-cache 85 * dcache_wbinv_range Write-back and Invalidate D-cache range 86 * dcache_inv_range Invalidate D-cache range 87 * dcache_wb_range Write-back D-cache range 88 * 89 * idcache_wbinv_all Write-back and Invalidate D-cache, 90 * Invalidate I-cache 91 * idcache_wbinv_range Write-back and Invalidate D-cache, 92 * Invalidate I-cache range 93 * 94 * Note that the ARM term for "write-back" is "clean". We use 95 * the term "write-back" since it's a more common way to describe 96 * the operation. 97 * 98 * There are some rules that must be followed: 99 * 100 * I-cache Synch (all or range): 101 * The goal is to synchronize the instruction stream, 102 * so you may beed to write-back dirty D-cache blocks 103 * first. If a range is requested, and you can't 104 * synchronize just a range, you have to hit the whole 105 * thing. 106 * 107 * D-cache Write-Back and Invalidate range: 108 * If you can't WB-Inv a range, you must WB-Inv the 109 * entire D-cache. 110 * 111 * D-cache Invalidate: 112 * If you can't Inv the D-cache, you must Write-Back 113 * and Invalidate. Code that uses this operation 114 * MUST NOT assume that the D-cache will not be written 115 * back to memory. 116 * 117 * D-cache Write-Back: 118 * If you can't Write-back without doing an Inv, 119 * that's fine. Then treat this as a WB-Inv. 120 * Skipping the invalidate is merely an optimization. 121 * 122 * All operations: 123 * Valid virtual addresses must be passed to each 124 * cache operation. 125 */ 126 void (*cf_icache_sync_all) (void); 127 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 128 129 void (*cf_dcache_wbinv_all) (void); 130 void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t); 131 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 132 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 133 134 void (*cf_idcache_wbinv_all) (void); 135 void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t); 136 137 /* Other functions */ 138 139 void (*cf_flush_prefetchbuf) (void); 140 void (*cf_drain_writebuf) (void); 141 void (*cf_flush_brnchtgt_C) (void); 142 void (*cf_flush_brnchtgt_E) (u_int); 143 144 void (*cf_sleep) (int mode); 145 146 /* Soft functions */ 147 148 int (*cf_dataabt_fixup) (void *); 149 int (*cf_prefetchabt_fixup) (void *); 150 151 void (*cf_context_switch) (u_int); 152 153 void (*cf_setup) (char *); 154 }; 155 156 extern struct cpu_functions cpufuncs; 157 extern u_int cputype; 158 159 #define cpu_id() cpufuncs.cf_id() 160 161 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 162 #define cpu_domains(d) cpufuncs.cf_domains(d) 163 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 164 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 165 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 166 167 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 168 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 169 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 170 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 171 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 172 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 173 174 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 175 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 176 177 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 178 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 179 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 180 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 181 182 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 183 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 184 185 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 186 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 187 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 188 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 189 190 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 191 192 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 193 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 194 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 195 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 196 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 197 198 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 199 #define cpu_setup(a) cpufuncs.cf_setup(a) 200 201 int set_cpufuncs (void); 202 int set_cpufuncs_id (u_int); 203 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 204 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 205 206 void cpufunc_nullop (void); 207 int cpufunc_null_fixup (void *); 208 int early_abort_fixup (void *); 209 int late_abort_fixup (void *); 210 u_int cpufunc_id (void); 211 u_int cpufunc_control (u_int, u_int); 212 void cpufunc_domains (u_int); 213 u_int cpufunc_faultstatus (void); 214 u_int cpufunc_faultaddress (void); 215 216 #ifdef CPU_ARM2 217 u_int arm2_id (void); 218 #endif /* CPU_ARM2 */ 219 220 #ifdef CPU_ARM250 221 u_int arm250_id (void); 222 #endif 223 224 #ifdef CPU_ARM3 225 u_int arm3_control (u_int, u_int); 226 void arm3_cache_flush (void); 227 #endif /* CPU_ARM3 */ 228 229 #if defined(CPU_ARM6) || defined(CPU_ARM7) 230 void arm67_setttb (u_int); 231 void arm67_tlb_flush (void); 232 void arm67_tlb_purge (u_int); 233 void arm67_cache_flush (void); 234 void arm67_context_switch (u_int); 235 #endif /* CPU_ARM6 || CPU_ARM7 */ 236 237 #ifdef CPU_ARM6 238 void arm6_setup (char *); 239 #endif /* CPU_ARM6 */ 240 241 #ifdef CPU_ARM7 242 void arm7_setup (char *); 243 #endif /* CPU_ARM7 */ 244 245 #ifdef CPU_ARM7TDMI 246 int arm7_dataabt_fixup (void *); 247 void arm7tdmi_setup (char *); 248 void arm7tdmi_setttb (u_int); 249 void arm7tdmi_tlb_flushID (void); 250 void arm7tdmi_tlb_flushID_SE (u_int); 251 void arm7tdmi_cache_flushID (void); 252 void arm7tdmi_context_switch (u_int); 253 #endif /* CPU_ARM7TDMI */ 254 255 #ifdef CPU_ARM8 256 void arm8_setttb (u_int); 257 void arm8_tlb_flushID (void); 258 void arm8_tlb_flushID_SE (u_int); 259 void arm8_cache_flushID (void); 260 void arm8_cache_flushID_E (u_int); 261 void arm8_cache_cleanID (void); 262 void arm8_cache_cleanID_E (u_int); 263 void arm8_cache_purgeID (void); 264 void arm8_cache_purgeID_E (u_int entry); 265 266 void arm8_cache_syncI (void); 267 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 268 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 269 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 270 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 271 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 272 273 void arm8_context_switch (u_int); 274 275 void arm8_setup (char *); 276 277 u_int arm8_clock_config (u_int, u_int); 278 #endif 279 280 #ifdef CPU_FA526 281 void fa526_setup (char *); 282 void fa526_setttb (u_int); 283 void fa526_context_switch (u_int); 284 void fa526_cpu_sleep (int); 285 void fa526_tlb_flushI_SE (u_int); 286 void fa526_tlb_flushID_SE (u_int); 287 void fa526_flush_prefetchbuf (void); 288 void fa526_flush_brnchtgt_E (u_int); 289 290 void fa526_icache_sync_all (void); 291 void fa526_icache_sync_range(vaddr_t, vsize_t); 292 void fa526_dcache_wbinv_all (void); 293 void fa526_dcache_wbinv_range(vaddr_t, vsize_t); 294 void fa526_dcache_inv_range (vaddr_t, vsize_t); 295 void fa526_dcache_wb_range (vaddr_t, vsize_t); 296 void fa526_idcache_wbinv_all(void); 297 void fa526_idcache_wbinv_range(vaddr_t, vsize_t); 298 #endif 299 300 #ifdef CPU_SA110 301 void sa110_setup (char *); 302 void sa110_context_switch (u_int); 303 #endif /* CPU_SA110 */ 304 305 #if defined(CPU_SA1100) || defined(CPU_SA1110) 306 void sa11x0_drain_readbuf (void); 307 308 void sa11x0_context_switch (u_int); 309 void sa11x0_cpu_sleep (int); 310 311 void sa11x0_setup (char *); 312 #endif 313 314 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 315 void sa1_setttb (u_int); 316 317 void sa1_tlb_flushID_SE (u_int); 318 319 void sa1_cache_flushID (void); 320 void sa1_cache_flushI (void); 321 void sa1_cache_flushD (void); 322 void sa1_cache_flushD_SE (u_int); 323 324 void sa1_cache_cleanID (void); 325 void sa1_cache_cleanD (void); 326 void sa1_cache_cleanD_E (u_int); 327 328 void sa1_cache_purgeID (void); 329 void sa1_cache_purgeID_E (u_int); 330 void sa1_cache_purgeD (void); 331 void sa1_cache_purgeD_E (u_int); 332 333 void sa1_cache_syncI (void); 334 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 335 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 336 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 337 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 338 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 339 340 #endif 341 342 #ifdef CPU_ARM9 343 void arm9_setttb (u_int); 344 345 void arm9_tlb_flushID_SE (u_int); 346 347 void arm9_icache_sync_all (void); 348 void arm9_icache_sync_range (vaddr_t, vsize_t); 349 350 void arm9_dcache_wbinv_all (void); 351 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 352 void arm9_dcache_inv_range (vaddr_t, vsize_t); 353 void arm9_dcache_wb_range (vaddr_t, vsize_t); 354 355 void arm9_idcache_wbinv_all (void); 356 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 357 358 void arm9_context_switch (u_int); 359 360 void arm9_setup (char *); 361 362 extern unsigned arm9_dcache_sets_max; 363 extern unsigned arm9_dcache_sets_inc; 364 extern unsigned arm9_dcache_index_max; 365 extern unsigned arm9_dcache_index_inc; 366 #endif 367 368 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 369 void arm10_tlb_flushID_SE (u_int); 370 void arm10_tlb_flushI_SE (u_int); 371 372 void arm10_context_switch (u_int); 373 374 void arm10_setup (char *); 375 #endif 376 377 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 378 void armv5_ec_setttb (u_int); 379 380 void armv5_ec_icache_sync_all (void); 381 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 382 383 void armv5_ec_dcache_wbinv_all (void); 384 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 385 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 386 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 387 388 void armv5_ec_idcache_wbinv_all (void); 389 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 390 #endif 391 392 #if defined (CPU_ARM10) 393 void armv5_setttb (u_int); 394 395 void armv5_icache_sync_all (void); 396 void armv5_icache_sync_range (vaddr_t, vsize_t); 397 398 void armv5_dcache_wbinv_all (void); 399 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 400 void armv5_dcache_inv_range (vaddr_t, vsize_t); 401 void armv5_dcache_wb_range (vaddr_t, vsize_t); 402 403 void armv5_idcache_wbinv_all (void); 404 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 405 406 extern unsigned armv5_dcache_sets_max; 407 extern unsigned armv5_dcache_sets_inc; 408 extern unsigned armv5_dcache_index_max; 409 extern unsigned armv5_dcache_index_inc; 410 #endif 411 412 #if defined(CPU_ARM11) || defined(CPU_CORTEXA8) 413 void arm11_setttb (u_int); 414 415 void arm11_tlb_flushID_SE (u_int); 416 void arm11_tlb_flushI_SE (u_int); 417 418 void arm11_context_switch (u_int); 419 420 void arm11_cpu_sleep (int); 421 void arm11_setup (char *string); 422 void arm11_tlb_flushID (void); 423 void arm11_tlb_flushI (void); 424 void arm11_tlb_flushD (void); 425 void arm11_tlb_flushD_SE (u_int va); 426 427 void armv11_dcache_wbinv_all (void); 428 void armv11_idcache_wbinv_all(void); 429 430 void arm11_drain_writebuf (void); 431 void arm11_sleep (int); 432 433 void armv6_setttb (u_int); 434 435 void armv6_icache_sync_all (void); 436 void armv6_icache_sync_range (vaddr_t, vsize_t); 437 438 void armv6_dcache_wbinv_all (void); 439 void armv6_dcache_wbinv_range (vaddr_t, vsize_t); 440 void armv6_dcache_inv_range (vaddr_t, vsize_t); 441 void armv6_dcache_wb_range (vaddr_t, vsize_t); 442 443 void armv6_idcache_wbinv_all (void); 444 void armv6_idcache_wbinv_range (vaddr_t, vsize_t); 445 #endif 446 447 #if defined(CPU_CORTEXA8) 448 void armv7_setttb(u_int); 449 450 void armv7_icache_sync_range(vaddr_t, vsize_t); 451 void armv7_dcache_wb_range(vaddr_t, vsize_t); 452 void armv7_dcache_wbinv_range(vaddr_t, vsize_t); 453 void armv7_dcache_inv_range(vaddr_t, vsize_t); 454 void armv7_idcache_wbinv_range(vaddr_t, vsize_t); 455 456 void armv7_dcache_wbinv_all (void); 457 void armv7_idcache_wbinv_all(void); 458 void armv7_icache_sync_all(void); 459 void armv7_cpu_sleep(int); 460 void armv7_context_switch(u_int); 461 void armv7_tlb_flushID_SE(u_int); 462 void armv7_setup (char *string); 463 #endif 464 465 466 #if defined(CPU_ARM1136) 467 void arm1136_setttb (u_int); 468 void arm1136_idcache_wbinv_all (void); 469 void arm1136_dcache_wbinv_all (void); 470 void arm1136_icache_sync_all (void); 471 void arm1136_flush_prefetchbuf (void); 472 void arm1136_icache_sync_range (vaddr_t, vsize_t); 473 void arm1136_idcache_wbinv_range (vaddr_t, vsize_t); 474 void arm1136_setup (char *string); 475 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 476 #endif 477 478 479 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 480 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 481 defined(CPU_FA526) || \ 482 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 483 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEXA8) 484 485 void armv4_tlb_flushID (void); 486 void armv4_tlb_flushI (void); 487 void armv4_tlb_flushD (void); 488 void armv4_tlb_flushD_SE (u_int); 489 490 void armv4_drain_writebuf (void); 491 #endif 492 493 #if defined(CPU_IXP12X0) 494 void ixp12x0_drain_readbuf (void); 495 void ixp12x0_context_switch (u_int); 496 void ixp12x0_setup (char *); 497 #endif 498 499 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 500 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \ 501 defined(CPU_CORTEXA8) 502 503 void xscale_cpwait (void); 504 #define cpu_cpwait() cpufuncs.cf_cpwait() 505 506 void xscale_cpu_sleep (int); 507 508 u_int xscale_control (u_int, u_int); 509 510 void xscale_setttb (u_int); 511 512 void xscale_tlb_flushID_SE (u_int); 513 514 void xscale_cache_flushID (void); 515 void xscale_cache_flushI (void); 516 void xscale_cache_flushD (void); 517 void xscale_cache_flushD_SE (u_int); 518 519 void xscale_cache_cleanID (void); 520 void xscale_cache_cleanD (void); 521 void xscale_cache_cleanD_E (u_int); 522 523 void xscale_cache_clean_minidata (void); 524 525 void xscale_cache_purgeID (void); 526 void xscale_cache_purgeID_E (u_int); 527 void xscale_cache_purgeD (void); 528 void xscale_cache_purgeD_E (u_int); 529 530 void xscale_cache_syncI (void); 531 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 532 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 533 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 534 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 535 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 536 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 537 538 void xscale_context_switch (u_int); 539 540 void xscale_setup (char *); 541 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEXA8 */ 542 543 #define tlb_flush cpu_tlb_flushID 544 #define setttb cpu_setttb 545 #define drain_writebuf cpu_drain_writebuf 546 547 #ifndef cpu_cpwait 548 #define cpu_cpwait() 549 #endif 550 551 /* 552 * Macros for manipulating CPU interrupts 553 */ 554 #ifdef __PROG32 555 static __inline u_int32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__)); 556 static __inline u_int32_t disable_interrupts(uint32_t mask) __attribute__((__unused__)); 557 static __inline u_int32_t enable_interrupts(uint32_t mask) __attribute__((__unused__)); 558 559 static __inline uint32_t 560 __set_cpsr_c(uint32_t bic, uint32_t eor) 561 { 562 uint32_t tmp, ret; 563 564 __asm volatile( 565 "mrs %0, cpsr\n" /* Get the CPSR */ 566 "bic %1, %0, %2\n" /* Clear bits */ 567 "eor %1, %1, %3\n" /* XOR bits */ 568 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 569 : "=&r" (ret), "=&r" (tmp) 570 : "r" (bic), "r" (eor) : "memory"); 571 572 return ret; 573 } 574 575 static __inline uint32_t 576 disable_interrupts(uint32_t mask) 577 { 578 uint32_t tmp, ret; 579 mask &= (I32_bit | F32_bit); 580 581 __asm volatile( 582 "mrs %0, cpsr\n" /* Get the CPSR */ 583 "orr %1, %0, %2\n" /* set bits */ 584 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 585 : "=&r" (ret), "=&r" (tmp) 586 : "r" (mask) 587 : "memory"); 588 589 return ret; 590 } 591 592 static __inline uint32_t 593 enable_interrupts(uint32_t mask) 594 { 595 uint32_t ret, tmp; 596 mask &= (I32_bit | F32_bit); 597 598 __asm volatile( 599 "mrs %0, cpsr\n" /* Get the CPSR */ 600 "bic %1, %0, %2\n" /* Clear bits */ 601 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 602 : "=&r" (ret), "=&r" (tmp) 603 : "r" (mask) 604 : "memory"); 605 606 return ret; 607 } 608 609 #define restore_interrupts(old_cpsr) \ 610 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 611 612 static inline void cpsie(register_t psw) __attribute__((__unused__)); 613 static inline register_t cpsid(register_t psw) __attribute__((__unused__)); 614 615 static inline void 616 cpsie(register_t psw) 617 { 618 #ifdef _ARM_ARCH_6 619 if (!__builtin_constant_p(psw)) { 620 enable_interrupts(psw); 621 return; 622 } 623 switch (psw & (I32_bit|F32_bit)) { 624 case I32_bit: __asm("cpsie\ti"); break; 625 case F32_bit: __asm("cpsie\tf"); break; 626 case I32_bit|F32_bit: __asm("cpsie\tif"); break; 627 } 628 #else 629 enable_interrupts(psw); 630 #endif 631 } 632 633 static inline register_t 634 cpsid(register_t psw) 635 { 636 #ifdef _ARM_ARCH_6 637 register_t oldpsw; 638 if (!__builtin_constant_p(psw)) 639 return disable_interrupts(psw); 640 641 __asm("mrs %0, cpsr" : "=r"(oldpsw)); 642 switch (psw & (I32_bit|F32_bit)) { 643 case I32_bit: __asm("cpsid\ti"); break; 644 case F32_bit: __asm("cpsid\tf"); break; 645 case I32_bit|F32_bit: __asm("cpsid\tif"); break; 646 } 647 return oldpsw; 648 #else 649 return disable_interrupts(psw); 650 #endif 651 } 652 653 #else /* ! __PROG32 */ 654 #define disable_interrupts(mask) \ 655 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 656 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 657 658 #define enable_interrupts(mask) \ 659 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 660 661 #define restore_interrupts(old_r15) \ 662 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 663 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 664 #endif /* __PROG32 */ 665 666 #ifdef __PROG32 667 /* Functions to manipulate the CPSR. */ 668 u_int SetCPSR(u_int, u_int); 669 u_int GetCPSR(void); 670 #else 671 /* Functions to manipulate the processor control bits in r15. */ 672 u_int set_r15(u_int, u_int); 673 u_int get_r15(void); 674 #endif /* __PROG32 */ 675 676 /* 677 * Functions to manipulate cpu r13 678 * (in arm/arm32/setstack.S) 679 */ 680 681 void set_stackptr (u_int, u_int); 682 u_int get_stackptr (u_int); 683 684 /* 685 * Miscellany 686 */ 687 688 int get_pc_str_offset (void); 689 690 /* 691 * CPU functions from locore.S 692 */ 693 694 void cpu_reset (void) __attribute__((__noreturn__)); 695 696 /* 697 * Cache info variables. 698 */ 699 700 /* PRIMARY CACHE VARIABLES */ 701 extern int arm_picache_size; 702 extern int arm_picache_line_size; 703 extern int arm_picache_ways; 704 705 extern int arm_pdcache_size; /* and unified */ 706 extern int arm_pdcache_line_size; 707 extern int arm_pdcache_ways; 708 extern int arm_cache_prefer_mask; 709 710 extern int arm_pcache_type; 711 extern int arm_pcache_unified; 712 713 extern int arm_dcache_align; 714 extern int arm_dcache_align_mask; 715 716 #endif /* _KERNEL */ 717 #endif /* _ARM32_CPUFUNC_H_ */ 718 719 /* End of cpufunc.h */ 720
Indexes created Mon Sep 29 18:09:42 GMT 2025