cpufunc.h revision 1.56
1 /* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM32_CPUFUNC_H_ 43 #define _ARM32_CPUFUNC_H_ 44 45 #ifdef _KERNEL 46 47 #include <sys/types.h> 48 #include <arm/armreg.h> 49 #include <arm/cpuconf.h> 50 #include <arm/armreg.h> 51 52 struct cpu_functions { 53 54 /* CPU functions */ 55 56 u_int (*cf_id) (void); 57 void (*cf_cpwait) (void); 58 59 /* MMU functions */ 60 61 u_int (*cf_control) (u_int, u_int); 62 void (*cf_domains) (u_int); 63 void (*cf_setttb) (u_int); 64 u_int (*cf_faultstatus) (void); 65 u_int (*cf_faultaddress) (void); 66 67 /* TLB functions */ 68 69 void (*cf_tlb_flushID) (void); 70 void (*cf_tlb_flushID_SE) (u_int); 71 void (*cf_tlb_flushI) (void); 72 void (*cf_tlb_flushI_SE) (u_int); 73 void (*cf_tlb_flushD) (void); 74 void (*cf_tlb_flushD_SE) (u_int); 75 76 /* 77 * Cache operations: 78 * 79 * We define the following primitives: 80 * 81 * icache_sync_all Synchronize I-cache 82 * icache_sync_range Synchronize I-cache range 83 * 84 * dcache_wbinv_all Write-back and Invalidate D-cache 85 * dcache_wbinv_range Write-back and Invalidate D-cache range 86 * dcache_inv_range Invalidate D-cache range 87 * dcache_wb_range Write-back D-cache range 88 * 89 * idcache_wbinv_all Write-back and Invalidate D-cache, 90 * Invalidate I-cache 91 * idcache_wbinv_range Write-back and Invalidate D-cache, 92 * Invalidate I-cache range 93 * 94 * Note that the ARM term for "write-back" is "clean". We use 95 * the term "write-back" since it's a more common way to describe 96 * the operation. 97 * 98 * There are some rules that must be followed: 99 * 100 * I-cache Synch (all or range): 101 * The goal is to synchronize the instruction stream, 102 * so you may beed to write-back dirty D-cache blocks 103 * first. If a range is requested, and you can't 104 * synchronize just a range, you have to hit the whole 105 * thing. 106 * 107 * D-cache Write-Back and Invalidate range: 108 * If you can't WB-Inv a range, you must WB-Inv the 109 * entire D-cache. 110 * 111 * D-cache Invalidate: 112 * If you can't Inv the D-cache, you must Write-Back 113 * and Invalidate. Code that uses this operation 114 * MUST NOT assume that the D-cache will not be written 115 * back to memory. 116 * 117 * D-cache Write-Back: 118 * If you can't Write-back without doing an Inv, 119 * that's fine. Then treat this as a WB-Inv. 120 * Skipping the invalidate is merely an optimization. 121 * 122 * All operations: 123 * Valid virtual addresses must be passed to each 124 * cache operation. 125 */ 126 void (*cf_icache_sync_all) (void); 127 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 128 129 void (*cf_dcache_wbinv_all) (void); 130 void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t); 131 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 132 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 133 134 void (*cf_idcache_wbinv_all) (void); 135 void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t); 136 137 /* Other functions */ 138 139 void (*cf_flush_prefetchbuf) (void); 140 void (*cf_drain_writebuf) (void); 141 void (*cf_flush_brnchtgt_C) (void); 142 void (*cf_flush_brnchtgt_E) (u_int); 143 144 void (*cf_sleep) (int mode); 145 146 /* Soft functions */ 147 148 int (*cf_dataabt_fixup) (void *); 149 int (*cf_prefetchabt_fixup) (void *); 150 151 void (*cf_context_switch) (u_int); 152 153 void (*cf_setup) (char *); 154 }; 155 156 extern struct cpu_functions cpufuncs; 157 extern u_int cputype; 158 159 #define cpu_id() cpufuncs.cf_id() 160 161 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 162 #define cpu_domains(d) cpufuncs.cf_domains(d) 163 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 164 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 165 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 166 167 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 168 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 169 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 170 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 171 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 172 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 173 174 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 175 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 176 177 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 178 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 179 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 180 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 181 182 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 183 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 184 185 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 186 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 187 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 188 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 189 190 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 191 192 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 193 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 194 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 195 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 196 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 197 198 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 199 #define cpu_setup(a) cpufuncs.cf_setup(a) 200 201 int set_cpufuncs (void); 202 int set_cpufuncs_id (u_int); 203 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 204 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 205 206 void cpufunc_nullop (void); 207 int cpufunc_null_fixup (void *); 208 int early_abort_fixup (void *); 209 int late_abort_fixup (void *); 210 u_int cpufunc_id (void); 211 u_int cpufunc_control (u_int, u_int); 212 void cpufunc_domains (u_int); 213 u_int cpufunc_faultstatus (void); 214 u_int cpufunc_faultaddress (void); 215 216 #if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) 217 void arm3_cache_flush (void); 218 #endif /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */ 219 220 #ifdef CPU_ARM2 221 u_int arm2_id (void); 222 #endif /* CPU_ARM2 */ 223 224 #ifdef CPU_ARM250 225 u_int arm250_id (void); 226 #endif 227 228 #ifdef CPU_ARM3 229 u_int arm3_control (u_int, u_int); 230 #endif /* CPU_ARM3 */ 231 232 #if defined(CPU_ARM6) || defined(CPU_ARM7) 233 void arm67_setttb (u_int); 234 void arm67_tlb_flush (void); 235 void arm67_tlb_purge (u_int); 236 void arm67_cache_flush (void); 237 void arm67_context_switch (u_int); 238 #endif /* CPU_ARM6 || CPU_ARM7 */ 239 240 #ifdef CPU_ARM6 241 void arm6_setup (char *); 242 #endif /* CPU_ARM6 */ 243 244 #ifdef CPU_ARM7 245 void arm7_setup (char *); 246 #endif /* CPU_ARM7 */ 247 248 #ifdef CPU_ARM7TDMI 249 int arm7_dataabt_fixup (void *); 250 void arm7tdmi_setup (char *); 251 void arm7tdmi_setttb (u_int); 252 void arm7tdmi_tlb_flushID (void); 253 void arm7tdmi_tlb_flushID_SE (u_int); 254 void arm7tdmi_cache_flushID (void); 255 void arm7tdmi_context_switch (u_int); 256 #endif /* CPU_ARM7TDMI */ 257 258 #ifdef CPU_ARM8 259 void arm8_setttb (u_int); 260 void arm8_tlb_flushID (void); 261 void arm8_tlb_flushID_SE (u_int); 262 void arm8_cache_flushID (void); 263 void arm8_cache_flushID_E (u_int); 264 void arm8_cache_cleanID (void); 265 void arm8_cache_cleanID_E (u_int); 266 void arm8_cache_purgeID (void); 267 void arm8_cache_purgeID_E (u_int entry); 268 269 void arm8_cache_syncI (void); 270 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 271 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 272 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 273 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 274 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 275 276 void arm8_context_switch (u_int); 277 278 void arm8_setup (char *); 279 280 u_int arm8_clock_config (u_int, u_int); 281 #endif 282 283 #ifdef CPU_FA526 284 void fa526_setup (char *); 285 void fa526_setttb (u_int); 286 void fa526_context_switch (u_int); 287 void fa526_cpu_sleep (int); 288 void fa526_tlb_flushI_SE (u_int); 289 void fa526_tlb_flushID_SE (u_int); 290 void fa526_flush_prefetchbuf (void); 291 void fa526_flush_brnchtgt_E (u_int); 292 293 void fa526_icache_sync_all (void); 294 void fa526_icache_sync_range(vaddr_t, vsize_t); 295 void fa526_dcache_wbinv_all (void); 296 void fa526_dcache_wbinv_range(vaddr_t, vsize_t); 297 void fa526_dcache_inv_range (vaddr_t, vsize_t); 298 void fa526_dcache_wb_range (vaddr_t, vsize_t); 299 void fa526_idcache_wbinv_all(void); 300 void fa526_idcache_wbinv_range(vaddr_t, vsize_t); 301 #endif 302 303 #ifdef CPU_SA110 304 void sa110_setup (char *); 305 void sa110_context_switch (u_int); 306 #endif /* CPU_SA110 */ 307 308 #if defined(CPU_SA1100) || defined(CPU_SA1110) 309 void sa11x0_drain_readbuf (void); 310 311 void sa11x0_context_switch (u_int); 312 void sa11x0_cpu_sleep (int); 313 314 void sa11x0_setup (char *); 315 #endif 316 317 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 318 void sa1_setttb (u_int); 319 320 void sa1_tlb_flushID_SE (u_int); 321 322 void sa1_cache_flushID (void); 323 void sa1_cache_flushI (void); 324 void sa1_cache_flushD (void); 325 void sa1_cache_flushD_SE (u_int); 326 327 void sa1_cache_cleanID (void); 328 void sa1_cache_cleanD (void); 329 void sa1_cache_cleanD_E (u_int); 330 331 void sa1_cache_purgeID (void); 332 void sa1_cache_purgeID_E (u_int); 333 void sa1_cache_purgeD (void); 334 void sa1_cache_purgeD_E (u_int); 335 336 void sa1_cache_syncI (void); 337 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 338 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 339 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 340 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 341 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 342 343 #endif 344 345 #ifdef CPU_ARM9 346 void arm9_setttb (u_int); 347 348 void arm9_tlb_flushID_SE (u_int); 349 350 void arm9_icache_sync_all (void); 351 void arm9_icache_sync_range (vaddr_t, vsize_t); 352 353 void arm9_dcache_wbinv_all (void); 354 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 355 void arm9_dcache_inv_range (vaddr_t, vsize_t); 356 void arm9_dcache_wb_range (vaddr_t, vsize_t); 357 358 void arm9_idcache_wbinv_all (void); 359 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 360 361 void arm9_context_switch (u_int); 362 363 void arm9_setup (char *); 364 365 extern unsigned arm9_dcache_sets_max; 366 extern unsigned arm9_dcache_sets_inc; 367 extern unsigned arm9_dcache_index_max; 368 extern unsigned arm9_dcache_index_inc; 369 #endif 370 371 #if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA) 372 void arm10_tlb_flushID_SE (u_int); 373 void arm10_tlb_flushI_SE (u_int); 374 375 void arm10_context_switch (u_int); 376 377 void arm10_setup (char *); 378 #endif 379 380 #if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA) 381 void armv5_ec_setttb (u_int); 382 383 void armv5_ec_icache_sync_all (void); 384 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 385 386 void armv5_ec_dcache_wbinv_all (void); 387 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 388 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 389 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 390 391 void armv5_ec_idcache_wbinv_all (void); 392 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 393 #endif 394 395 #if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE) 396 void armv5_setttb (u_int); 397 398 void armv5_icache_sync_all (void); 399 void armv5_icache_sync_range (vaddr_t, vsize_t); 400 401 void armv5_dcache_wbinv_all (void); 402 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 403 void armv5_dcache_inv_range (vaddr_t, vsize_t); 404 void armv5_dcache_wb_range (vaddr_t, vsize_t); 405 406 void armv5_idcache_wbinv_all (void); 407 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 408 409 extern unsigned armv5_dcache_sets_max; 410 extern unsigned armv5_dcache_sets_inc; 411 extern unsigned armv5_dcache_index_max; 412 extern unsigned armv5_dcache_index_inc; 413 #endif 414 415 #if defined(CPU_ARM11MPCORE) 416 void arm11mpcore_setup (char *); 417 #endif 418 419 #if defined(CPU_ARM11) || defined(CPU_CORTEX) 420 void arm11_setttb (u_int); 421 422 void arm11_tlb_flushID_SE (u_int); 423 void arm11_tlb_flushI_SE (u_int); 424 425 void arm11_context_switch (u_int); 426 427 void arm11_cpu_sleep (int); 428 void arm11_setup (char *string); 429 void arm11_tlb_flushID (void); 430 void arm11_tlb_flushI (void); 431 void arm11_tlb_flushD (void); 432 void arm11_tlb_flushD_SE (u_int va); 433 434 void armv11_dcache_wbinv_all (void); 435 void armv11_idcache_wbinv_all(void); 436 437 void arm11_drain_writebuf (void); 438 void arm11_sleep (int); 439 440 void armv6_setttb (u_int); 441 442 void armv6_icache_sync_all (void); 443 void armv6_icache_sync_range (vaddr_t, vsize_t); 444 445 void armv6_dcache_wbinv_all (void); 446 void armv6_dcache_wbinv_range (vaddr_t, vsize_t); 447 void armv6_dcache_inv_range (vaddr_t, vsize_t); 448 void armv6_dcache_wb_range (vaddr_t, vsize_t); 449 450 void armv6_idcache_wbinv_all (void); 451 void armv6_idcache_wbinv_range (vaddr_t, vsize_t); 452 #endif 453 454 #if defined(CPU_CORTEX) 455 void armv7_setttb(u_int); 456 457 void armv7_icache_sync_range(vaddr_t, vsize_t); 458 void armv7_dcache_wb_range(vaddr_t, vsize_t); 459 void armv7_dcache_wbinv_range(vaddr_t, vsize_t); 460 void armv7_dcache_inv_range(vaddr_t, vsize_t); 461 void armv7_idcache_wbinv_range(vaddr_t, vsize_t); 462 463 void armv7_dcache_wbinv_all (void); 464 void armv7_idcache_wbinv_all(void); 465 void armv7_icache_sync_all(void); 466 void armv7_cpu_sleep(int); 467 void armv7_context_switch(u_int); 468 void armv7_tlb_flushID_SE(u_int); 469 void armv7_setup (char *string); 470 #endif 471 472 473 #if defined(CPU_ARM1136) 474 void arm1136_setttb (u_int); 475 void arm1136_idcache_wbinv_all (void); 476 void arm1136_dcache_wbinv_all (void); 477 void arm1136_icache_sync_all (void); 478 void arm1136_flush_prefetchbuf (void); 479 void arm1136_icache_sync_range (vaddr_t, vsize_t); 480 void arm1136_idcache_wbinv_range (vaddr_t, vsize_t); 481 void arm1136_setup (char *string); 482 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 483 #endif 484 485 486 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 487 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 488 defined(CPU_FA526) || \ 489 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 490 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \ 491 defined(CPU_CORTEX) || defined(CPU_SHEEVA) 492 493 void armv4_tlb_flushID (void); 494 void armv4_tlb_flushI (void); 495 void armv4_tlb_flushD (void); 496 void armv4_tlb_flushD_SE (u_int); 497 498 void armv4_drain_writebuf (void); 499 #endif 500 501 #if defined(CPU_IXP12X0) 502 void ixp12x0_drain_readbuf (void); 503 void ixp12x0_context_switch (u_int); 504 void ixp12x0_setup (char *); 505 #endif 506 507 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 508 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \ 509 defined(CPU_CORTEX) 510 511 void xscale_cpwait (void); 512 #define cpu_cpwait() cpufuncs.cf_cpwait() 513 514 void xscale_cpu_sleep (int); 515 516 u_int xscale_control (u_int, u_int); 517 518 void xscale_setttb (u_int); 519 520 void xscale_tlb_flushID_SE (u_int); 521 522 void xscale_cache_flushID (void); 523 void xscale_cache_flushI (void); 524 void xscale_cache_flushD (void); 525 void xscale_cache_flushD_SE (u_int); 526 527 void xscale_cache_cleanID (void); 528 void xscale_cache_cleanD (void); 529 void xscale_cache_cleanD_E (u_int); 530 531 void xscale_cache_clean_minidata (void); 532 533 void xscale_cache_purgeID (void); 534 void xscale_cache_purgeID_E (u_int); 535 void xscale_cache_purgeD (void); 536 void xscale_cache_purgeD_E (u_int); 537 538 void xscale_cache_syncI (void); 539 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 540 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 541 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 542 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 543 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 544 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 545 546 void xscale_context_switch (u_int); 547 548 void xscale_setup (char *); 549 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEX */ 550 551 #if defined(CPU_SHEEVA) 552 void sheeva_dcache_wbinv_range (vaddr_t, vsize_t); 553 void sheeva_dcache_inv_range (vaddr_t, vsize_t); 554 void sheeva_dcache_wb_range (vaddr_t, vsize_t); 555 void sheeva_idcache_wbinv_range (vaddr_t, vsize_t); 556 void sheeva_setup(char *); 557 void sheeva_cpu_sleep(int); 558 #endif 559 560 #define tlb_flush cpu_tlb_flushID 561 #define setttb cpu_setttb 562 #define drain_writebuf cpu_drain_writebuf 563 564 #ifndef cpu_cpwait 565 #define cpu_cpwait() 566 #endif 567 568 /* 569 * Macros for manipulating CPU interrupts 570 */ 571 #ifdef __PROG32 572 static __inline u_int32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__)); 573 static __inline u_int32_t disable_interrupts(uint32_t mask) __attribute__((__unused__)); 574 static __inline u_int32_t enable_interrupts(uint32_t mask) __attribute__((__unused__)); 575 576 static __inline uint32_t 577 __set_cpsr_c(uint32_t bic, uint32_t eor) 578 { 579 uint32_t tmp, ret; 580 581 __asm volatile( 582 "mrs %0, cpsr\n" /* Get the CPSR */ 583 "bic %1, %0, %2\n" /* Clear bits */ 584 "eor %1, %1, %3\n" /* XOR bits */ 585 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 586 : "=&r" (ret), "=&r" (tmp) 587 : "r" (bic), "r" (eor) : "memory"); 588 589 return ret; 590 } 591 592 static __inline uint32_t 593 disable_interrupts(uint32_t mask) 594 { 595 uint32_t tmp, ret; 596 mask &= (I32_bit | F32_bit); 597 598 __asm volatile( 599 "mrs %0, cpsr\n" /* Get the CPSR */ 600 "orr %1, %0, %2\n" /* set bits */ 601 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 602 : "=&r" (ret), "=&r" (tmp) 603 : "r" (mask) 604 : "memory"); 605 606 return ret; 607 } 608 609 static __inline uint32_t 610 enable_interrupts(uint32_t mask) 611 { 612 uint32_t ret, tmp; 613 mask &= (I32_bit | F32_bit); 614 615 __asm volatile( 616 "mrs %0, cpsr\n" /* Get the CPSR */ 617 "bic %1, %0, %2\n" /* Clear bits */ 618 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 619 : "=&r" (ret), "=&r" (tmp) 620 : "r" (mask) 621 : "memory"); 622 623 return ret; 624 } 625 626 #define restore_interrupts(old_cpsr) \ 627 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 628 629 static inline void cpsie(register_t psw) __attribute__((__unused__)); 630 static inline register_t cpsid(register_t psw) __attribute__((__unused__)); 631 632 static inline void 633 cpsie(register_t psw) 634 { 635 #ifdef _ARM_ARCH_6 636 if (!__builtin_constant_p(psw)) { 637 enable_interrupts(psw); 638 return; 639 } 640 switch (psw & (I32_bit|F32_bit)) { 641 case I32_bit: __asm("cpsie\ti"); break; 642 case F32_bit: __asm("cpsie\tf"); break; 643 case I32_bit|F32_bit: __asm("cpsie\tif"); break; 644 } 645 #else 646 enable_interrupts(psw); 647 #endif 648 } 649 650 static inline register_t 651 cpsid(register_t psw) 652 { 653 #ifdef _ARM_ARCH_6 654 register_t oldpsw; 655 if (!__builtin_constant_p(psw)) 656 return disable_interrupts(psw); 657 658 __asm("mrs %0, cpsr" : "=r"(oldpsw)); 659 switch (psw & (I32_bit|F32_bit)) { 660 case I32_bit: __asm("cpsid\ti"); break; 661 case F32_bit: __asm("cpsid\tf"); break; 662 case I32_bit|F32_bit: __asm("cpsid\tif"); break; 663 } 664 return oldpsw; 665 #else 666 return disable_interrupts(psw); 667 #endif 668 } 669 670 #else /* ! __PROG32 */ 671 #define disable_interrupts(mask) \ 672 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 673 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 674 675 #define enable_interrupts(mask) \ 676 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 677 678 #define restore_interrupts(old_r15) \ 679 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 680 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 681 #endif /* __PROG32 */ 682 683 #ifdef __PROG32 684 /* Functions to manipulate the CPSR. */ 685 u_int SetCPSR(u_int, u_int); 686 u_int GetCPSR(void); 687 #else 688 /* Functions to manipulate the processor control bits in r15. */ 689 u_int set_r15(u_int, u_int); 690 u_int get_r15(void); 691 #endif /* __PROG32 */ 692 693 694 /* 695 * CPU functions from locore.S 696 */ 697 698 void cpu_reset (void) __attribute__((__noreturn__)); 699 700 /* 701 * Cache info variables. 702 */ 703 704 /* PRIMARY CACHE VARIABLES */ 705 extern int arm_picache_size; 706 extern int arm_picache_line_size; 707 extern int arm_picache_ways; 708 709 extern int arm_pdcache_size; /* and unified */ 710 extern int arm_pdcache_line_size; 711 extern int arm_pdcache_ways; 712 extern int arm_cache_prefer_mask; 713 714 extern int arm_pcache_type; 715 extern int arm_pcache_unified; 716 717 extern int arm_dcache_align; 718 extern int arm_dcache_align_mask; 719 720 #endif /* _KERNEL */ 721 722 #if defined(_KERNEL) || defined(_KMEMUSER) 723 /* 724 * Miscellany 725 */ 726 727 int get_pc_str_offset (void); 728 729 /* 730 * Functions to manipulate cpu r13 731 * (in arm/arm32/setstack.S) 732 */ 733 734 void set_stackptr (u_int, u_int); 735 u_int get_stackptr (u_int); 736 737 #endif /* _KERNEL || _KMEMUSER */ 738 739 #endif /* _ARM32_CPUFUNC_H_ */ 740 741 /* End of cpufunc.h */ 742
Indexes created Sat Sep 27 14:09:57 GMT 2025