locore.h revision 1.14
1 /* $NetBSD: locore.h,v 1.14 2014/03/03 08:15:36 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef _KERNEL_OPT 52 #include "opt_cpuoptions.h" 53 #include "opt_cputypes.h" 54 #endif 55 56 #include <arm/cpuconf.h> 57 #include <arm/armreg.h> 58 59 #include <machine/frame.h> 60 61 #ifdef _LOCORE 62 63 #if defined(_ARM_ARCH_6) 64 #define IRQdisable cpsid i 65 #define IRQenable cpsie i 66 #elif defined(__PROG32) 67 #define IRQdisable \ 68 stmfd sp!, {r0} ; \ 69 mrs r0, cpsr ; \ 70 orr r0, r0, #(I32_bit) ; \ 71 msr cpsr_c, r0 ; \ 72 ldmfd sp!, {r0} 73 74 #define IRQenable \ 75 stmfd sp!, {r0} ; \ 76 mrs r0, cpsr ; \ 77 bic r0, r0, #(I32_bit) ; \ 78 msr cpsr_c, r0 ; \ 79 ldmfd sp!, {r0} 80 #else 81 /* Not yet used in 26-bit code */ 82 #endif 83 84 #if defined (TPIDRPRW_IS_CURCPU) 85 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 86 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 87 #elif defined (TPIDRPRW_IS_CURLWP) 88 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 89 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 90 #elif !defined(MULTIPROCESSOR) 91 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 92 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 93 #endif 94 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 95 96 #else /* !_LOCORE */ 97 98 #include <arm/cpufunc.h> 99 100 #ifdef __PROG32 101 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 102 #define IRQenable __set_cpsr_c(I32_bit, 0); 103 #else 104 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE); 105 #define IRQenable set_r15(R15_IRQ_DISABLE, 0); 106 #endif 107 108 /* 109 * Validate a PC or PSR for a user process. Used by various system calls 110 * that take a context passed by the user and restore it. 111 */ 112 113 #ifdef __PROG32 114 #define VALID_R15_PSR(r15,psr) \ 115 (((psr) & PSR_MODE) == PSR_USR32_MODE && \ 116 ((psr) & (I32_bit | F32_bit)) == 0) 117 #else 118 #define VALID_R15_PSR(r15,psr) \ 119 (((r15) & R15_MODE) == R15_MODE_USR && \ 120 ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0) 121 #endif 122 123 124 125 /* The address of the vector page. */ 126 extern vaddr_t vector_page; 127 #ifdef __PROG32 128 void arm32_vector_init(vaddr_t, int); 129 130 #define ARM_VEC_RESET (1 << 0) 131 #define ARM_VEC_UNDEFINED (1 << 1) 132 #define ARM_VEC_SWI (1 << 2) 133 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 134 #define ARM_VEC_DATA_ABORT (1 << 4) 135 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 136 #define ARM_VEC_IRQ (1 << 6) 137 #define ARM_VEC_FIQ (1 << 7) 138 139 #define ARM_NVEC 8 140 #define ARM_VEC_ALL 0xffffffff 141 #endif /* __PROG32 */ 142 143 #ifndef acorn26 144 /* 145 * cpu device glue (belongs in cpuvar.h) 146 */ 147 void cpu_attach(device_t, cpuid_t); 148 #endif 149 150 /* 1 == use cpu_sleep(), 0 == don't */ 151 extern int cpu_do_powersave; 152 extern int cpu_printfataltraps; 153 extern int cpu_fpu_present; 154 extern int cpu_hwdiv_present; 155 extern int cpu_neon_present; 156 extern int cpu_simd_present; 157 extern int cpu_simdex_present; 158 extern int cpu_umull_present; 159 extern int cpu_synchprim_present; 160 161 extern int cpu_instruction_set_attributes[6]; 162 extern int cpu_memory_model_features[4]; 163 extern int cpu_processor_features[2]; 164 extern int cpu_media_and_vfp_features[2]; 165 166 extern u_int arm_cpu_max; 167 168 #if !defined(CPU_ARMV7) 169 #define CPU_IS_ARMV7_P() false 170 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 171 extern bool cpu_armv7_p; 172 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 173 #else 174 #define CPU_IS_ARMV7_P() true 175 #endif 176 #if !defined(CPU_ARMV6) 177 #define CPU_IS_ARMV6_P() false 178 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 179 extern bool cpu_armv6_p; 180 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 181 #else 182 #define CPU_IS_ARMV6_P() true 183 #endif 184 185 /* 186 * Used by the fault code to read the current instruction. 187 */ 188 static inline uint32_t 189 read_insn(vaddr_t va, bool user_p) 190 { 191 uint32_t insn; 192 if (user_p) { 193 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 194 } else { 195 insn = *(const uint32_t *)va; 196 } 197 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 198 insn = bswap32(insn); 199 #endif 200 return insn; 201 } 202 203 /* 204 * Used by the fault code to read the current thumb instruction. 205 */ 206 static inline uint32_t 207 read_thumb_insn(vaddr_t va, bool user_p) 208 { 209 va &= ~1; 210 uint32_t insn; 211 if (user_p) { 212 #ifdef _ARM_ARCH_T2 213 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 214 #else 215 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 216 #ifdef __ARMEB__ 217 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 218 #else 219 insn = (uint16_t) (insn >> ((va & 2) << 3)); 220 #endif 221 #endif 222 } else { 223 insn = *(const uint16_t *)va; 224 } 225 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 226 insn = bswap16(insn); 227 #endif 228 return insn; 229 } 230 231 /* 232 * Random cruft 233 */ 234 235 struct lwp; 236 237 /* locore.S */ 238 void atomic_set_bit(u_int *, u_int); 239 void atomic_clear_bit(u_int *, u_int); 240 241 /* cpuswitch.S */ 242 struct pcb; 243 void savectx(struct pcb *); 244 245 /* ast.c */ 246 void userret(struct lwp *); 247 248 /* *_machdep.c */ 249 void bootsync(void); 250 251 /* fault.c */ 252 int badaddr_read(void *, size_t, void *); 253 254 /* syscall.c */ 255 void swi_handler(trapframe_t *); 256 257 /* arm_machdep.c */ 258 void ucas_ras_check(trapframe_t *); 259 260 /* vfp_init.c */ 261 void vfp_attach(void); 262 void vfp_discardcontext(bool); 263 void vfp_savecontext(void); 264 void vfp_kernel_acquire(void); 265 void vfp_kernel_release(void); 266 bool vfp_used_p(void); 267 extern const pcu_ops_t arm_vfp_ops; 268 269 #endif /* !_LOCORE */ 270 271 #endif /* !_ARM_LOCORE_H_ */ 272
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