locore.h revision 1.15
1 /* $NetBSD: locore.h,v 1.15 2014/03/18 07:05:46 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef _KERNEL_OPT 52 #include "opt_cpuoptions.h" 53 #include "opt_cputypes.h" 54 #include "opt_arm_debug.h" 55 #endif 56 57 #include <arm/cpuconf.h> 58 #include <arm/armreg.h> 59 60 #include <machine/frame.h> 61 62 #ifdef _LOCORE 63 64 #if defined(_ARM_ARCH_6) 65 #define IRQdisable cpsid i 66 #define IRQenable cpsie i 67 #elif defined(__PROG32) 68 #define IRQdisable \ 69 stmfd sp!, {r0} ; \ 70 mrs r0, cpsr ; \ 71 orr r0, r0, #(I32_bit) ; \ 72 msr cpsr_c, r0 ; \ 73 ldmfd sp!, {r0} 74 75 #define IRQenable \ 76 stmfd sp!, {r0} ; \ 77 mrs r0, cpsr ; \ 78 bic r0, r0, #(I32_bit) ; \ 79 msr cpsr_c, r0 ; \ 80 ldmfd sp!, {r0} 81 #else 82 /* Not yet used in 26-bit code */ 83 #endif 84 85 #if defined (TPIDRPRW_IS_CURCPU) 86 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 87 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 88 #elif defined (TPIDRPRW_IS_CURLWP) 89 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 90 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 91 #elif !defined(MULTIPROCESSOR) 92 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 93 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 94 #endif 95 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 96 97 #else /* !_LOCORE */ 98 99 #include <arm/cpufunc.h> 100 101 #ifdef __PROG32 102 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 103 #define IRQenable __set_cpsr_c(I32_bit, 0); 104 #else 105 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE); 106 #define IRQenable set_r15(R15_IRQ_DISABLE, 0); 107 #endif 108 109 /* 110 * Validate a PC or PSR for a user process. Used by various system calls 111 * that take a context passed by the user and restore it. 112 */ 113 114 #ifdef __PROG32 115 #define VALID_R15_PSR(r15,psr) \ 116 (((psr) & PSR_MODE) == PSR_USR32_MODE && \ 117 ((psr) & (I32_bit | F32_bit)) == 0) 118 #else 119 #define VALID_R15_PSR(r15,psr) \ 120 (((r15) & R15_MODE) == R15_MODE_USR && \ 121 ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0) 122 #endif 123 124 125 126 /* The address of the vector page. */ 127 extern vaddr_t vector_page; 128 #ifdef __PROG32 129 void arm32_vector_init(vaddr_t, int); 130 131 #define ARM_VEC_RESET (1 << 0) 132 #define ARM_VEC_UNDEFINED (1 << 1) 133 #define ARM_VEC_SWI (1 << 2) 134 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 135 #define ARM_VEC_DATA_ABORT (1 << 4) 136 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 137 #define ARM_VEC_IRQ (1 << 6) 138 #define ARM_VEC_FIQ (1 << 7) 139 140 #define ARM_NVEC 8 141 #define ARM_VEC_ALL 0xffffffff 142 #endif /* __PROG32 */ 143 144 #ifndef acorn26 145 /* 146 * cpu device glue (belongs in cpuvar.h) 147 */ 148 void cpu_attach(device_t, cpuid_t); 149 #endif 150 151 /* 1 == use cpu_sleep(), 0 == don't */ 152 extern int cpu_do_powersave; 153 extern int cpu_printfataltraps; 154 extern int cpu_fpu_present; 155 extern int cpu_hwdiv_present; 156 extern int cpu_neon_present; 157 extern int cpu_simd_present; 158 extern int cpu_simdex_present; 159 extern int cpu_umull_present; 160 extern int cpu_synchprim_present; 161 162 extern int cpu_instruction_set_attributes[6]; 163 extern int cpu_memory_model_features[4]; 164 extern int cpu_processor_features[2]; 165 extern int cpu_media_and_vfp_features[2]; 166 167 extern u_int arm_cpu_max; 168 169 #if !defined(CPU_ARMV7) 170 #define CPU_IS_ARMV7_P() false 171 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 172 extern bool cpu_armv7_p; 173 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 174 #else 175 #define CPU_IS_ARMV7_P() true 176 #endif 177 #if !defined(CPU_ARMV6) 178 #define CPU_IS_ARMV6_P() false 179 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 180 extern bool cpu_armv6_p; 181 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 182 #else 183 #define CPU_IS_ARMV6_P() true 184 #endif 185 186 /* 187 * Used by the fault code to read the current instruction. 188 */ 189 static inline uint32_t 190 read_insn(vaddr_t va, bool user_p) 191 { 192 uint32_t insn; 193 if (user_p) { 194 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 195 } else { 196 insn = *(const uint32_t *)va; 197 } 198 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 199 insn = bswap32(insn); 200 #endif 201 return insn; 202 } 203 204 /* 205 * Used by the fault code to read the current thumb instruction. 206 */ 207 static inline uint32_t 208 read_thumb_insn(vaddr_t va, bool user_p) 209 { 210 va &= ~1; 211 uint32_t insn; 212 if (user_p) { 213 #ifdef _ARM_ARCH_T2 214 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 215 #else 216 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 217 #ifdef __ARMEB__ 218 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 219 #else 220 insn = (uint16_t) (insn >> ((va & 2) << 3)); 221 #endif 222 #endif 223 } else { 224 insn = *(const uint16_t *)va; 225 } 226 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 227 insn = bswap16(insn); 228 #endif 229 return insn; 230 } 231 232 /* 233 * Random cruft 234 */ 235 236 struct lwp; 237 238 /* locore.S */ 239 void atomic_set_bit(u_int *, u_int); 240 void atomic_clear_bit(u_int *, u_int); 241 242 /* cpuswitch.S */ 243 struct pcb; 244 void savectx(struct pcb *); 245 246 /* ast.c */ 247 void userret(struct lwp *); 248 249 /* *_machdep.c */ 250 void bootsync(void); 251 252 /* fault.c */ 253 int badaddr_read(void *, size_t, void *); 254 255 /* syscall.c */ 256 void swi_handler(trapframe_t *); 257 258 /* arm_machdep.c */ 259 void ucas_ras_check(trapframe_t *); 260 261 /* vfp_init.c */ 262 void vfp_attach(void); 263 void vfp_discardcontext(bool); 264 void vfp_savecontext(void); 265 void vfp_kernel_acquire(void); 266 void vfp_kernel_release(void); 267 bool vfp_used_p(void); 268 extern const pcu_ops_t arm_vfp_ops; 269 270 #endif /* !_LOCORE */ 271 272 #endif /* !_ARM_LOCORE_H_ */ 273
Indexes created Tue Sep 30 11:09:46 GMT 2025