locore.h revision 1.18
1 /* $NetBSD: locore.h,v 1.18 2014/11/07 20:48:41 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef _KERNEL_OPT 52 #include "opt_cpuoptions.h" 53 #include "opt_cputypes.h" 54 #include "opt_arm_debug.h" 55 #endif 56 57 #include <arm/cpuconf.h> 58 #include <arm/armreg.h> 59 60 #include <machine/frame.h> 61 62 #ifdef _LOCORE 63 64 #if defined(_ARM_ARCH_6) 65 #define IRQdisable cpsid i 66 #define IRQenable cpsie i 67 #elif defined(__PROG32) 68 #define IRQdisable \ 69 stmfd sp!, {r0} ; \ 70 mrs r0, cpsr ; \ 71 orr r0, r0, #(I32_bit) ; \ 72 msr cpsr_c, r0 ; \ 73 ldmfd sp!, {r0} 74 75 #define IRQenable \ 76 stmfd sp!, {r0} ; \ 77 mrs r0, cpsr ; \ 78 bic r0, r0, #(I32_bit) ; \ 79 msr cpsr_c, r0 ; \ 80 ldmfd sp!, {r0} 81 #else 82 /* Not yet used in 26-bit code */ 83 #endif 84 85 #if defined (TPIDRPRW_IS_CURCPU) 86 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 87 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 88 #elif defined (TPIDRPRW_IS_CURLWP) 89 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 90 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 91 #elif !defined(MULTIPROCESSOR) 92 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 93 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 94 #endif 95 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 96 97 #else /* !_LOCORE */ 98 99 #include <arm/cpufunc.h> 100 101 #ifdef __PROG32 102 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 103 #define IRQenable __set_cpsr_c(I32_bit, 0); 104 #else 105 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE); 106 #define IRQenable set_r15(R15_IRQ_DISABLE, 0); 107 #endif 108 109 /* 110 * Validate a PC or PSR for a user process. Used by various system calls 111 * that take a context passed by the user and restore it. 112 */ 113 114 #ifdef __PROG32 115 #ifdef __NO_FIQ 116 #define VALID_R15_PSR(r15,psr) \ 117 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0) 118 #else 119 #define VALID_R15_PSR(r15,psr) \ 120 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0) 121 #endif 122 #else 123 #define VALID_R15_PSR(r15,psr) \ 124 (((r15) & R15_MODE) == R15_MODE_USR && \ 125 ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0) 126 #endif 127 128 129 130 /* The address of the vector page. */ 131 extern vaddr_t vector_page; 132 #ifdef __PROG32 133 void arm32_vector_init(vaddr_t, int); 134 135 #define ARM_VEC_RESET (1 << 0) 136 #define ARM_VEC_UNDEFINED (1 << 1) 137 #define ARM_VEC_SWI (1 << 2) 138 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 139 #define ARM_VEC_DATA_ABORT (1 << 4) 140 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 141 #define ARM_VEC_IRQ (1 << 6) 142 #define ARM_VEC_FIQ (1 << 7) 143 144 #define ARM_NVEC 8 145 #define ARM_VEC_ALL 0xffffffff 146 #endif /* __PROG32 */ 147 148 #ifndef acorn26 149 /* 150 * cpu device glue (belongs in cpuvar.h) 151 */ 152 void cpu_attach(device_t, cpuid_t); 153 #endif 154 155 /* 1 == use cpu_sleep(), 0 == don't */ 156 extern int cpu_do_powersave; 157 extern int cpu_printfataltraps; 158 extern int cpu_fpu_present; 159 extern int cpu_hwdiv_present; 160 extern int cpu_neon_present; 161 extern int cpu_simd_present; 162 extern int cpu_simdex_present; 163 extern int cpu_umull_present; 164 extern int cpu_synchprim_present; 165 166 extern int cpu_instruction_set_attributes[6]; 167 extern int cpu_memory_model_features[4]; 168 extern int cpu_processor_features[2]; 169 extern int cpu_media_and_vfp_features[2]; 170 171 extern bool arm_has_tlbiasid_p; 172 #ifdef MULTIPROCESSOR 173 extern u_int arm_cpu_max; 174 extern volatile u_int arm_cpu_hatched; 175 #endif 176 177 #if !defined(CPU_ARMV7) 178 #define CPU_IS_ARMV7_P() false 179 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 180 extern bool cpu_armv7_p; 181 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 182 #else 183 #define CPU_IS_ARMV7_P() true 184 #endif 185 #if !defined(CPU_ARMV6) 186 #define CPU_IS_ARMV6_P() false 187 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 188 extern bool cpu_armv6_p; 189 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 190 #else 191 #define CPU_IS_ARMV6_P() true 192 #endif 193 194 /* 195 * Used by the fault code to read the current instruction. 196 */ 197 static inline uint32_t 198 read_insn(vaddr_t va, bool user_p) 199 { 200 uint32_t insn; 201 if (user_p) { 202 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 203 } else { 204 insn = *(const uint32_t *)va; 205 } 206 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 207 insn = bswap32(insn); 208 #endif 209 return insn; 210 } 211 212 /* 213 * Used by the fault code to read the current thumb instruction. 214 */ 215 static inline uint32_t 216 read_thumb_insn(vaddr_t va, bool user_p) 217 { 218 va &= ~1; 219 uint32_t insn; 220 if (user_p) { 221 #ifdef _ARM_ARCH_T2 222 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 223 #else 224 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 225 #ifdef __ARMEB__ 226 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 227 #else 228 insn = (uint16_t) (insn >> ((va & 2) << 3)); 229 #endif 230 #endif 231 } else { 232 insn = *(const uint16_t *)va; 233 } 234 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 235 insn = bswap16(insn); 236 #endif 237 return insn; 238 } 239 240 #ifndef _RUMPKERNEL 241 static inline void 242 arm_dmb(void) 243 { 244 if (CPU_IS_ARMV6_P()) 245 armreg_dmb_write(0); 246 else if (CPU_IS_ARMV7_P()) 247 __asm __volatile("dmb"); 248 } 249 250 static inline void 251 arm_dsb(void) 252 { 253 if (CPU_IS_ARMV6_P()) 254 armreg_dsb_write(0); 255 else if (CPU_IS_ARMV7_P()) 256 __asm __volatile("dsb"); 257 } 258 259 static inline void 260 arm_isb(void) 261 { 262 if (CPU_IS_ARMV6_P()) 263 armreg_isb_write(0); 264 else if (CPU_IS_ARMV7_P()) 265 __asm __volatile("isb"); 266 } 267 #endif 268 269 /* 270 * Random cruft 271 */ 272 273 struct lwp; 274 275 /* cpu.c */ 276 void identify_arm_cpu(device_t, struct cpu_info *); 277 278 /* cpuswitch.S */ 279 struct pcb; 280 void savectx(struct pcb *); 281 282 /* ast.c */ 283 void userret(struct lwp *); 284 285 /* *_machdep.c */ 286 void bootsync(void); 287 288 /* fault.c */ 289 int badaddr_read(void *, size_t, void *); 290 291 /* syscall.c */ 292 void swi_handler(trapframe_t *); 293 294 /* arm_machdep.c */ 295 void ucas_ras_check(trapframe_t *); 296 297 /* vfp_init.c */ 298 void vfp_attach(struct cpu_info *); 299 void vfp_discardcontext(bool); 300 void vfp_savecontext(void); 301 void vfp_kernel_acquire(void); 302 void vfp_kernel_release(void); 303 bool vfp_used_p(void); 304 extern const pcu_ops_t arm_vfp_ops; 305 306 #endif /* !_LOCORE */ 307 308 #endif /* !_ARM_LOCORE_H_ */ 309
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