locore.h revision 1.20
1 /* $NetBSD: locore.h,v 1.20 2015/03/29 09:49:54 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef _KERNEL_OPT 52 #include "opt_cpuoptions.h" 53 #include "opt_cputypes.h" 54 #include "opt_arm_debug.h" 55 #endif 56 57 #include <arm/cpuconf.h> 58 #include <arm/armreg.h> 59 60 #include <machine/frame.h> 61 62 #ifdef _LOCORE 63 64 #if defined(_ARM_ARCH_6) 65 #define IRQdisable cpsid i 66 #define IRQenable cpsie i 67 #elif defined(__PROG32) 68 #define IRQdisable \ 69 stmfd sp!, {r0} ; \ 70 mrs r0, cpsr ; \ 71 orr r0, r0, #(I32_bit) ; \ 72 msr cpsr_c, r0 ; \ 73 ldmfd sp!, {r0} 74 75 #define IRQenable \ 76 stmfd sp!, {r0} ; \ 77 mrs r0, cpsr ; \ 78 bic r0, r0, #(I32_bit) ; \ 79 msr cpsr_c, r0 ; \ 80 ldmfd sp!, {r0} 81 #else 82 /* Not yet used in 26-bit code */ 83 #endif 84 85 #if defined (TPIDRPRW_IS_CURCPU) 86 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 87 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 88 #elif defined (TPIDRPRW_IS_CURLWP) 89 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 90 #if defined (MULTIPROCESSOR) 91 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 92 #elif defined(_ARM_ARCH_7) 93 #define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store 94 #else 95 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 96 #endif 97 #elif !defined(MULTIPROCESSOR) 98 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 99 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 100 #endif 101 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 102 103 #else /* !_LOCORE */ 104 105 #include <arm/cpufunc.h> 106 107 #ifdef __PROG32 108 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 109 #define IRQenable __set_cpsr_c(I32_bit, 0); 110 #else 111 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE); 112 #define IRQenable set_r15(R15_IRQ_DISABLE, 0); 113 #endif 114 115 /* 116 * Validate a PC or PSR for a user process. Used by various system calls 117 * that take a context passed by the user and restore it. 118 */ 119 120 #ifdef __PROG32 121 #ifdef __NO_FIQ 122 #define VALID_R15_PSR(r15,psr) \ 123 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0) 124 #else 125 #define VALID_R15_PSR(r15,psr) \ 126 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0) 127 #endif 128 #else 129 #define VALID_R15_PSR(r15,psr) \ 130 (((r15) & R15_MODE) == R15_MODE_USR && \ 131 ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0) 132 #endif 133 134 135 136 /* The address of the vector page. */ 137 extern vaddr_t vector_page; 138 #ifdef __PROG32 139 void arm32_vector_init(vaddr_t, int); 140 141 #define ARM_VEC_RESET (1 << 0) 142 #define ARM_VEC_UNDEFINED (1 << 1) 143 #define ARM_VEC_SWI (1 << 2) 144 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 145 #define ARM_VEC_DATA_ABORT (1 << 4) 146 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 147 #define ARM_VEC_IRQ (1 << 6) 148 #define ARM_VEC_FIQ (1 << 7) 149 150 #define ARM_NVEC 8 151 #define ARM_VEC_ALL 0xffffffff 152 #endif /* __PROG32 */ 153 154 #ifndef acorn26 155 /* 156 * cpu device glue (belongs in cpuvar.h) 157 */ 158 void cpu_attach(device_t, cpuid_t); 159 #endif 160 161 /* 1 == use cpu_sleep(), 0 == don't */ 162 extern int cpu_do_powersave; 163 extern int cpu_printfataltraps; 164 extern int cpu_fpu_present; 165 extern int cpu_hwdiv_present; 166 extern int cpu_neon_present; 167 extern int cpu_simd_present; 168 extern int cpu_simdex_present; 169 extern int cpu_umull_present; 170 extern int cpu_synchprim_present; 171 172 extern int cpu_instruction_set_attributes[6]; 173 extern int cpu_memory_model_features[4]; 174 extern int cpu_processor_features[2]; 175 extern int cpu_media_and_vfp_features[2]; 176 177 extern bool arm_has_tlbiasid_p; 178 #ifdef MULTIPROCESSOR 179 extern u_int arm_cpu_max; 180 extern volatile u_int arm_cpu_hatched; 181 #endif 182 183 #if !defined(CPU_ARMV7) 184 #define CPU_IS_ARMV7_P() false 185 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 186 extern bool cpu_armv7_p; 187 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 188 #else 189 #define CPU_IS_ARMV7_P() true 190 #endif 191 #if !defined(CPU_ARMV6) 192 #define CPU_IS_ARMV6_P() false 193 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 194 extern bool cpu_armv6_p; 195 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 196 #else 197 #define CPU_IS_ARMV6_P() true 198 #endif 199 200 /* 201 * Used by the fault code to read the current instruction. 202 */ 203 static inline uint32_t 204 read_insn(vaddr_t va, bool user_p) 205 { 206 uint32_t insn; 207 if (user_p) { 208 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 209 } else { 210 insn = *(const uint32_t *)va; 211 } 212 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 213 insn = bswap32(insn); 214 #endif 215 return insn; 216 } 217 218 /* 219 * Used by the fault code to read the current thumb instruction. 220 */ 221 static inline uint32_t 222 read_thumb_insn(vaddr_t va, bool user_p) 223 { 224 va &= ~1; 225 uint32_t insn; 226 if (user_p) { 227 #ifdef _ARM_ARCH_T2 228 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 229 #else 230 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 231 #ifdef __ARMEB__ 232 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 233 #else 234 insn = (uint16_t) (insn >> ((va & 2) << 3)); 235 #endif 236 #endif 237 } else { 238 insn = *(const uint16_t *)va; 239 } 240 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 241 insn = bswap16(insn); 242 #endif 243 return insn; 244 } 245 246 #ifndef _RUMPKERNEL 247 static inline void 248 arm_dmb(void) 249 { 250 if (CPU_IS_ARMV6_P()) 251 armreg_dmb_write(0); 252 else if (CPU_IS_ARMV7_P()) 253 __asm __volatile("dmb" ::: "memory"); 254 } 255 256 static inline void 257 arm_dsb(void) 258 { 259 if (CPU_IS_ARMV6_P()) 260 armreg_dsb_write(0); 261 else if (CPU_IS_ARMV7_P()) 262 __asm __volatile("dsb" ::: "memory"); 263 } 264 265 static inline void 266 arm_isb(void) 267 { 268 if (CPU_IS_ARMV6_P()) 269 armreg_isb_write(0); 270 else if (CPU_IS_ARMV7_P()) 271 __asm __volatile("isb" ::: "memory"); 272 } 273 #endif 274 275 /* 276 * Random cruft 277 */ 278 279 struct lwp; 280 281 /* cpu.c */ 282 void identify_arm_cpu(device_t, struct cpu_info *); 283 284 /* cpuswitch.S */ 285 struct pcb; 286 void savectx(struct pcb *); 287 288 /* ast.c */ 289 void userret(struct lwp *); 290 291 /* *_machdep.c */ 292 void bootsync(void); 293 294 /* fault.c */ 295 int badaddr_read(void *, size_t, void *); 296 297 /* syscall.c */ 298 void swi_handler(trapframe_t *); 299 300 /* arm_machdep.c */ 301 void ucas_ras_check(trapframe_t *); 302 303 /* vfp_init.c */ 304 void vfp_attach(struct cpu_info *); 305 void vfp_discardcontext(bool); 306 void vfp_savecontext(void); 307 void vfp_kernel_acquire(void); 308 void vfp_kernel_release(void); 309 bool vfp_used_p(void); 310 extern const pcu_ops_t arm_vfp_ops; 311 312 #endif /* !_LOCORE */ 313 314 #endif /* !_ARM_LOCORE_H_ */ 315
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