locore.h revision 1.29
1 /* $NetBSD: locore.h,v 1.29 2018/01/24 09:04:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef _KERNEL_OPT 52 #include "opt_cpuoptions.h" 53 #include "opt_cputypes.h" 54 #include "opt_arm_debug.h" 55 #endif 56 57 #include <sys/pcu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/armreg.h> 61 62 #include <machine/frame.h> 63 64 #ifdef _LOCORE 65 66 #if defined(_ARM_ARCH_6) 67 #define IRQdisable cpsid i 68 #define IRQenable cpsie i 69 #else 70 #define IRQdisable \ 71 stmfd sp!, {r0} ; \ 72 mrs r0, cpsr ; \ 73 orr r0, r0, #(I32_bit) ; \ 74 msr cpsr_c, r0 ; \ 75 ldmfd sp!, {r0} 76 77 #define IRQenable \ 78 stmfd sp!, {r0} ; \ 79 mrs r0, cpsr ; \ 80 bic r0, r0, #(I32_bit) ; \ 81 msr cpsr_c, r0 ; \ 82 ldmfd sp!, {r0} 83 #endif 84 85 #if defined (TPIDRPRW_IS_CURCPU) 86 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 87 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 88 #elif defined (TPIDRPRW_IS_CURLWP) 89 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 90 #if defined (MULTIPROCESSOR) 91 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 92 #elif defined(_ARM_ARCH_7) 93 #define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store 94 #else 95 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 96 #endif 97 #elif !defined(MULTIPROCESSOR) 98 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 99 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 100 #endif 101 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 102 103 #else /* !_LOCORE */ 104 105 #include <arm/cpufunc.h> 106 107 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 108 #define IRQenable __set_cpsr_c(I32_bit, 0); 109 110 /* 111 * Validate a PC or PSR for a user process. Used by various system calls 112 * that take a context passed by the user and restore it. 113 */ 114 115 #ifdef __NO_FIQ 116 #define VALID_R15_PSR(r15,psr) \ 117 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0) 118 #else 119 #define VALID_R15_PSR(r15,psr) \ 120 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0) 121 #endif 122 123 /* 124 * Translation Table Base Register Share/Cache settings 125 */ 126 #define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C) 127 #define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA) 128 129 /* The address of the vector page. */ 130 extern vaddr_t vector_page; 131 void arm32_vector_init(vaddr_t, int); 132 133 #define ARM_VEC_RESET (1 << 0) 134 #define ARM_VEC_UNDEFINED (1 << 1) 135 #define ARM_VEC_SWI (1 << 2) 136 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 137 #define ARM_VEC_DATA_ABORT (1 << 4) 138 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 139 #define ARM_VEC_IRQ (1 << 6) 140 #define ARM_VEC_FIQ (1 << 7) 141 142 #define ARM_NVEC 8 143 #define ARM_VEC_ALL 0xffffffff 144 145 /* 146 * cpu device glue (belongs in cpuvar.h) 147 */ 148 void cpu_attach(device_t, cpuid_t); 149 150 /* 1 == use cpu_sleep(), 0 == don't */ 151 extern int cpu_do_powersave; 152 extern int cpu_printfataltraps; 153 extern int cpu_fpu_present; 154 extern int cpu_hwdiv_present; 155 extern int cpu_neon_present; 156 extern int cpu_simd_present; 157 extern int cpu_simdex_present; 158 extern int cpu_umull_present; 159 extern int cpu_synchprim_present; 160 161 extern int cpu_instruction_set_attributes[6]; 162 extern int cpu_memory_model_features[4]; 163 extern int cpu_processor_features[2]; 164 extern int cpu_media_and_vfp_features[2]; 165 166 extern bool arm_has_tlbiasid_p; 167 extern bool arm_has_mpext_p; 168 #ifdef MULTIPROCESSOR 169 extern u_int arm_cpu_max; 170 extern volatile u_int arm_cpu_hatched; 171 #endif 172 173 #if !defined(CPU_ARMV7) 174 #define CPU_IS_ARMV7_P() false 175 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 176 extern bool cpu_armv7_p; 177 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 178 #else 179 #define CPU_IS_ARMV7_P() true 180 #endif 181 #if !defined(CPU_ARMV6) 182 #define CPU_IS_ARMV6_P() false 183 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 184 extern bool cpu_armv6_p; 185 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 186 #else 187 #define CPU_IS_ARMV6_P() true 188 #endif 189 190 /* 191 * Used by the fault code to read the current instruction. 192 */ 193 static inline uint32_t 194 read_insn(vaddr_t va, bool user_p) 195 { 196 uint32_t insn; 197 if (user_p) { 198 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 199 } else { 200 insn = *(const uint32_t *)va; 201 } 202 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 203 insn = bswap32(insn); 204 #endif 205 return insn; 206 } 207 208 /* 209 * Used by the fault code to read the current thumb instruction. 210 */ 211 static inline uint32_t 212 read_thumb_insn(vaddr_t va, bool user_p) 213 { 214 va &= ~1; 215 uint32_t insn; 216 if (user_p) { 217 #if defined(__thumb__) && defined(_ARM_ARCH_T2) 218 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va)); 219 #elif defined(_ARM_ARCH_7) 220 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 221 #else 222 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 223 #ifdef __ARMEB__ 224 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 225 #else 226 insn = (uint16_t) (insn >> ((va & 2) << 3)); 227 #endif 228 #endif 229 } else { 230 insn = *(const uint16_t *)va; 231 } 232 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 233 insn = bswap16(insn); 234 #endif 235 return insn; 236 } 237 238 #ifndef _RUMPKERNEL 239 static inline void 240 arm_dmb(void) 241 { 242 if (CPU_IS_ARMV6_P()) 243 armreg_dmb_write(0); 244 else if (CPU_IS_ARMV7_P()) 245 __asm __volatile("dmb" ::: "memory"); 246 } 247 248 static inline void 249 arm_dsb(void) 250 { 251 if (CPU_IS_ARMV6_P()) 252 armreg_dsb_write(0); 253 else if (CPU_IS_ARMV7_P()) 254 __asm __volatile("dsb" ::: "memory"); 255 } 256 257 static inline void 258 arm_isb(void) 259 { 260 if (CPU_IS_ARMV6_P()) 261 armreg_isb_write(0); 262 else if (CPU_IS_ARMV7_P()) 263 __asm __volatile("isb" ::: "memory"); 264 } 265 #endif 266 267 /* 268 * Random cruft 269 */ 270 271 struct lwp; 272 273 /* cpu.c */ 274 void identify_arm_cpu(device_t, struct cpu_info *); 275 276 /* cpuswitch.S */ 277 struct pcb; 278 void savectx(struct pcb *); 279 280 /* ast.c */ 281 void userret(struct lwp *); 282 283 /* *_machdep.c */ 284 void bootsync(void); 285 286 /* fault.c */ 287 int badaddr_read(void *, size_t, void *); 288 289 /* syscall.c */ 290 void swi_handler(trapframe_t *); 291 292 /* arm_machdep.c */ 293 void ucas_ras_check(trapframe_t *); 294 295 /* vfp_init.c */ 296 void vfp_attach(struct cpu_info *); 297 void vfp_discardcontext(lwp_t *, bool); 298 void vfp_savecontext(lwp_t *); 299 void vfp_kernel_acquire(void); 300 void vfp_kernel_release(void); 301 bool vfp_used_p(const lwp_t *); 302 extern const pcu_ops_t arm_vfp_ops; 303 304 #endif /* !_LOCORE */ 305 306 #endif /* !_ARM_LOCORE_H_ */ 307
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