locore.h revision 1.30
1 /* $NetBSD: locore.h,v 1.30 2018/04/01 04:35:04 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef __arm__ 52 53 #ifdef _KERNEL_OPT 54 #include "opt_cpuoptions.h" 55 #include "opt_cputypes.h" 56 #include "opt_arm_debug.h" 57 #endif 58 59 #include <sys/pcu.h> 60 61 #include <arm/cpuconf.h> 62 #include <arm/armreg.h> 63 64 #include <machine/frame.h> 65 66 #ifdef _LOCORE 67 68 #if defined(_ARM_ARCH_6) 69 #define IRQdisable cpsid i 70 #define IRQenable cpsie i 71 #else 72 #define IRQdisable \ 73 stmfd sp!, {r0} ; \ 74 mrs r0, cpsr ; \ 75 orr r0, r0, #(I32_bit) ; \ 76 msr cpsr_c, r0 ; \ 77 ldmfd sp!, {r0} 78 79 #define IRQenable \ 80 stmfd sp!, {r0} ; \ 81 mrs r0, cpsr ; \ 82 bic r0, r0, #(I32_bit) ; \ 83 msr cpsr_c, r0 ; \ 84 ldmfd sp!, {r0} 85 #endif 86 87 #if defined (TPIDRPRW_IS_CURCPU) 88 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 89 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 90 #elif defined (TPIDRPRW_IS_CURLWP) 91 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 92 #if defined (MULTIPROCESSOR) 93 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 94 #elif defined(_ARM_ARCH_7) 95 #define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store 96 #else 97 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 98 #endif 99 #elif !defined(MULTIPROCESSOR) 100 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 101 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 102 #endif 103 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 104 105 #else /* !_LOCORE */ 106 107 #include <arm/cpufunc.h> 108 109 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 110 #define IRQenable __set_cpsr_c(I32_bit, 0); 111 112 /* 113 * Validate a PC or PSR for a user process. Used by various system calls 114 * that take a context passed by the user and restore it. 115 */ 116 117 #ifdef __NO_FIQ 118 #define VALID_R15_PSR(r15,psr) \ 119 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0) 120 #else 121 #define VALID_R15_PSR(r15,psr) \ 122 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0) 123 #endif 124 125 /* 126 * Translation Table Base Register Share/Cache settings 127 */ 128 #define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C) 129 #define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA) 130 131 /* The address of the vector page. */ 132 extern vaddr_t vector_page; 133 void arm32_vector_init(vaddr_t, int); 134 135 #define ARM_VEC_RESET (1 << 0) 136 #define ARM_VEC_UNDEFINED (1 << 1) 137 #define ARM_VEC_SWI (1 << 2) 138 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 139 #define ARM_VEC_DATA_ABORT (1 << 4) 140 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 141 #define ARM_VEC_IRQ (1 << 6) 142 #define ARM_VEC_FIQ (1 << 7) 143 144 #define ARM_NVEC 8 145 #define ARM_VEC_ALL 0xffffffff 146 147 /* 148 * cpu device glue (belongs in cpuvar.h) 149 */ 150 void cpu_attach(device_t, cpuid_t); 151 152 /* 1 == use cpu_sleep(), 0 == don't */ 153 extern int cpu_do_powersave; 154 extern int cpu_printfataltraps; 155 extern int cpu_fpu_present; 156 extern int cpu_hwdiv_present; 157 extern int cpu_neon_present; 158 extern int cpu_simd_present; 159 extern int cpu_simdex_present; 160 extern int cpu_umull_present; 161 extern int cpu_synchprim_present; 162 163 extern int cpu_instruction_set_attributes[6]; 164 extern int cpu_memory_model_features[4]; 165 extern int cpu_processor_features[2]; 166 extern int cpu_media_and_vfp_features[2]; 167 168 extern bool arm_has_tlbiasid_p; 169 extern bool arm_has_mpext_p; 170 #ifdef MULTIPROCESSOR 171 extern u_int arm_cpu_max; 172 extern volatile u_int arm_cpu_hatched; 173 #endif 174 175 #if !defined(CPU_ARMV7) 176 #define CPU_IS_ARMV7_P() false 177 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 178 extern bool cpu_armv7_p; 179 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 180 #else 181 #define CPU_IS_ARMV7_P() true 182 #endif 183 #if !defined(CPU_ARMV6) 184 #define CPU_IS_ARMV6_P() false 185 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 186 extern bool cpu_armv6_p; 187 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 188 #else 189 #define CPU_IS_ARMV6_P() true 190 #endif 191 192 /* 193 * Used by the fault code to read the current instruction. 194 */ 195 static inline uint32_t 196 read_insn(vaddr_t va, bool user_p) 197 { 198 uint32_t insn; 199 if (user_p) { 200 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 201 } else { 202 insn = *(const uint32_t *)va; 203 } 204 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 205 insn = bswap32(insn); 206 #endif 207 return insn; 208 } 209 210 /* 211 * Used by the fault code to read the current thumb instruction. 212 */ 213 static inline uint32_t 214 read_thumb_insn(vaddr_t va, bool user_p) 215 { 216 va &= ~1; 217 uint32_t insn; 218 if (user_p) { 219 #if defined(__thumb__) && defined(_ARM_ARCH_T2) 220 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va)); 221 #elif defined(_ARM_ARCH_7) 222 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 223 #else 224 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 225 #ifdef __ARMEB__ 226 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 227 #else 228 insn = (uint16_t) (insn >> ((va & 2) << 3)); 229 #endif 230 #endif 231 } else { 232 insn = *(const uint16_t *)va; 233 } 234 #if defined(__ARMEB__) && defined(_ARM_ARCH_7) 235 insn = bswap16(insn); 236 #endif 237 return insn; 238 } 239 240 #ifndef _RUMPKERNEL 241 static inline void 242 arm_dmb(void) 243 { 244 if (CPU_IS_ARMV6_P()) 245 armreg_dmb_write(0); 246 else if (CPU_IS_ARMV7_P()) 247 __asm __volatile("dmb" ::: "memory"); 248 } 249 250 static inline void 251 arm_dsb(void) 252 { 253 if (CPU_IS_ARMV6_P()) 254 armreg_dsb_write(0); 255 else if (CPU_IS_ARMV7_P()) 256 __asm __volatile("dsb" ::: "memory"); 257 } 258 259 static inline void 260 arm_isb(void) 261 { 262 if (CPU_IS_ARMV6_P()) 263 armreg_isb_write(0); 264 else if (CPU_IS_ARMV7_P()) 265 __asm __volatile("isb" ::: "memory"); 266 } 267 #endif 268 269 /* 270 * Random cruft 271 */ 272 273 struct lwp; 274 275 /* cpu.c */ 276 void identify_arm_cpu(device_t, struct cpu_info *); 277 278 /* cpuswitch.S */ 279 struct pcb; 280 void savectx(struct pcb *); 281 282 /* ast.c */ 283 void userret(struct lwp *); 284 285 /* *_machdep.c */ 286 void bootsync(void); 287 288 /* fault.c */ 289 int badaddr_read(void *, size_t, void *); 290 291 /* syscall.c */ 292 void swi_handler(trapframe_t *); 293 294 /* arm_machdep.c */ 295 void ucas_ras_check(trapframe_t *); 296 297 /* vfp_init.c */ 298 void vfp_attach(struct cpu_info *); 299 void vfp_discardcontext(lwp_t *, bool); 300 void vfp_savecontext(lwp_t *); 301 void vfp_kernel_acquire(void); 302 void vfp_kernel_release(void); 303 bool vfp_used_p(const lwp_t *); 304 extern const pcu_ops_t arm_vfp_ops; 305 306 #endif /* !_LOCORE */ 307 308 #elif defined(__aarch64__) 309 310 #include <aarch64/locore.h> 311 312 #endif /* __arm__/__aarch64__ */ 313 314 #endif /* !_ARM_LOCORE_H_ */ 315
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