locore.h revision 1.39
1 /* $NetBSD: locore.h,v 1.39 2025/10/07 10:35:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_LOCORE_H_ 49 #define _ARM_LOCORE_H_ 50 51 #ifdef __arm__ 52 53 #ifdef _KERNEL_OPT 54 #include "opt_cpuoptions.h" 55 #include "opt_cputypes.h" 56 #include "opt_arm_debug.h" 57 #endif 58 59 #include <sys/pcu.h> 60 61 #include <arm/cpuconf.h> 62 #include <arm/armreg.h> 63 64 #include <machine/frame.h> 65 66 #ifdef _LOCORE 67 68 #if defined(_ARM_ARCH_6) 69 #define IRQ_DISABLE(rTMP) cpsid i 70 #define IRQ_ENABLE(rTMP) cpsie i 71 #else 72 #define IRQ_DISABLE(rTMP) \ 73 mrs rTMP, cpsr ; \ 74 orr rTMP, rTMP, #(I32_bit) ; \ 75 msr cpsr_c, rTMP 76 77 #define IRQ_ENABLE(rTMP) \ 78 mrs rTMP, cpsr ; \ 79 bic rTMP, rTMP, #(I32_bit) ; \ 80 msr cpsr_c, rTMP 81 #endif 82 83 #if defined (TPIDRPRW_IS_CURCPU) 84 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 85 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 86 #define GET_CURX(rCPU, rLWP) GET_CURCPU(rCPU); ldr rLWP, [rCPU, #CI_CURLWP] 87 #elif defined (TPIDRPRW_IS_CURLWP) 88 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 89 #if defined (MULTIPROCESSOR) 90 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 91 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); ldr rCPU, [rLWP, #L_CPU] 92 #elif defined(_ARM_ARCH_7) 93 #define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store 94 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); GET_CURCPU(rCPU) 95 #else 96 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 97 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); ldr rCPU, [rLWP, #L_CPU] 98 #endif 99 #elif !defined(MULTIPROCESSOR) 100 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 101 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 102 #define GET_CURX(rCPU, rLWP) GET_CURCPU(rCPU); ldr rLWP, [rCPU, #CI_CURLWP] 103 #endif 104 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 105 106 #else /* !_LOCORE */ 107 108 #include <arm/cpufunc.h> 109 110 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 111 #define IRQenable __set_cpsr_c(I32_bit, 0); 112 113 /* 114 * Validate a PC or PSR for a user process. Used by various system calls 115 * that take a context passed by the user and restore it. 116 */ 117 118 #ifdef __NO_FIQ 119 #define VALID_PSR(psr) \ 120 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0) 121 #else 122 #define VALID_PSR(psr) \ 123 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0) 124 #endif 125 126 /* 127 * Translation Table Base Register Share/Cache settings 128 */ 129 #define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C) 130 #define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA) 131 132 /* The address of the vector page. */ 133 extern vaddr_t vector_page; 134 void arm32_vector_init(vaddr_t, int); 135 136 #define ARM_VEC_RESET (1 << 0) 137 #define ARM_VEC_UNDEFINED (1 << 1) 138 #define ARM_VEC_SWI (1 << 2) 139 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 140 #define ARM_VEC_DATA_ABORT (1 << 4) 141 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 142 #define ARM_VEC_IRQ (1 << 6) 143 #define ARM_VEC_FIQ (1 << 7) 144 145 #define ARM_NVEC 8 146 #define ARM_VEC_ALL 0xffffffff 147 148 /* 149 * cpu device glue (belongs in cpuvar.h) 150 */ 151 void cpu_attach(device_t, cpuid_t); 152 153 /* 1 == use cpu_sleep(), 0 == don't */ 154 extern int cpu_do_powersave; 155 extern int cpu_printfataltraps; 156 extern int cpu_fpu_present; 157 extern int cpu_hwdiv_present; 158 extern int cpu_neon_present; 159 extern int cpu_simd_present; 160 extern int cpu_simdex_present; 161 extern int cpu_umull_present; 162 extern int cpu_synchprim_present; 163 164 extern int cpu_instruction_set_attributes[6]; 165 extern int cpu_memory_model_features[4]; 166 extern int cpu_processor_features[2]; 167 extern int cpu_media_and_vfp_features[2]; 168 169 extern bool arm_has_tlbiasid_p; 170 extern bool arm_has_mpext_p; 171 172 #if !defined(CPU_ARMV7) 173 #define CPU_IS_ARMV7_P() false 174 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) 175 extern bool cpu_armv7_p; 176 #define CPU_IS_ARMV7_P() (cpu_armv7_p) 177 #else 178 #define CPU_IS_ARMV7_P() true 179 #endif 180 #if !defined(CPU_ARMV6) 181 #define CPU_IS_ARMV6_P() false 182 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6) 183 extern bool cpu_armv6_p; 184 #define CPU_IS_ARMV6_P() (cpu_armv6_p) 185 #else 186 #define CPU_IS_ARMV6_P() true 187 #endif 188 189 /* 190 * Used by the fault code to read the current instruction. 191 */ 192 static inline uint32_t 193 read_insn(vaddr_t va, bool user_p) 194 { 195 uint32_t insn; 196 if (user_p) { 197 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va)); 198 } else { 199 insn = *(const uint32_t *)va; 200 } 201 #ifdef _ARM_ARCH_BE8 202 insn = bswap32(insn); 203 #endif 204 return insn; 205 } 206 207 /* 208 * Used by the fault code to read the current thumb instruction. 209 */ 210 static inline uint32_t 211 read_thumb_insn(vaddr_t va, bool user_p) 212 { 213 va &= ~1; 214 uint32_t insn; 215 if (user_p) { 216 #if defined(__thumb__) && defined(_ARM_ARCH_T2) 217 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va)); 218 #elif defined(_ARM_ARCH_7) 219 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va)); 220 #else 221 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3)); 222 #ifdef __ARMEB__ 223 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3)); 224 #else 225 insn = (uint16_t) (insn >> ((va & 2) << 3)); 226 #endif 227 #endif 228 } else { 229 insn = *(const uint16_t *)va; 230 } 231 #ifdef _ARM_ARCH_BE8 232 insn = bswap16(insn); 233 #endif 234 return insn; 235 } 236 237 /* 238 * Random cruft 239 */ 240 241 struct lwp; 242 243 /* cpu.c */ 244 void identify_arm_cpu(device_t, struct cpu_info *); 245 246 /* cpuswitch.S */ 247 struct pcb; 248 void savectx(struct pcb *); 249 250 /* ast.c */ 251 void userret(struct lwp *); 252 253 /* *_machdep.c */ 254 void bootsync(void); 255 256 /* fault.c */ 257 int badaddr_read(void *, size_t, void *); 258 259 /* syscall.c */ 260 void swi_handler(trapframe_t *); 261 262 /* vfp_init.c */ 263 void vfp_detect(struct cpu_info *); 264 void vfp_attach(struct cpu_info *); 265 void vfp_discardcontext(lwp_t *, bool); 266 void vfp_savecontext(lwp_t *); 267 void vfp_kernel_acquire(void); 268 void vfp_kernel_release(void); 269 bool vfp_used_p(const lwp_t *); 270 extern const pcu_ops_t arm_vfp_ops; 271 272 #endif /* !_LOCORE */ 273 274 #elif defined(__aarch64__) 275 276 #include <aarch64/locore.h> 277 278 #endif /* __arm__/__aarch64__ */ 279 280 #endif /* !_ARM_LOCORE_H_ */ 281
Indexes created Wed Oct 29 20:09:47 GMT 2025