iomd_irq.S revision 1.14.4.2
1 /* $NetBSD: iomd_irq.S,v 1.14.4.2 2014/05/18 17:44:58 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42 #include "opt_irqstats.h" 43 44 #include "assym.h" 45 #include <arm/asm.h> 46 #include <arm/locore.h> 47 #include <arm/iomd/iomdreg.h> 48 49 .text 50 .align 0 51 /* 52 * ffs table used for servicing irq's quickly must be here otherwise adr can't 53 * reach it 54 * The algorithm for ffs was devised by D. Seal and posted to 55 * comp.sys.arm on 16 Feb 1994. 56 */ 57 .type Lirq_ffs_table, _ASM_TYPE_OBJECT; 58 Lirq_ffs_table: 59 /* same as ffs table but all nums are -1 from that */ 60 /* 0 1 2 3 4 5 6 7 */ 61 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 62 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 63 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 64 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 65 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 66 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 67 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 68 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 69 70 /* 71 * 72 * irq_entry 73 * 74 * Main entry point for the IRQ vector 75 * 76 * This function reads the irq request bits in the IOMD registers 77 * IRQRQA, IRQRQB and DMARQ 78 * It then calls an installed handler for each bit that is set. 79 * The function stray_irqhandler is called if a handler is not defined 80 * for a particular interrupt. 81 * If a interrupt handler is found then it is called with r0 containing 82 * the argument defined in the handler structure. If the field ih_arg 83 * is zero then a pointer to the IRQ frame on the stack is passed instead. 84 */ 85 86 Lcurrent_spl_level: 87 .word _C_LABEL(cpu_info_store) + CI_CPL 88 89 Ldisabled_mask: 90 .word _C_LABEL(disabled_mask) 91 92 Lspl_masks: 93 .word _C_LABEL(spl_masks) 94 95 LOCK_CAS_CHECK_LOCALS 96 97 AST_ALIGNMENT_FAULT_LOCALS 98 99 /* 100 * Register usage 101 * 102 * r4 - Address of cpu_info 103 * r5 - Address of ffs table 104 * r6 - Address of current handler 105 * r7 - Pointer to handler pointer list 106 * r8 - Current IRQ requests. 107 * r10 - Base address of IOMD 108 * r11 - IRQ requests still to service. 109 */ 110 111 Liomd_base: 112 .word _C_LABEL(iomd_base) 113 114 Larm7500_ioc_found: 115 .word _C_LABEL(arm7500_ioc_found) 116 117 ASENTRY_NP(irq_entry) 118 sub lr, lr, #0x00000004 /* Adjust the lr */ 119 120 PUSHFRAMEINSVC /* Push an interrupt frame */ 121 ENABLE_ALIGNMENT_FAULTS 122 123 str r7, [sp, #TF_FILL] /* save r7 */ 124 125 /* Load r8 with the IOMD interrupt requests */ 126 127 ldr r10, Liomd_base 128 ldr r10, [r10] /* Point to the IOMD */ 129 ldrb r8, [r10, #(IOMD_IRQRQA << 2)] /* Get IRQ request A */ 130 ldrb r9, [r10, #(IOMD_IRQRQB << 2)] /* Get IRQ request B */ 131 orr r8, r8, r9, lsl #8 132 133 ldr r9, Larm7500_ioc_found 134 ldr r9, [r9] /* get the flag */ 135 cmp r9, #0 136 beq skip_extended_IRQs_reading 137 138 /* ARM 7500 only */ 139 ldrb r9, [r10, #(IOMD_IRQRQC << 2)] /* Get IRQ request C */ 140 orr r8, r8, r9, lsl #16 141 ldrb r9, [r10, #(IOMD_IRQRQD << 2)] /* Get IRQ request D */ 142 orr r8, r8, r9, lsl #24 143 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 144 tst r9, #0x10 145 orrne r8, r8, r9, lsl #27 146 b irq_entry_continue 147 148 skip_extended_IRQs_reading: 149 /* non ARM7500 machines */ 150 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 151 orr r8, r8, r9, lsl #16 152 irq_entry_continue: 153 154 and r0, r8, #0x7d /* Clear IOMD IRQA bits */ 155 strb r0, [r10, #(IOMD_IRQRQA << 2)] 156 157 /* 158 * Note that we have entered the IRQ handler. 159 * We are in SVC mode so we cannot use the processor mode 160 * to determine if we are in an IRQ. Instead we will count the 161 * each time the interrupt handler is nested. 162 */ 163 164 ldr r0, [r4, #CI_INTR_DEPTH] 165 add r0, r0, #1 166 str r0, [r4, #CI_INTR_DEPTH] 167 168 /* Block the current requested interrupts */ 169 ldr r1, Ldisabled_mask 170 ldr r0, [r1] 171 stmfd sp!, {r0} 172 orr r0, r0, r8 173 174 /* 175 * Need to block all interrupts at the IPL or lower for 176 * all asserted interrupts. 177 * This basically emulates hardware interrupt priority levels. 178 * Means we need to go through the interrupt mask and for 179 * every asserted interrupt we need to mask out all other 180 * interrupts at the same or lower IPL. 181 * If only we could wait until the main loop but we need to sort 182 * this out first so interrupts can be re-enabled. 183 * 184 * This would benefit from a special ffs type routine 185 */ 186 187 mov r9, #(NIPL - 1) 188 ldr r7, Lspl_masks 189 190 Lfind_highest_ipl: 191 ldr r2, [r7, r9, lsl #2] 192 tst r8, r2 193 subeq r9, r9, #1 194 beq Lfind_highest_ipl 195 196 /* r9 = SPL level of highest priority interrupt */ 197 add r9, r9, #1 198 ldr r2, [r7, r9, lsl #2] 199 mvn r2, r2 200 orr r0, r0, r2 201 202 str r0, [r1] 203 204 ldr r0, [r4, #CI_CPL] 205 str r9, [r4, #CI_CPL] 206 stmfd sp!, {r0} 207 208 /* Update the IOMD irq masks */ 209 bl _C_LABEL(irq_setmasks) 210 211 mrs r0, cpsr /* Enable IRQ's */ 212 bic r0, r0, #I32_bit 213 msr cpsr_all, r0 214 215 ldr r7, Lirqhandlers 216 217 /* 218 * take a copy of the IRQ request so that we can strip bits out of it 219 * note that we only use 24 bits with iomd2 chips 220 */ 221 ldr r5, Larm7500_ioc_found 222 ldr r5, [r5] /* get the flag */ 223 cmp r5, #0 224 movne r11, r8 /* ARM7500 -> copy all bits */ 225 biceq r11, r8, #0xff000000 /* !ARM7500 -> only use 24 bit */ 226 227 /* ffs routine to find first irq to service */ 228 /* standard trick to isolate bottom bit in a0 or 0 if a0 = 0 on entry */ 229 rsb r5, r11, #0 230 ands r10, r11, r5 231 232 /* 233 * now r10 has at most 1 set bit, call this X 234 * if X = 0, branch to exit code 235 */ 236 beq exitirq 237 irqloop: 238 adr r5, Lirq_ffs_table 239 /* 240 * at this point: 241 * r5 = address of ffs table 242 * r7 = address of irq handlers table 243 * r8 = irq request 244 * r10 = bit of irq to be serviced 245 * r11 = bitmask of IRQ's to service 246 */ 247 248 /* find the set bit */ 249 orr r9, r10, r10, lsl #4 /* X * 0x11 */ 250 orr r9, r9, r9, lsl #6 /* X * 0x451 */ 251 rsb r9, r9, r9, lsl #16 /* X * 0x0450fbaf */ 252 /* fetch the bit number */ 253 ldrb r9, [r5, r9, lsr #26 ] 254 255 /* 256 * r9 = irq to service 257 */ 258 259 /* apologies for the dogs dinner of code here, but it's in an attempt 260 * to minimise stalling on SA's, hence lots of things happen here: 261 * - getting address of handler, if it doesn't exist we call 262 * stray_irqhandler this is assumed to be rare so we don't 263 * care about performance for it 264 * - statinfo is updated 265 * - unsetting of the irq bit in r11 266 * - irq stats (if enabled) also get put in the mix 267 */ 268 ldr r6, [r7, r9, lsl #2] /* Get address of first handler structure */ 269 270 teq r6, #0x00000000 /* Do we have a handler */ 271 moveq r0, r8 /* IRQ requests as arg 0 */ 272 adreq lr, nextirq /* return Address */ 273 beq _C_LABEL(stray_irqhandler) /* call special handler */ 274 275 /* stat info C */ 276 ldr r1, [r4, #(CI_CC_NINTR)] /* Stat info B */ 277 ldr r2, [r4, #(CI_CC_NINTR+4)] 278 #ifdef _ARMEL 279 adds r1, r1, #0x00000001 280 adc r2, r2, #0x00000000 281 #else 282 adds r2, r2, #0x00000001 283 adc r1, r1, #0x00000000 284 #endif 285 str r1, [r4, #(CI_CC_NINTR)] 286 str r2, [r4, #(CI_CC_NINTR+4)] 287 288 #ifdef IRQSTATS 289 ldr r2, Lintrcnt 290 ldr r3, [r6, #(IH_NUM)] 291 ldr r3, [r2, r3, lsl #2]! 292 #endif 293 bic r11, r11, r10 /* clear the IRQ bit */ 294 295 #ifdef IRQSTATS 296 add r3, r3, #0x00000001 297 str r3, [r2] 298 #endif /* IRQSTATS */ 299 300 irqchainloop: 301 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 302 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 303 addeq r0, sp, #8 /* ... stack frame [XXX needs care] */ 304 mov lr, pc /* return address */ 305 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 306 307 ldr r6, [r6, #(IH_NEXT)] /* fetch next handler */ 308 309 teq r0, #0x00000001 /* Was the irq serviced ? */ 310 311 /* if it was it'll just fall through this: */ 312 teqne r6, #0x00000000 313 bne irqchainloop 314 nextirq: 315 /* Check for next irq */ 316 rsb r5, r11, #0 317 ands r10, r11, r5 318 /* check if there are anymore irq's to service */ 319 bne irqloop 320 321 exitirq: 322 ldmfd sp!, {r2, r3} 323 ldr r0, Ldisabled_mask 324 str r2, [r4, #CI_CPL] 325 str r3, [r0] 326 327 bl _C_LABEL(irq_setmasks) 328 329 #if __HAVE_FAST_SOFTINTS 330 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 331 #endif 332 333 /* Kill IRQ's in preparation for exit */ 334 mrs r0, cpsr 335 orr r0, r0, #(I32_bit) 336 msr cpsr_all, r0 337 338 /* Decrement the nest count */ 339 ldr r0, [r4, #CI_INTR_DEPTH] 340 sub r0, r0, #1 341 str r0, [r4, #CI_INTR_DEPTH] 342 343 ldr r7, [sp, #TF_FILL] /* restore r7 */ 344 LOCK_CAS_CHECK 345 346 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 347 PULLFRAMEFROMSVCANDEXIT 348 349 /* NOT REACHED */ 350 b . - 8 351 352 Lcurrent_mask: 353 .word _C_LABEL(current_mask) /* irq's that are usable */ 354 355 ENTRY(irq_setmasks) 356 /* Disable interrupts */ 357 mrs r3, cpsr 358 orr r1, r3, #(I32_bit) 359 msr cpsr_all, r1 360 361 /* Calculate IOMD interrupt mask */ 362 ldr r1, Lcurrent_mask /* All the enabled interrupts */ 363 ldr r1, [r1] 364 ldr r0, Lspl_masks /* Block due to current spl level */ 365 ldr r2, Lcurrent_spl_level 366 ldr r2, [r2] 367 ldr r2, [r0, r2, lsl #2] 368 and r1, r1, r2 369 ldr r2, Ldisabled_mask /* Block due to active interrupts */ 370 ldr r2, [r2] 371 bic r1, r1, r2 372 373 ldr r0, Liomd_base 374 ldr r0, [r0] /* Point to the IOMD */ 375 strb r1, [r0, #(IOMD_IRQMSKA << 2)] /* Set IRQ mask A */ 376 mov r1, r1, lsr #8 377 strb r1, [r0, #(IOMD_IRQMSKB << 2)] /* Set IRQ mask B */ 378 mov r1, r1, lsr #8 379 380 ldr r2, Larm7500_ioc_found 381 ldr r2, [r2] 382 cmp r2, #0 383 beq skip_setting_extended_DMA_mask 384 385 /* only for ARM7500's */ 386 strb r1, [r0, #(IOMD_IRQMSKC << 2)] 387 mov r1, r1, lsr #8 388 and r2, r1, #0xef 389 strb r2, [r0, #(IOMD_IRQMSKD << 2)] 390 mov r1, r1, lsr #3 391 and r2, r1, #0x10 392 strb r2, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 393 b continue_setting_masks 394 395 skip_setting_extended_DMA_mask: 396 /* non ARM7500's */ 397 strb r1, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 398 399 continue_setting_masks: 400 401 /* Restore old cpsr and exit */ 402 msr cpsr_all, r3 403 mov pc, lr 404 405 Lintrcnt: 406 .word _C_LABEL(intrcnt) 407 408 409 Lirqhandlers: 410 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 411 412 #ifdef IRQSTATS 413 /* These symbols are used by vmstat */ 414 415 .section .rodata 416 417 .global _C_LABEL(_intrnames) 418 _C_LABEL(_intrnames): 419 .word _C_LABEL(intrnames) 420 421 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 422 _C_LABEL(intrnames): 423 .asciz "interrupt 0 " 424 .asciz "interrupt 1 " /* reserved0 */ 425 .asciz "interrupt 2 " 426 .asciz "interrupt 3 " 427 .asciz "interrupt 4 " 428 .asciz "interrupt 5 " 429 .asciz "interrupt 6 " 430 .asciz "interrupt 7 " /* reserved1 */ 431 .asciz "interrupt 8 " /* reserved2 */ 432 .asciz "interrupt 9 " 433 .asciz "interrupt 10 " 434 .asciz "interrupt 11 " 435 .asciz "interrupt 12 " 436 .asciz "interrupt 13 " 437 .asciz "interrupt 14 " 438 .asciz "interrupt 15 " 439 .asciz "dma channel 0" 440 .asciz "dma channel 1" 441 .asciz "dma channel 2" 442 .asciz "dma channel 3" 443 .asciz "interrupt 20 " 444 .asciz "interrupt 21 " 445 .asciz "reserved 3 " 446 .asciz "reserved 4 " 447 .asciz "exp card 0 " 448 .asciz "exp card 1 " 449 .asciz "exp card 2 " 450 .asciz "exp card 3 " 451 .asciz "exp card 4 " 452 .asciz "exp card 5 " 453 .asciz "exp card 6 " 454 .asciz "exp card 7 " 455 456 _C_LABEL(sintrnames): 457 .asciz "softclock " 458 .asciz "softnet " 459 .asciz "softserial " 460 .asciz "softintr 3 " 461 .asciz "softintr 4 " 462 .asciz "softintr 5 " 463 .asciz "softintr 6 " 464 .asciz "softintr 7 " 465 .asciz "softintr 8 " 466 .asciz "softintr 9 " 467 .asciz "softintr 10 " 468 .asciz "softintr 11 " 469 .asciz "softintr 12 " 470 .asciz "softintr 13 " 471 .asciz "softintr 14 " 472 .asciz "softintr 15 " 473 .asciz "softintr 16 " 474 .asciz "softintr 17 " 475 .asciz "softintr 18 " 476 .asciz "softintr 19 " 477 .asciz "softintr 20 " 478 .asciz "softintr 21 " 479 .asciz "softintr 22 " 480 .asciz "softintr 23 " 481 .asciz "softintr 24 " 482 .asciz "softintr 25 " 483 .asciz "softintr 26 " 484 .asciz "softintr 27 " 485 .asciz "softintr 28 " 486 .asciz "softintr 29 " 487 .asciz "softintr 30 " 488 .asciz "softintr 31 " 489 _C_LABEL(eintrnames): 490 491 .bss 492 .align 0 493 _C_LABEL(intrcnt): 494 .space 32*4 /* XXX Should be linked to number of interrupts */ 495 496 _C_LABEL(sintrcnt): 497 .space 32*4 /* XXX Should be linked to number of interrupts */ 498 _C_LABEL(eintrcnt): 499 500 #else /* IRQSTATS */ 501 /* Dummy entries to keep vmstat happy */ 502 503 .section .rodata 504 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 505 _C_LABEL(intrnames): 506 .long 0 507 _C_LABEL(eintrnames): 508 509 _C_LABEL(intrcnt): 510 .long 0 511 _C_LABEL(eintrcnt): 512 #endif /* IRQSTATS */ 513
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