iomd_irq.S revision 1.16.42.1
1 /* $NetBSD: iomd_irq.S,v 1.16.42.1 2020/12/14 14:37:49 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42 #include "opt_irqstats.h" 43 44 #include "assym.h" 45 #include <arm/asm.h> 46 #include <arm/locore.h> 47 #include <arm/iomd/iomdreg.h> 48 49 .text 50 .align 0 51 /* 52 * ffs table used for servicing irq's quickly must be here otherwise adr can't 53 * reach it 54 * The algorithm for ffs was devised by D. Seal and posted to 55 * comp.sys.arm on 16 Feb 1994. 56 */ 57 .type Lirq_ffs_table, _ASM_TYPE_OBJECT; 58 Lirq_ffs_table: 59 /* same as ffs table but all nums are -1 from that */ 60 /* 0 1 2 3 4 5 6 7 */ 61 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 62 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 63 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 64 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 65 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 66 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 67 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 68 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 69 70 /* 71 * 72 * irq_entry 73 * 74 * Main entry point for the IRQ vector 75 * 76 * This function reads the irq request bits in the IOMD registers 77 * IRQRQA, IRQRQB and DMARQ 78 * It then calls an installed handler for each bit that is set. 79 * The function stray_irqhandler is called if a handler is not defined 80 * for a particular interrupt. 81 * If a interrupt handler is found then it is called with r0 containing 82 * the argument defined in the handler structure. If the field ih_arg 83 * is zero then a pointer to the IRQ frame on the stack is passed instead. 84 */ 85 86 Lcurrent_spl_level: 87 .word _C_LABEL(cpu_info_store) + CI_CPL 88 89 Ldisabled_mask: 90 .word _C_LABEL(disabled_mask) 91 92 Lspl_masks: 93 .word _C_LABEL(spl_masks) 94 95 LOCK_CAS_CHECK_LOCALS 96 97 AST_ALIGNMENT_FAULT_LOCALS 98 99 /* 100 * Register usage 101 * 102 * r4 - Address of cpu_info 103 * r5 - Address of curlwp 104 * r6 - Address of current handler 105 * r7 - Pointer to handler pointer list 106 * r8 - Current IRQ requests. 107 * r9 - scratch 108 * r10 - Base address of IOMD 109 * r11 - IRQ requests still to service. 110 */ 111 112 Liomd_base: 113 .word _C_LABEL(iomd_base) 114 115 Larm7500_ioc_found: 116 .word _C_LABEL(arm7500_ioc_found) 117 118 ASENTRY_NP(irq_entry) 119 sub lr, lr, #0x00000004 /* Adjust the lr */ 120 121 PUSHFRAMEINSVC /* Push an interrupt frame */ 122 ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */ 123 124 str r7, [sp, #TF_FILL] /* save r7 */ 125 126 /* Load r8 with the IOMD interrupt requests */ 127 128 ldr r10, Liomd_base 129 ldr r10, [r10] /* Point to the IOMD */ 130 ldrb r8, [r10, #(IOMD_IRQRQA << 2)] /* Get IRQ request A */ 131 ldrb r9, [r10, #(IOMD_IRQRQB << 2)] /* Get IRQ request B */ 132 orr r8, r8, r9, lsl #8 133 134 ldr r9, Larm7500_ioc_found 135 ldr r9, [r9] /* get the flag */ 136 cmp r9, #0 137 beq skip_extended_IRQs_reading 138 139 /* ARM 7500 only */ 140 ldrb r9, [r10, #(IOMD_IRQRQC << 2)] /* Get IRQ request C */ 141 orr r8, r8, r9, lsl #16 142 ldrb r9, [r10, #(IOMD_IRQRQD << 2)] /* Get IRQ request D */ 143 orr r8, r8, r9, lsl #24 144 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 145 tst r9, #0x10 146 orrne r8, r8, r9, lsl #27 147 b irq_entry_continue 148 149 skip_extended_IRQs_reading: 150 /* non ARM7500 machines */ 151 ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */ 152 orr r8, r8, r9, lsl #16 153 irq_entry_continue: 154 155 and r0, r8, #0x7d /* Clear IOMD IRQA bits */ 156 strb r0, [r10, #(IOMD_IRQRQA << 2)] 157 158 /* 159 * Note that we have entered the IRQ handler. 160 * We are in SVC mode so we cannot use the processor mode 161 * to determine if we are in an IRQ. Instead we will count the 162 * each time the interrupt handler is nested. 163 */ 164 165 ldr r0, [r4, #CI_INTR_DEPTH] 166 add r0, r0, #1 167 str r0, [r4, #CI_INTR_DEPTH] 168 169 /* Block the current requested interrupts */ 170 ldr r1, Ldisabled_mask 171 ldr r0, [r1] 172 stmfd sp!, {r0} 173 orr r0, r0, r8 174 175 /* 176 * Need to block all interrupts at the IPL or lower for 177 * all asserted interrupts. 178 * This basically emulates hardware interrupt priority levels. 179 * Means we need to go through the interrupt mask and for 180 * every asserted interrupt we need to mask out all other 181 * interrupts at the same or lower IPL. 182 * If only we could wait until the main loop but we need to sort 183 * this out first so interrupts can be re-enabled. 184 * 185 * This would benefit from a special ffs type routine 186 */ 187 188 mov r9, #(NIPL - 1) 189 ldr r7, Lspl_masks 190 191 Lfind_highest_ipl: 192 ldr r2, [r7, r9, lsl #2] 193 tst r8, r2 194 subeq r9, r9, #1 195 beq Lfind_highest_ipl 196 197 /* r9 = SPL level of highest priority interrupt */ 198 add r9, r9, #1 199 ldr r2, [r7, r9, lsl #2] 200 mvn r2, r2 201 orr r0, r0, r2 202 203 str r0, [r1] 204 205 ldr r0, [r4, #CI_CPL] 206 str r9, [r4, #CI_CPL] 207 stmfd sp!, {r0} 208 209 /* Update the IOMD irq masks */ 210 bl _C_LABEL(irq_setmasks) 211 212 mrs r0, cpsr /* Enable IRQ's */ 213 bic r0, r0, #I32_bit 214 msr cpsr_all, r0 215 216 /* 217 * take a copy of the IRQ request so that we can strip bits out of it 218 * note that we only use 24 bits with iomd2 chips 219 */ 220 ldr r7, Larm7500_ioc_found 221 ldr r7, [r7] /* get the flag */ 222 cmp r7, #0 223 movne r11, r8 /* ARM7500 -> copy all bits */ 224 biceq r11, r8, #0xff000000 /* !ARM7500 -> only use 24 bit */ 225 226 /* ffs routine to find first irq to service */ 227 /* standard trick to isolate bottom bit in a0 or 0 if a0 = 0 on entry */ 228 rsb r7, r11, #0 229 ands r10, r11, r7 230 231 /* 232 * now r10 has at most 1 set bit, call this X 233 * if X = 0, branch to exit code 234 */ 235 beq exitirq 236 irqloop: 237 ldr r6, Lirqhandlers 238 adr r7, Lirq_ffs_table 239 /* 240 * at this point: 241 * r6 = address of irq handlers table 242 * r7 = address of ffs table 243 * r8 = irq request 244 * r10 = bit of irq to be serviced 245 * r11 = bitmask of IRQ's to service 246 */ 247 /* find the set bit */ 248 orr r9, r10, r10, lsl #4 /* X * 0x11 */ 249 orr r9, r9, r9, lsl #6 /* X * 0x451 */ 250 rsb r9, r9, r9, lsl #16 /* X * 0x0450fbaf */ 251 /* fetch the bit number */ 252 ldrb r9, [r7, r9, lsr #26 ] 253 254 /* 255 * r9 = irq to service 256 */ 257 258 /* apologies for the dogs dinner of code here, but it's in an attempt 259 * to minimise stalling on SA's, hence lots of things happen here: 260 * - getting address of handler, if it doesn't exist we call 261 * stray_irqhandler this is assumed to be rare so we don't 262 * care about performance for it 263 * - statinfo is updated 264 * - unsetting of the irq bit in r11 265 * - irq stats (if enabled) also get put in the mix 266 */ 267 ldr r6, [r6, r9, lsl #2] /* Get address of first handler structure */ 268 269 teq r6, #0x00000000 /* Do we have a handler */ 270 moveq r0, r8 /* IRQ requests as arg 0 */ 271 adreq lr, nextirq /* return Address */ 272 beq _C_LABEL(stray_irqhandler) /* call special handler */ 273 274 /* stat info C */ 275 ldr r1, [r4, #(CI_CC_NINTR)] /* Stat info B */ 276 ldr r2, [r4, #(CI_CC_NINTR+4)] 277 #ifdef _ARMEL 278 adds r1, r1, #0x00000001 279 adc r2, r2, #0x00000000 280 #else 281 adds r2, r2, #0x00000001 282 adc r1, r1, #0x00000000 283 #endif 284 str r1, [r4, #(CI_CC_NINTR)] 285 str r2, [r4, #(CI_CC_NINTR+4)] 286 287 #ifdef IRQSTATS 288 ldr r2, Lintrcnt 289 ldr r3, [r6, #(IH_NUM)] 290 ldr r3, [r2, r3, lsl #2]! 291 #endif 292 bic r11, r11, r10 /* clear the IRQ bit */ 293 294 #ifdef IRQSTATS 295 add r3, r3, #0x00000001 296 str r3, [r2] 297 #endif /* IRQSTATS */ 298 299 irqchainloop: 300 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 301 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 302 addeq r0, sp, #8 /* ... stack frame [XXX needs care] */ 303 304 mov lr, pc /* return address */ 305 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 306 307 ldr r6, [r6, #(IH_NEXT)] /* fetch next handler */ 308 309 teq r0, #0x00000001 /* Was the irq serviced ? */ 310 311 /* if it was it'll just fall through this: */ 312 teqne r6, #0x00000000 313 bne irqchainloop 314 nextirq: 315 /* Check for next irq */ 316 rsb r7, r11, #0 317 ands r10, r11, r7 318 /* check if there are anymore irq's to service */ 319 bne irqloop 320 321 exitirq: 322 ldmfd sp!, {r2, r3} 323 ldr r0, Ldisabled_mask 324 str r2, [r4, #CI_CPL] 325 str r3, [r0] 326 327 bl _C_LABEL(irq_setmasks) 328 329 /* Kill IRQ's in preparation for exit */ 330 mrs r0, cpsr 331 orr r0, r0, #(I32_bit) 332 msr cpsr_all, r0 333 334 /* Decrement the nest count */ 335 ldr r0, [r4, #CI_INTR_DEPTH] 336 sub r0, r0, #1 337 str r0, [r4, #CI_INTR_DEPTH] 338 339 ldr r7, [sp, #TF_FILL] /* restore r7 */ 340 LOCK_CAS_CHECK 341 342 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 343 PULLFRAMEFROMSVCANDEXIT 344 345 /* NOT REACHED */ 346 b . - 8 347 348 Lcurrent_mask: 349 .word _C_LABEL(current_mask) /* irq's that are usable */ 350 351 ENTRY(irq_setmasks) 352 /* Disable interrupts */ 353 mrs r3, cpsr 354 orr r1, r3, #(I32_bit) 355 msr cpsr_all, r1 356 357 /* Calculate IOMD interrupt mask */ 358 ldr r1, Lcurrent_mask /* All the enabled interrupts */ 359 ldr r1, [r1] 360 ldr r0, Lspl_masks /* Block due to current spl level */ 361 ldr r2, Lcurrent_spl_level 362 ldr r2, [r2] 363 ldr r2, [r0, r2, lsl #2] 364 and r1, r1, r2 365 ldr r2, Ldisabled_mask /* Block due to active interrupts */ 366 ldr r2, [r2] 367 bic r1, r1, r2 368 369 ldr r0, Liomd_base 370 ldr r0, [r0] /* Point to the IOMD */ 371 strb r1, [r0, #(IOMD_IRQMSKA << 2)] /* Set IRQ mask A */ 372 mov r1, r1, lsr #8 373 strb r1, [r0, #(IOMD_IRQMSKB << 2)] /* Set IRQ mask B */ 374 mov r1, r1, lsr #8 375 376 ldr r2, Larm7500_ioc_found 377 ldr r2, [r2] 378 cmp r2, #0 379 beq skip_setting_extended_DMA_mask 380 381 /* only for ARM7500's */ 382 strb r1, [r0, #(IOMD_IRQMSKC << 2)] 383 mov r1, r1, lsr #8 384 and r2, r1, #0xef 385 strb r2, [r0, #(IOMD_IRQMSKD << 2)] 386 mov r1, r1, lsr #3 387 and r2, r1, #0x10 388 strb r2, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 389 b continue_setting_masks 390 391 skip_setting_extended_DMA_mask: 392 /* non ARM7500's */ 393 strb r1, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */ 394 395 continue_setting_masks: 396 397 /* Restore old cpsr and exit */ 398 msr cpsr_all, r3 399 mov pc, lr 400 401 Lintrcnt: 402 .word _C_LABEL(intrcnt) 403 404 405 Lirqhandlers: 406 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 407 408 #ifdef IRQSTATS 409 /* These symbols are used by vmstat */ 410 411 .section .rodata 412 413 .global _C_LABEL(_intrnames) 414 _C_LABEL(_intrnames): 415 .word _C_LABEL(intrnames) 416 417 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 418 _C_LABEL(intrnames): 419 .asciz "interrupt 0 " 420 .asciz "interrupt 1 " /* reserved0 */ 421 .asciz "interrupt 2 " 422 .asciz "interrupt 3 " 423 .asciz "interrupt 4 " 424 .asciz "interrupt 5 " 425 .asciz "interrupt 6 " 426 .asciz "interrupt 7 " /* reserved1 */ 427 .asciz "interrupt 8 " /* reserved2 */ 428 .asciz "interrupt 9 " 429 .asciz "interrupt 10 " 430 .asciz "interrupt 11 " 431 .asciz "interrupt 12 " 432 .asciz "interrupt 13 " 433 .asciz "interrupt 14 " 434 .asciz "interrupt 15 " 435 .asciz "dma channel 0" 436 .asciz "dma channel 1" 437 .asciz "dma channel 2" 438 .asciz "dma channel 3" 439 .asciz "interrupt 20 " 440 .asciz "interrupt 21 " 441 .asciz "reserved 3 " 442 .asciz "reserved 4 " 443 .asciz "exp card 0 " 444 .asciz "exp card 1 " 445 .asciz "exp card 2 " 446 .asciz "exp card 3 " 447 .asciz "exp card 4 " 448 .asciz "exp card 5 " 449 .asciz "exp card 6 " 450 .asciz "exp card 7 " 451 452 _C_LABEL(sintrnames): 453 .asciz "softclock " 454 .asciz "softnet " 455 .asciz "softserial " 456 .asciz "softintr 3 " 457 .asciz "softintr 4 " 458 .asciz "softintr 5 " 459 .asciz "softintr 6 " 460 .asciz "softintr 7 " 461 .asciz "softintr 8 " 462 .asciz "softintr 9 " 463 .asciz "softintr 10 " 464 .asciz "softintr 11 " 465 .asciz "softintr 12 " 466 .asciz "softintr 13 " 467 .asciz "softintr 14 " 468 .asciz "softintr 15 " 469 .asciz "softintr 16 " 470 .asciz "softintr 17 " 471 .asciz "softintr 18 " 472 .asciz "softintr 19 " 473 .asciz "softintr 20 " 474 .asciz "softintr 21 " 475 .asciz "softintr 22 " 476 .asciz "softintr 23 " 477 .asciz "softintr 24 " 478 .asciz "softintr 25 " 479 .asciz "softintr 26 " 480 .asciz "softintr 27 " 481 .asciz "softintr 28 " 482 .asciz "softintr 29 " 483 .asciz "softintr 30 " 484 .asciz "softintr 31 " 485 _C_LABEL(eintrnames): 486 487 .bss 488 .align 0 489 _C_LABEL(intrcnt): 490 .space 32*4 /* XXX Should be linked to number of interrupts */ 491 492 _C_LABEL(sintrcnt): 493 .space 32*4 /* XXX Should be linked to number of interrupts */ 494 _C_LABEL(eintrcnt): 495 496 #else /* IRQSTATS */ 497 /* Dummy entries to keep vmstat happy */ 498 499 .section .rodata 500 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 501 _C_LABEL(intrnames): 502 .long 0 503 _C_LABEL(eintrnames): 504 505 _C_LABEL(intrcnt): 506 .long 0 507 _C_LABEL(eintrcnt): 508 #endif /* IRQSTATS */ 509
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