mvsocreg.h revision 1.2.2.2
1 1.2.2.2 rmind /* $NetBSD: mvsocreg.h,v 1.2.2.2 2011/03/05 20:49:37 rmind Exp $ */ 2 1.2.2.2 rmind /* 3 1.2.2.2 rmind * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 1.2.2.2 rmind * All rights reserved. 5 1.2.2.2 rmind * 6 1.2.2.2 rmind * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 rmind * modification, are permitted provided that the following conditions 8 1.2.2.2 rmind * are met: 9 1.2.2.2 rmind * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 rmind * documentation and/or other materials provided with the distribution. 14 1.2.2.2 rmind * 15 1.2.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.2.2 rmind * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.2.2.2 rmind * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.2.2.2 rmind * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.2.2.2 rmind * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.2.2.2 rmind * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.2.2.2 rmind * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.2.2.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.2.2.2 rmind * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.2.2.2 rmind * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.2.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 26 1.2.2.2 rmind */ 27 1.2.2.2 rmind 28 1.2.2.2 rmind #ifndef _MVSOCREG_H_ 29 1.2.2.2 rmind #define _MVSOCREG_H_ 30 1.2.2.2 rmind 31 1.2.2.2 rmind #define MVSOC_UNITID_MASK 0xf 32 1.2.2.2 rmind #define MVSOC_UNITID_DDR 0x0 /* DDR registers */ 33 1.2.2.2 rmind #define MVSOC_UNITID_DEVBUS 0x1 /* Device Bus registers */ 34 1.2.2.2 rmind #define MVSOC_UNITID_MLMB 0x2 /* Mbus-L to Mbus Bridge reg */ 35 1.2.2.2 rmind #define MVSOC_UNITID_PEX 0x4 /* PCI Express Interface reg */ 36 1.2.2.2 rmind 37 1.2.2.2 rmind 38 1.2.2.2 rmind /* 39 1.2.2.2 rmind * Physical address of integrated peripherals 40 1.2.2.2 rmind */ 41 1.2.2.2 rmind 42 1.2.2.2 rmind #define UNITID2PHYS(uid) ((MVSOC_UNITID_ ## uid) << 16) 43 1.2.2.2 rmind 44 1.2.2.2 rmind /* 45 1.2.2.2 rmind * DDR SDRAM Controller Registers 46 1.2.2.2 rmind */ 47 1.2.2.2 rmind #define MVSOC_DDR_BASE (UNITID2PHYS(DDR)) /* 0x00000 */ 48 1.2.2.2 rmind 49 1.2.2.2 rmind /* DDR SDRAM Contriller Address Decode Registers */ 50 1.2.2.2 rmind #define MVSOC_DSC_BASE 0x01500 /* DDR SDRAM Ctrl Addr Reg */ 51 1.2.2.2 rmind #define MVSOC_DSC_NCS 4 52 1.2.2.2 rmind #define MVSOC_DSC_CSBAR(x) ((x) * 8) 53 1.2.2.2 rmind #define MVSOC_DSC_CSBAR_BASE_MASK 0xff000000 54 1.2.2.2 rmind #define MVSOC_DSC_CSSR(x) ((x) * 8 + 4) 55 1.2.2.2 rmind #define MVSOC_DSC_CSSR_WINEN 0x00000001 56 1.2.2.2 rmind #define MVSOC_DSC_CSSR_SIZE_MASK 0xff000000 57 1.2.2.2 rmind 58 1.2.2.2 rmind 59 1.2.2.2 rmind /* 60 1.2.2.2 rmind * Device Bus 61 1.2.2.2 rmind */ 62 1.2.2.2 rmind #define MVSOC_DEVBUS_BASE (UNITID2PHYS(DEVBUS)) /* 0x10000 */ 63 1.2.2.2 rmind 64 1.2.2.2 rmind /* 65 1.2.2.2 rmind * General Purpose Port Registers 66 1.2.2.2 rmind */ 67 1.2.2.2 rmind #define MVSOC_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100) 68 1.2.2.2 rmind 69 1.2.2.2 rmind /* 70 1.2.2.2 rmind * Two-Wire Serial Interface Registers 71 1.2.2.2 rmind */ 72 1.2.2.2 rmind #define MVSOC_TWSI_BASE (MVSOC_DEVBUS_BASE + 0x1000) 73 1.2.2.2 rmind 74 1.2.2.2 rmind /* 75 1.2.2.2 rmind * UART Interface Registers 76 1.2.2.2 rmind */ 77 1.2.2.2 rmind /* NS16550 compatible */ 78 1.2.2.2 rmind #define MVSOC_COM0_BASE (MVSOC_DEVBUS_BASE + 0x2000) 79 1.2.2.2 rmind #define MVSOC_COM1_BASE (MVSOC_DEVBUS_BASE + 0x2100) 80 1.2.2.2 rmind 81 1.2.2.2 rmind /* 82 1.2.2.2 rmind * Mbus-L to Mbus Bridge Registers 83 1.2.2.2 rmind */ 84 1.2.2.2 rmind #define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */ 85 1.2.2.2 rmind 86 1.2.2.2 rmind /* CPU Address Map Registers */ 87 1.2.2.2 rmind #define MVSOC_MLMB_WCR(w) (((w) << 4) + 0x0) 88 1.2.2.2 rmind #define MVSOC_MLMB_WCR_WINEN (1 << 0) 89 1.2.2.2 rmind #define MVSOC_MLMB_WCR_TARGET(t) (((t) & 0xf) << 4) 90 1.2.2.2 rmind #define MVSOC_MLMB_WCR_ATTR(a) (((a) & 0xff) << 8) 91 1.2.2.2 rmind #define MVSOC_MLMB_WCR_SIZE_MASK 0xffff0000 92 1.2.2.2 rmind #define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK) 93 1.2.2.2 rmind #define MVSOC_MLMB_WBR(w) (((w) << 4) + 0x4) 94 1.2.2.2 rmind #define MVSOC_MLMB_WBR_BASE_MASK 0xffff0000 95 1.2.2.2 rmind #define MVSOC_MLMB_WRLR(w) (((w) << 4) + 0x8) 96 1.2.2.2 rmind #define MVSOC_MLMB_WRLR_REMAP_MASK 0xffff0000 97 1.2.2.2 rmind #define MVSOC_MLMB_WRHR(w) (((w) << 4) + 0xc) 98 1.2.2.2 rmind #define MVSOC_MLMB_IRBAR 0x080 /* Internal regs Base Address */ 99 1.2.2.2 rmind #define MVSOC_MLMB_IRBAR_BASE_MASK 0xfff00000 100 1.2.2.2 rmind 101 1.2.2.2 rmind /* CPU Control and Status Registers */ 102 1.2.2.2 rmind #define MVSOC_MLMB_CPUCR 0x100 /* CPU Configuration Register */ 103 1.2.2.2 rmind #define MVSOC_MLMB_CPUCSR 0x104 /* CPU Control/Status Register*/ 104 1.2.2.2 rmind #define MVSOC_MLMB_RSTOUTNMASKR 0x108 /* RSTOUTn Mask Register */ 105 1.2.2.2 rmind #define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN (1 << 0) 106 1.2.2.2 rmind #define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN (1 << 1) 107 1.2.2.2 rmind #define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2) 108 1.2.2.2 rmind #define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */ 109 1.2.2.2 rmind #define MVSOC_MLMB_SSRR_SYSTEMSOFTRST (1 << 0) 110 1.2.2.2 rmind #define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/ 111 1.2.2.2 rmind #define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */ 112 1.2.2.2 rmind 113 1.2.2.2 rmind #define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */ 114 1.2.2.2 rmind 115 1.2.2.2 rmind #define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300) 116 1.2.2.2 rmind 117 1.2.2.2 rmind /* CPU Doorbell Registers */ 118 1.2.2.2 rmind #define MVSOC_MLMB_H2CDR 0x400 /* Host-to-CPU Doorbell */ 119 1.2.2.2 rmind #define MVSOC_MLMB_H2CDMR 0x404 /* Host-to-CPU Doorbell Mask */ 120 1.2.2.2 rmind #define MVSOC_MLMB_C2HDR 0x408 /* CPU-to-Host Doorbell */ 121 1.2.2.2 rmind #define MVSOC_MLMB_C2HDMR 0x40c /* CPU-to-Host Doorbell Mask */ 122 1.2.2.2 rmind 123 1.2.2.2 rmind /* Local to System Bridge Interrupt {Cause,Mask} Register bits */ 124 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_CPUSELFINT 0 125 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ 1 126 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ 2 127 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ 3 128 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_ACCESSERR 4 129 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_BIT64ERR 5 130 1.2.2.2 rmind 131 1.2.2.2 rmind #define MVSOC_MLMB_MLMBI_NIRQ 6 132 1.2.2.2 rmind 133 1.2.2.2 rmind /* 134 1.2.2.2 rmind * PCI-Express Interface Registers 135 1.2.2.2 rmind */ 136 1.2.2.2 rmind #define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */ 137 1.2.2.2 rmind 138 1.2.2.2 rmind #endif /* _MVSOCREG_H_ */ 139
Indexes created Tue Oct 28 12:10:06 GMT 2025