mvsoctmr.c revision 1.1.10.2
1 1.1.10.2 rmind /* $NetBSD: mvsoctmr.c,v 1.1.10.2 2011/03/05 20:49:37 rmind Exp $ */ 2 1.1.10.2 rmind /* 3 1.1.10.2 rmind * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 1.1.10.2 rmind * All rights reserved. 5 1.1.10.2 rmind * 6 1.1.10.2 rmind * Redistribution and use in source and binary forms, with or without 7 1.1.10.2 rmind * modification, are permitted provided that the following conditions 8 1.1.10.2 rmind * are met: 9 1.1.10.2 rmind * 1. Redistributions of source code must retain the above copyright 10 1.1.10.2 rmind * notice, this list of conditions and the following disclaimer. 11 1.1.10.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 12 1.1.10.2 rmind * notice, this list of conditions and the following disclaimer in the 13 1.1.10.2 rmind * documentation and/or other materials provided with the distribution. 14 1.1.10.2 rmind * 15 1.1.10.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.1.10.2 rmind * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.1.10.2 rmind * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.1.10.2 rmind * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.1.10.2 rmind * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.1.10.2 rmind * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.1.10.2 rmind * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1.10.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.1.10.2 rmind * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.1.10.2 rmind * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.1.10.2 rmind * POSSIBILITY OF SUCH DAMAGE. 26 1.1.10.2 rmind */ 27 1.1.10.2 rmind #include <sys/cdefs.h> 28 1.1.10.2 rmind __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.1.10.2 2011/03/05 20:49:37 rmind Exp $"); 29 1.1.10.2 rmind 30 1.1.10.2 rmind #include <sys/param.h> 31 1.1.10.2 rmind #include <sys/atomic.h> 32 1.1.10.2 rmind #include <sys/bus.h> 33 1.1.10.2 rmind #include <sys/device.h> 34 1.1.10.2 rmind #include <sys/errno.h> 35 1.1.10.2 rmind #include <sys/kernel.h> 36 1.1.10.2 rmind #include <sys/time.h> 37 1.1.10.2 rmind #include <sys/timetc.h> 38 1.1.10.2 rmind #include <sys/systm.h> 39 1.1.10.2 rmind 40 1.1.10.2 rmind #include <machine/intr.h> 41 1.1.10.2 rmind 42 1.1.10.2 rmind #include <arm/cpufunc.h> 43 1.1.10.2 rmind 44 1.1.10.2 rmind #include <arm/marvell/mvsocreg.h> 45 1.1.10.2 rmind #include <arm/marvell/mvsocvar.h> 46 1.1.10.2 rmind #include <arm/marvell/mvsoctmrreg.h> 47 1.1.10.2 rmind 48 1.1.10.2 rmind #include <dev/marvell/marvellvar.h> 49 1.1.10.2 rmind 50 1.1.10.2 rmind 51 1.1.10.2 rmind struct mvsoctmr_softc { 52 1.1.10.2 rmind device_t sc_dev; 53 1.1.10.2 rmind 54 1.1.10.2 rmind bus_space_tag_t sc_iot; 55 1.1.10.2 rmind bus_space_handle_t sc_ioh; 56 1.1.10.2 rmind }; 57 1.1.10.2 rmind 58 1.1.10.2 rmind 59 1.1.10.2 rmind static int mvsoctmr_match(device_t, struct cfdata *, void *); 60 1.1.10.2 rmind static void mvsoctmr_attach(device_t, device_t, void *); 61 1.1.10.2 rmind 62 1.1.10.2 rmind static int clockhandler(void *); 63 1.1.10.2 rmind static int statclockhandler(void *); 64 1.1.10.2 rmind 65 1.1.10.2 rmind static u_int mvsoctmr_get_timecount(struct timecounter *); 66 1.1.10.2 rmind 67 1.1.10.2 rmind static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int); 68 1.1.10.2 rmind 69 1.1.10.2 rmind #ifndef STATHZ 70 1.1.10.2 rmind #define STATHZ 64 71 1.1.10.2 rmind #endif 72 1.1.10.2 rmind 73 1.1.10.2 rmind static struct mvsoctmr_softc *mvsoctmr_sc; 74 1.1.10.2 rmind static uint32_t clock_ticks, statclock_ticks; 75 1.1.10.2 rmind static struct timecounter mvsoctmr_timecounter = { 76 1.1.10.2 rmind mvsoctmr_get_timecount, /* get_timecount */ 77 1.1.10.2 rmind 0, /* no poll_pps */ 78 1.1.10.2 rmind ~0u, /* counter_mask */ 79 1.1.10.2 rmind 0, /* frequency (set by cpu_initclocks()) */ 80 1.1.10.2 rmind "mvsoctmr", /* name */ 81 1.1.10.2 rmind 100, /* quality */ 82 1.1.10.2 rmind NULL, /* prev */ 83 1.1.10.2 rmind NULL, /* next */ 84 1.1.10.2 rmind }; 85 1.1.10.2 rmind static volatile uint32_t mvsoctmr_base; 86 1.1.10.2 rmind 87 1.1.10.2 rmind CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc), 88 1.1.10.2 rmind mvsoctmr_match, mvsoctmr_attach, NULL, NULL); 89 1.1.10.2 rmind 90 1.1.10.2 rmind 91 1.1.10.2 rmind /* ARGSUSED */ 92 1.1.10.2 rmind static int 93 1.1.10.2 rmind mvsoctmr_match(device_t parent, struct cfdata *match, void *aux) 94 1.1.10.2 rmind { 95 1.1.10.2 rmind struct marvell_attach_args *mva = aux; 96 1.1.10.2 rmind 97 1.1.10.2 rmind if (strcmp(mva->mva_name, match->cf_name) != 0) 98 1.1.10.2 rmind return 0; 99 1.1.10.2 rmind if (mva->mva_offset == MVA_OFFSET_DEFAULT) 100 1.1.10.2 rmind return 0; 101 1.1.10.2 rmind 102 1.1.10.2 rmind mva->mva_size = MVSOCTMR_SIZE; 103 1.1.10.2 rmind return 1; 104 1.1.10.2 rmind } 105 1.1.10.2 rmind 106 1.1.10.2 rmind /* ARGSUSED */ 107 1.1.10.2 rmind static void 108 1.1.10.2 rmind mvsoctmr_attach(device_t parent, device_t self, void *aux) 109 1.1.10.2 rmind { 110 1.1.10.2 rmind struct mvsoctmr_softc *sc = device_private(self); 111 1.1.10.2 rmind struct marvell_attach_args *mva = aux; 112 1.1.10.2 rmind 113 1.1.10.2 rmind aprint_naive("\n"); 114 1.1.10.2 rmind aprint_normal(": Marvell SoC Timer\n"); 115 1.1.10.2 rmind 116 1.1.10.2 rmind if (mvsoctmr_sc == NULL) 117 1.1.10.2 rmind mvsoctmr_sc = sc; 118 1.1.10.2 rmind 119 1.1.10.2 rmind sc->sc_dev = self; 120 1.1.10.2 rmind sc->sc_iot = mva->mva_iot; 121 1.1.10.2 rmind if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 122 1.1.10.2 rmind mva->mva_offset, mva->mva_size, &sc->sc_ioh)) 123 1.1.10.2 rmind panic("%s: Cannot map registers", device_xname(self)); 124 1.1.10.2 rmind } 125 1.1.10.2 rmind 126 1.1.10.2 rmind /* 127 1.1.10.2 rmind * clockhandler: 128 1.1.10.2 rmind * 129 1.1.10.2 rmind * Handle the hardclock interrupt. 130 1.1.10.2 rmind */ 131 1.1.10.2 rmind static int 132 1.1.10.2 rmind clockhandler(void *arg) 133 1.1.10.2 rmind { 134 1.1.10.2 rmind struct clockframe *frame = arg; 135 1.1.10.2 rmind 136 1.1.10.2 rmind atomic_add_32(&mvsoctmr_base, clock_ticks); 137 1.1.10.2 rmind 138 1.1.10.2 rmind hardclock(frame); 139 1.1.10.2 rmind 140 1.1.10.2 rmind return 1; 141 1.1.10.2 rmind } 142 1.1.10.2 rmind 143 1.1.10.2 rmind /* 144 1.1.10.2 rmind * statclockhandler: 145 1.1.10.2 rmind * 146 1.1.10.2 rmind * Handle the statclock interrupt. 147 1.1.10.2 rmind */ 148 1.1.10.2 rmind static int 149 1.1.10.2 rmind statclockhandler(void *arg) 150 1.1.10.2 rmind { 151 1.1.10.2 rmind struct clockframe *frame = arg; 152 1.1.10.2 rmind 153 1.1.10.2 rmind statclock(frame); 154 1.1.10.2 rmind 155 1.1.10.2 rmind return 1; 156 1.1.10.2 rmind } 157 1.1.10.2 rmind 158 1.1.10.2 rmind 159 1.1.10.2 rmind /* 160 1.1.10.2 rmind * setstatclockrate: 161 1.1.10.2 rmind * 162 1.1.10.2 rmind * Set the rate of the statistics clock. 163 1.1.10.2 rmind * 164 1.1.10.2 rmind * We assume that hz is either stathz or profhz, and that neither 165 1.1.10.2 rmind * will change after being set by cpu_initclocks(). We could 166 1.1.10.2 rmind * recalculate the intervals here, but that would be a pain. 167 1.1.10.2 rmind */ 168 1.1.10.2 rmind /* ARGSUSED */ 169 1.1.10.2 rmind void 170 1.1.10.2 rmind setstatclockrate(int newhz) 171 1.1.10.2 rmind { 172 1.1.10.2 rmind struct mvsoctmr_softc *sc = mvsoctmr_sc; 173 1.1.10.2 rmind const int en = 1, autoen = 1; 174 1.1.10.2 rmind 175 1.1.10.2 rmind statclock_ticks = mvTclk / newhz; 176 1.1.10.2 rmind 177 1.1.10.2 rmind mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, statclock_ticks, en, autoen); 178 1.1.10.2 rmind } 179 1.1.10.2 rmind 180 1.1.10.2 rmind /* 181 1.1.10.2 rmind * cpu_initclocks: 182 1.1.10.2 rmind * 183 1.1.10.2 rmind * Initialize the clock and get them going. 184 1.1.10.2 rmind */ 185 1.1.10.2 rmind void 186 1.1.10.2 rmind cpu_initclocks() 187 1.1.10.2 rmind { 188 1.1.10.2 rmind struct mvsoctmr_softc *sc; 189 1.1.10.2 rmind void *clock_ih; 190 1.1.10.2 rmind const int en = 1, autoen = 1; 191 1.1.10.2 rmind 192 1.1.10.2 rmind sc = mvsoctmr_sc; 193 1.1.10.2 rmind if (sc == NULL) 194 1.1.10.2 rmind panic("cpu_initclocks: mvsoctmr not found"); 195 1.1.10.2 rmind 196 1.1.10.2 rmind stathz = profhz = STATHZ; 197 1.1.10.2 rmind mvsoctmr_timecounter.tc_frequency = mvTclk; 198 1.1.10.2 rmind clock_ticks = mvTclk / hz; 199 1.1.10.2 rmind 200 1.1.10.2 rmind mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, clock_ticks, en, autoen); 201 1.1.10.2 rmind 202 1.1.10.2 rmind clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, 203 1.1.10.2 rmind IPL_CLOCK, clockhandler, NULL); 204 1.1.10.2 rmind if (clock_ih == NULL) 205 1.1.10.2 rmind panic("cpu_initclocks: unable to register timer interrupt"); 206 1.1.10.2 rmind 207 1.1.10.2 rmind if (stathz) { 208 1.1.10.2 rmind setstatclockrate(stathz); 209 1.1.10.2 rmind clock_ih = mvsoc_bridge_intr_establish( 210 1.1.10.2 rmind MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ, IPL_HIGH, 211 1.1.10.2 rmind statclockhandler, NULL); 212 1.1.10.2 rmind if (clock_ih == NULL) 213 1.1.10.2 rmind panic("cpu_initclocks:" 214 1.1.10.2 rmind " unable to register statclock timer interrupt"); 215 1.1.10.2 rmind } 216 1.1.10.2 rmind 217 1.1.10.2 rmind tc_init(&mvsoctmr_timecounter); 218 1.1.10.2 rmind } 219 1.1.10.2 rmind 220 1.1.10.2 rmind void 221 1.1.10.2 rmind delay(unsigned int n) 222 1.1.10.2 rmind { 223 1.1.10.2 rmind struct mvsoctmr_softc *sc; 224 1.1.10.2 rmind unsigned int cur_tick, initial_tick; 225 1.1.10.2 rmind int remaining; 226 1.1.10.2 rmind 227 1.1.10.2 rmind sc = mvsoctmr_sc; 228 1.1.10.2 rmind #ifdef DEBUG 229 1.1.10.2 rmind if (sc == NULL) { 230 1.1.10.2 rmind printf("%s: called before start mvsoctmr\n", __func__); 231 1.1.10.2 rmind return; 232 1.1.10.2 rmind } 233 1.1.10.2 rmind #endif 234 1.1.10.2 rmind 235 1.1.10.2 rmind /* 236 1.1.10.2 rmind * Read the counter first, so that the rest of the setup overhead is 237 1.1.10.2 rmind * counted. 238 1.1.10.2 rmind */ 239 1.1.10.2 rmind initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 240 1.1.10.2 rmind MVSOCTMR_TIMER(MVSOCTMR_TIMER0)); 241 1.1.10.2 rmind 242 1.1.10.2 rmind if (n <= UINT_MAX / mvTclk) { 243 1.1.10.2 rmind /* 244 1.1.10.2 rmind * For unsigned arithmetic, division can be replaced with 245 1.1.10.2 rmind * multiplication with the inverse and a shift. 246 1.1.10.2 rmind */ 247 1.1.10.2 rmind remaining = n * mvTclk / 1000000; 248 1.1.10.2 rmind } else { 249 1.1.10.2 rmind /* 250 1.1.10.2 rmind * This is a very long delay. 251 1.1.10.2 rmind * Being slow here doesn't matter. 252 1.1.10.2 rmind */ 253 1.1.10.2 rmind remaining = (unsigned long long) n * mvTclk / 1000000; 254 1.1.10.2 rmind } 255 1.1.10.2 rmind 256 1.1.10.2 rmind while (remaining > 0) { 257 1.1.10.2 rmind cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 258 1.1.10.2 rmind MVSOCTMR_TIMER(MVSOCTMR_TIMER0)); 259 1.1.10.2 rmind if (cur_tick > initial_tick) 260 1.1.10.2 rmind remaining -= clock_ticks - cur_tick + initial_tick; 261 1.1.10.2 rmind else 262 1.1.10.2 rmind remaining -= (initial_tick - cur_tick); 263 1.1.10.2 rmind initial_tick = cur_tick; 264 1.1.10.2 rmind } 265 1.1.10.2 rmind } 266 1.1.10.2 rmind 267 1.1.10.2 rmind static u_int 268 1.1.10.2 rmind mvsoctmr_get_timecount(struct timecounter *tc) 269 1.1.10.2 rmind { 270 1.1.10.2 rmind struct mvsoctmr_softc *sc = mvsoctmr_sc; 271 1.1.10.2 rmind uint32_t counter, base; 272 1.1.10.2 rmind u_int intrstat; 273 1.1.10.2 rmind 274 1.1.10.2 rmind intrstat = disable_interrupts(I32_bit); 275 1.1.10.2 rmind base = mvsoctmr_base; 276 1.1.10.2 rmind counter = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 277 1.1.10.2 rmind MVSOCTMR_TIMER(MVSOCTMR_TIMER0)); 278 1.1.10.2 rmind restore_interrupts(intrstat); 279 1.1.10.2 rmind 280 1.1.10.2 rmind return base - counter; 281 1.1.10.2 rmind } 282 1.1.10.2 rmind 283 1.1.10.2 rmind 284 1.1.10.2 rmind static void 285 1.1.10.2 rmind mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en, 286 1.1.10.2 rmind int autoen) 287 1.1.10.2 rmind { 288 1.1.10.2 rmind uint32_t ctrl; 289 1.1.10.2 rmind 290 1.1.10.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), 291 1.1.10.2 rmind ticks); 292 1.1.10.2 rmind 293 1.1.10.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks); 294 1.1.10.2 rmind 295 1.1.10.2 rmind ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR); 296 1.1.10.2 rmind if (en) 297 1.1.10.2 rmind ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num); 298 1.1.10.2 rmind else 299 1.1.10.2 rmind ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num); 300 1.1.10.2 rmind if (autoen) 301 1.1.10.2 rmind ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num); 302 1.1.10.2 rmind else 303 1.1.10.2 rmind ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num); 304 1.1.10.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl); 305 1.1.10.2 rmind } 306
Indexes created Tue Sep 30 07:10:03 GMT 2025