| History log of /src/sys/arch/arm/marvell/mvsoctmr.c |
| Revision | | Date | Author | Comments |
| 1.15 |
| 29-May-2020 |
rin | For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.
|
| 1.14 |
| 07-Jan-2017 |
kiyohara | Change to a tab from white-spaces.
|
| 1.13 |
| 15-Mar-2014 |
kiyohara | branches: 1.13.6; 1.13.10;
Support Armada 370. tested on MiraBox.
|
| 1.12 |
| 26-Feb-2014 |
martin | Initialize mvsoctmr_freq earlier (in mvsoctmr_attach) to avoid division
by zero in calculation of the watchdog parameters.
|
| 1.11 |
| 17-Feb-2014 |
kiyohara | Remove TMR_FLAGS_ARMADAXP and Add flags NOBRIDGE, 25MHZ, SYSCLK.
- NOBRIDGE does not go via a bridge.
- 25MHZ is always counted with the cycle of 25 MHz.
- SYSCLK is counted with the cycle of sysClk. This is used in a few days
for Armada 370.
And please use not mvTclk but variable mvsoctmr_freq for calculation of a clock.
(e.g. in delay())
|
| 1.10 |
| 14-Oct-2013 |
kiyohara | Remove some #ifdef ARMADAXP. We can enable simultaneously both ARMADAXP and
other SoC options.
|
| 1.9 |
| 01-May-2013 |
rkujawa | branches: 1.9.4;
Add support for timers on Armada XP.
Obtained from Marvell, Semihalf.
|
| 1.8 |
| 22-Jul-2012 |
jakllsch | branches: 1.8.2;
Actually, the WDT-expired bit in the ICR needs to be cleared before enabling
watchdog reset.
|
| 1.7 |
| 22-Jul-2012 |
jakllsch | The maximum watchdog period is dependant on mvTclk; calculate at runtime.
This gets the maximum period up to 25 seconds at 166⅔MHz mvTclk.
|
| 1.6 |
| 22-Jul-2012 |
jakllsch | Remove duplicate global variable.
|
| 1.5 |
| 22-Jul-2012 |
jakllsch | When disabling watchdog timer, do not set the counter to 0.
Having the watchdog counter at 0 and having WDRstOutEn set to 1 causes
immediate watchdog reset on my 88F5182 A2.
|
| 1.4 |
| 19-Jun-2012 |
hans | Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.
|
| 1.3 |
| 12-Feb-2012 |
matt | branches: 1.3.2;
Change old-style function defintions to C89 prototypes.
Approved by releng.
|
| 1.2 |
| 09-Jun-2011 |
jakllsch | branches: 1.2.2; 1.2.6;
Rework mvsoctmr(4), improving timekeeping accuracy
Inconveniently the Marvell hardware only counts down.
We need to reverse this for timecounter(9), and we need
to do it in a very lightweight way.
- use Timer0 for the clock interrupt
- use Timer1 for timecounter(9) and delay(9)
- drop statclock due to lack of timers (does anyone actually use this?)
|
| 1.1 |
| 03-Oct-2010 |
kiyohara | branches: 1.1.2; 1.1.4; 1.1.10; 1.1.12;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
|
| 1.1.12.1 |
| 23-Jun-2011 |
cherry | Catchup with rmind-uvmplock merge.
|
| 1.1.10.3 |
| 12-Jun-2011 |
rmind | sync with head
|
| 1.1.10.2 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.1.10.1 |
| 03-Oct-2010 |
rmind | file mvsoctmr.c was added on branch rmind-uvmplock on 2011-03-05 20:49:37 +0000
|
| 1.1.4.2 |
| 22-Oct-2010 |
uebayasi | Sync with HEAD (-D20101022).
|
| 1.1.4.1 |
| 03-Oct-2010 |
uebayasi | file mvsoctmr.c was added on branch uebayasi-xip on 2010-10-22 09:23:12 +0000
|
| 1.1.2.2 |
| 09-Oct-2010 |
yamt | sync with head
|
| 1.1.2.1 |
| 03-Oct-2010 |
yamt | file mvsoctmr.c was added on branch yamt-nfs-mp on 2010-10-09 03:31:40 +0000
|
| 1.2.6.1 |
| 18-Feb-2012 |
mrg | merge to -current.
|
| 1.2.2.3 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.2.2.2 |
| 30-Oct-2012 |
yamt | sync with head
|
| 1.2.2.1 |
| 17-Apr-2012 |
yamt | sync with head
|
| 1.3.2.1 |
| 13-Jan-2013 |
bouyer | Pull up following revision(s) (requested by riz in ticket #770):
sys/arch/arm/marvell/files.marvell: revision 1.5
sys/arch/arm/marvell/mvsoctmr.c: revision 1.4
sys/arch/arm/marvell/mvsoctmr.c: revision 1.5
sys/arch/arm/marvell/mvsoctmr.c: revision 1.6
sys/arch/arm/marvell/mvsoctmr.c: revision 1.7
Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.
When disabling watchdog timer, do not set the counter to 0.
Having the watchdog counter at 0 and having WDRstOutEn set to 1 causes
immediate watchdog reset on my 88F5182 A2.
Remove duplicate global variable.
The maximum watchdog period is dependant on mvTclk; calculate at runtime.
This gets the maximum period up to 25 seconds at 166⅔MHz mvTclk.
|
| 1.8.2.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.8.2.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.8.2.1 |
| 23-Jun-2013 |
tls | resync from head
|
| 1.9.4.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.13.10.1 |
| 20-Mar-2017 |
pgoyette | Sync with HEAD
|
| 1.13.6.1 |
| 05-Feb-2017 |
skrll | Sync with HEAD
|
