mvsoctmr.c revision 1.11
1 /* $NetBSD: mvsoctmr.c,v 1.11 2014/02/17 05:25:32 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.11 2014/02/17 05:25:32 kiyohara Exp $"); 29 30 #include "opt_ddb.h" 31 #include "opt_mvsoc.h" 32 33 #include <sys/param.h> 34 #include <sys/atomic.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/kernel.h> 39 #include <sys/time.h> 40 #include <sys/timetc.h> 41 #include <sys/systm.h> 42 #include <sys/wdog.h> 43 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/marvell/mvsocreg.h> 49 #include <arm/marvell/mvsocvar.h> 50 #include <arm/marvell/mvsoctmrreg.h> 51 52 #include <dev/marvell/marvellreg.h> 53 #include <dev/marvell/marvellvar.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 #ifdef DDB 58 #include <machine/db_machdep.h> 59 #include <ddb/db_extern.h> 60 #endif 61 62 63 struct mvsoctmr_softc { 64 device_t sc_dev; 65 66 struct sysmon_wdog sc_wdog; 67 uint32_t sc_wdog_period; 68 uint32_t sc_wdog_armed; 69 70 bus_space_tag_t sc_iot; 71 bus_space_handle_t sc_ioh; 72 int sc_irq; 73 74 #define TMR_FLAGS_NOBRIDGE (1 << 0) 75 #define TMR_FLAGS_25MHZ (1 << 1) 76 #define TMR_FLAGS_SYSCLK (1 << 2) 77 int sc_flags; 78 }; 79 80 81 static int mvsoctmr_match(device_t, struct cfdata *, void *); 82 static void mvsoctmr_attach(device_t, device_t, void *); 83 84 static int clockhandler(void *); 85 86 static u_int mvsoctmr_get_timecount(struct timecounter *); 87 88 static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int); 89 90 static int mvsoctmr_wdog_tickle(struct sysmon_wdog *); 91 static int mvsoctmr_wdog_setmode(struct sysmon_wdog *); 92 93 #ifdef DDB 94 static void mvsoctmr_wdog_ddb_trap(int); 95 #endif 96 97 static int mvsoctmr_freq; 98 99 #define MVSOC_WDOG_MAX_PERIOD (0xffffffff / mvsoctmr_freq) 100 101 static struct mvsoctmr_softc *mvsoctmr_sc; 102 static struct timecounter mvsoctmr_timecounter = { 103 mvsoctmr_get_timecount, /* get_timecount */ 104 0, /* no poll_pps */ 105 ~0u, /* counter_mask */ 106 0, /* frequency (set by cpu_initclocks()) */ 107 "mvsoctmr", /* name */ 108 100, /* quality */ 109 NULL, /* prev */ 110 NULL, /* next */ 111 }; 112 113 CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc), 114 mvsoctmr_match, mvsoctmr_attach, NULL, NULL); 115 116 117 /* ARGSUSED */ 118 static int 119 mvsoctmr_match(device_t parent, struct cfdata *match, void *aux) 120 { 121 struct marvell_attach_args *mva = aux; 122 123 if (strcmp(mva->mva_name, match->cf_name) != 0) 124 return 0; 125 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 126 mva->mva_irq == MVA_IRQ_DEFAULT) 127 return 0; 128 129 mva->mva_size = MVSOCTMR_SIZE; 130 return 1; 131 } 132 133 /* ARGSUSED */ 134 static void 135 mvsoctmr_attach(device_t parent, device_t self, void *aux) 136 { 137 struct mvsoctmr_softc *sc = device_private(self); 138 struct marvell_attach_args *mva = aux; 139 uint32_t rstoutn; 140 141 aprint_naive("\n"); 142 aprint_normal(": Marvell SoC Timer\n"); 143 144 if (mvsoctmr_sc == NULL) 145 mvsoctmr_sc = sc; 146 147 sc->sc_dev = self; 148 sc->sc_iot = mva->mva_iot; 149 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 150 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) 151 panic("%s: Cannot map registers", device_xname(self)); 152 sc->sc_irq = mva->mva_irq; 153 154 switch (mva->mva_model) { 155 case MARVELL_ARMADAXP_MV78130: 156 case MARVELL_ARMADAXP_MV78160: 157 case MARVELL_ARMADAXP_MV78230: 158 case MARVELL_ARMADAXP_MV78260: 159 case MARVELL_ARMADAXP_MV78460: 160 sc->sc_flags = TMR_FLAGS_25MHZ | TMR_FLAGS_NOBRIDGE; 161 break; 162 #if 0 163 case MARVELL_ARMADA370_MV6707: 164 case MARVELL_ARMADA370_MV6710: 165 case MARVELL_ARMADA370_MV6W11: 166 sc->sc_flags = TMR_FLAGS_NOBRIDGE | TMR_FLAGS_SYSCLK; 167 break; 168 #endif 169 } 170 171 mvsoctmr_timecounter.tc_name = device_xname(self); 172 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1); 173 174 /* 175 * stop watchdog timer, enable watchdog timer resets 176 */ 177 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 178 write_mlmbreg(MVSOC_MLMB_MLMBICR, 179 ~(1<<MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ)); 180 rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR); 181 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 182 rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN); 183 184 #ifdef DDB 185 db_trap_callback = mvsoctmr_wdog_ddb_trap; 186 #endif 187 188 sc->sc_wdog.smw_name = device_xname(self); 189 sc->sc_wdog.smw_cookie = sc; 190 sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode; 191 sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle; 192 sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD; 193 194 if (sysmon_wdog_register(&sc->sc_wdog) != 0) 195 aprint_error_dev(self, 196 "unable to register watchdog with sysmon\n"); 197 } 198 199 /* 200 * clockhandler: 201 * 202 * Handle the hardclock interrupt. 203 */ 204 static int 205 clockhandler(void *arg) 206 { 207 struct clockframe *frame = arg; 208 209 #if defined(ARMADAXP) 210 KASSERT(mvsoctmr_sc != NULL); 211 212 if (mvsoctmr_sc->sc_flags & TMR_FLAGS_NOBRIDGE) 213 /* Acknowledge all timers-related interrupts */ 214 bus_space_write_4(mvsoctmr_sc->sc_iot, mvsoctmr_sc->sc_ioh, 215 MVSOCTMR_TESR, 0x0); 216 #endif 217 218 hardclock(frame); 219 220 return 1; 221 } 222 223 /* 224 * setstatclockrate: 225 * 226 * Set the rate of the statistics clock. 227 */ 228 /* ARGSUSED */ 229 void 230 setstatclockrate(int newhz) 231 { 232 } 233 234 /* 235 * cpu_initclocks: 236 * 237 * Initialize the clock and get them going. 238 */ 239 void 240 cpu_initclocks(void) 241 { 242 struct mvsoctmr_softc *sc; 243 void *clock_ih; 244 const int en = 1, autoen = 1; 245 uint32_t timer0_tval; 246 247 sc = mvsoctmr_sc; 248 if (sc == NULL) 249 panic("cpu_initclocks: mvsoctmr not found"); 250 251 if (sc->sc_flags & TMR_FLAGS_25MHZ) 252 /* We set global timer and counter to 25 MHz mode */ 253 mvsoctmr_freq = 25000000; 254 else if (sc->sc_flags & TMR_FLAGS_SYSCLK) 255 mvsoctmr_freq = mvSysclk; 256 else 257 mvsoctmr_freq = mvTclk; 258 259 mvsoctmr_timecounter.tc_priv = sc; 260 mvsoctmr_timecounter.tc_frequency = mvsoctmr_freq; 261 262 timer0_tval = (mvsoctmr_freq * 2) / (u_long) hz; 263 timer0_tval = (timer0_tval / 2) + (timer0_tval & 1); 264 265 mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen); 266 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen); 267 268 if (sc->sc_flags & TMR_FLAGS_NOBRIDGE) { 269 /* 270 * Establishing timer interrupts is slightly different for 271 * Armada XP than for other supported SoCs from Marvell. 272 * Timer interrupt is no different from any other interrupt 273 * in Armada XP, so we use generic marvell_intr_establish(). 274 */ 275 clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK, 276 clockhandler, NULL); 277 } else 278 clock_ih = mvsoc_bridge_intr_establish( 279 MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, IPL_CLOCK, clockhandler, 280 NULL); 281 if (clock_ih == NULL) 282 panic("cpu_initclocks: unable to register timer interrupt"); 283 284 tc_init(&mvsoctmr_timecounter); 285 } 286 287 void 288 delay(unsigned int n) 289 { 290 struct mvsoctmr_softc *sc; 291 unsigned int cur_tick, initial_tick; 292 int remaining; 293 294 sc = mvsoctmr_sc; 295 #ifdef DEBUG 296 if (sc == NULL) { 297 printf("%s: called before start mvsoctmr\n", __func__); 298 return; 299 } 300 #endif 301 302 /* 303 * Read the counter first, so that the rest of the setup overhead is 304 * counted. 305 */ 306 initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 307 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 308 309 if (n <= UINT_MAX / mvsoctmr_freq) { 310 /* 311 * For unsigned arithmetic, division can be replaced with 312 * multiplication with the inverse and a shift. 313 */ 314 remaining = n * mvsoctmr_freq / 1000000; 315 } else { 316 /* 317 * This is a very long delay. 318 * Being slow here doesn't matter. 319 */ 320 remaining = (unsigned long long) n * mvsoctmr_freq / 1000000; 321 } 322 323 while (remaining > 0) { 324 cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 325 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 326 if (cur_tick > initial_tick) 327 remaining -= 0xffffffff - cur_tick + initial_tick; 328 else 329 remaining -= (initial_tick - cur_tick); 330 initial_tick = cur_tick; 331 } 332 } 333 334 static u_int 335 mvsoctmr_get_timecount(struct timecounter *tc) 336 { 337 struct mvsoctmr_softc *sc = tc->tc_priv; 338 339 return 0xffffffff - bus_space_read_4(sc->sc_iot, sc->sc_ioh, 340 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 341 } 342 343 static void 344 mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en, 345 int autoen) 346 { 347 uint32_t ctrl; 348 349 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), ticks); 350 351 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks); 352 353 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR); 354 if (en) 355 ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num); 356 else 357 ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num); 358 if (autoen) 359 ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num); 360 else 361 ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num); 362 if (sc->sc_flags & TMR_FLAGS_25MHZ) 363 /* Set timer and counter to 25MHz mode */ 364 ctrl |= MVSOCTMR_CTCR_25MHZEN(num); 365 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl); 366 } 367 368 static int 369 mvsoctmr_wdog_setmode(struct sysmon_wdog *smw) 370 { 371 struct mvsoctmr_softc *sc = smw->smw_cookie; 372 373 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 374 sc->sc_wdog_armed = 0; 375 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 376 } else { 377 sc->sc_wdog_armed = 1; 378 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 379 smw->smw_period = MVSOC_WDOG_MAX_PERIOD; 380 else if (smw->smw_period > MVSOC_WDOG_MAX_PERIOD || 381 smw->smw_period <= 0) 382 return (EOPNOTSUPP); 383 sc->sc_wdog_period = smw->smw_period * mvsoctmr_freq; 384 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 385 } 386 387 return (0); 388 } 389 390 static int 391 mvsoctmr_wdog_tickle(struct sysmon_wdog *smw) 392 { 393 struct mvsoctmr_softc *sc = smw->smw_cookie; 394 395 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 396 397 return (0); 398 } 399 400 #ifdef DDB 401 static void 402 mvsoctmr_wdog_ddb_trap(int enter) 403 { 404 struct mvsoctmr_softc *sc = mvsoctmr_sc; 405 406 if (sc == NULL) 407 return; 408 409 if (sc->sc_wdog_armed) { 410 if (enter) 411 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 412 else 413 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 414 sc->sc_wdog_period, 1, 0); 415 } 416 } 417 #endif 418
Indexes created Tue Sep 30 06:09:59 GMT 2025