mvsoctmr.c revision 1.2.2.2
1 /* $NetBSD: mvsoctmr.c,v 1.2.2.2 2012/10/30 17:19:06 yamt Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.2.2.2 2012/10/30 17:19:06 yamt Exp $"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/atomic.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/errno.h> 37 #include <sys/kernel.h> 38 #include <sys/time.h> 39 #include <sys/timetc.h> 40 #include <sys/systm.h> 41 #include <sys/wdog.h> 42 43 #include <machine/intr.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <arm/marvell/mvsocreg.h> 48 #include <arm/marvell/mvsocvar.h> 49 #include <arm/marvell/mvsoctmrreg.h> 50 51 #include <dev/marvell/marvellvar.h> 52 53 #include <dev/sysmon/sysmonvar.h> 54 55 #ifdef DDB 56 #include <machine/db_machdep.h> 57 #include <ddb/db_extern.h> 58 #endif 59 60 61 struct mvsoctmr_softc { 62 device_t sc_dev; 63 64 struct sysmon_wdog sc_wdog; 65 uint32_t sc_wdog_period; 66 uint32_t sc_wdog_armed; 67 68 bus_space_tag_t sc_iot; 69 bus_space_handle_t sc_ioh; 70 }; 71 72 73 static int mvsoctmr_match(device_t, struct cfdata *, void *); 74 static void mvsoctmr_attach(device_t, device_t, void *); 75 76 static int clockhandler(void *); 77 78 static u_int mvsoctmr_get_timecount(struct timecounter *); 79 80 static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int); 81 82 static int mvsoctmr_wdog_tickle(struct sysmon_wdog *); 83 static int mvsoctmr_wdog_setmode(struct sysmon_wdog *); 84 85 #ifdef DDB 86 static void mvsoctmr_wdog_ddb_trap(int); 87 #endif 88 89 #define MVSOC_WDOG_MAX_PERIOD (0xffffffff / mvTclk) 90 91 static struct mvsoctmr_softc *mvsoctmr_sc; 92 static struct timecounter mvsoctmr_timecounter = { 93 mvsoctmr_get_timecount, /* get_timecount */ 94 0, /* no poll_pps */ 95 ~0u, /* counter_mask */ 96 0, /* frequency (set by cpu_initclocks()) */ 97 "mvsoctmr", /* name */ 98 100, /* quality */ 99 NULL, /* prev */ 100 NULL, /* next */ 101 }; 102 103 CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc), 104 mvsoctmr_match, mvsoctmr_attach, NULL, NULL); 105 106 107 /* ARGSUSED */ 108 static int 109 mvsoctmr_match(device_t parent, struct cfdata *match, void *aux) 110 { 111 struct marvell_attach_args *mva = aux; 112 113 if (strcmp(mva->mva_name, match->cf_name) != 0) 114 return 0; 115 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 116 return 0; 117 118 mva->mva_size = MVSOCTMR_SIZE; 119 return 1; 120 } 121 122 /* ARGSUSED */ 123 static void 124 mvsoctmr_attach(device_t parent, device_t self, void *aux) 125 { 126 struct mvsoctmr_softc *sc = device_private(self); 127 struct marvell_attach_args *mva = aux; 128 uint32_t rstoutn; 129 130 aprint_naive("\n"); 131 aprint_normal(": Marvell SoC Timer\n"); 132 133 if (mvsoctmr_sc == NULL) 134 mvsoctmr_sc = sc; 135 136 sc->sc_dev = self; 137 sc->sc_iot = mva->mva_iot; 138 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 139 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) 140 panic("%s: Cannot map registers", device_xname(self)); 141 142 mvsoctmr_timecounter.tc_name = device_xname(self); 143 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1); 144 145 /* 146 * stop watchdog timer, enable watchdog timer resets 147 */ 148 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 149 write_mlmbreg(MVSOC_MLMB_MLMBICR, 150 ~(1<<MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ)); 151 rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR); 152 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 153 rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN); 154 155 #ifdef DDB 156 db_trap_callback = mvsoctmr_wdog_ddb_trap; 157 #endif 158 159 sc->sc_wdog.smw_name = device_xname(self); 160 sc->sc_wdog.smw_cookie = sc; 161 sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode; 162 sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle; 163 sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD; 164 165 if (sysmon_wdog_register(&sc->sc_wdog) != 0) 166 aprint_error_dev(self, 167 "unable to register watchdog with sysmon\n"); 168 } 169 170 /* 171 * clockhandler: 172 * 173 * Handle the hardclock interrupt. 174 */ 175 static int 176 clockhandler(void *arg) 177 { 178 struct clockframe *frame = arg; 179 180 hardclock(frame); 181 182 return 1; 183 } 184 185 /* 186 * setstatclockrate: 187 * 188 * Set the rate of the statistics clock. 189 */ 190 /* ARGSUSED */ 191 void 192 setstatclockrate(int newhz) 193 { 194 } 195 196 /* 197 * cpu_initclocks: 198 * 199 * Initialize the clock and get them going. 200 */ 201 void 202 cpu_initclocks(void) 203 { 204 struct mvsoctmr_softc *sc; 205 void *clock_ih; 206 const int en = 1, autoen = 1; 207 uint32_t timer0_tval; 208 209 sc = mvsoctmr_sc; 210 if (sc == NULL) 211 panic("cpu_initclocks: mvsoctmr not found"); 212 213 mvsoctmr_timecounter.tc_priv = sc; 214 mvsoctmr_timecounter.tc_frequency = mvTclk; 215 216 timer0_tval = (mvTclk * 2) / (u_long) hz; 217 timer0_tval = (timer0_tval / 2) + (timer0_tval & 1); 218 219 mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen); 220 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen); 221 222 clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, 223 IPL_CLOCK, clockhandler, NULL); 224 if (clock_ih == NULL) 225 panic("cpu_initclocks: unable to register timer interrupt"); 226 227 tc_init(&mvsoctmr_timecounter); 228 } 229 230 void 231 delay(unsigned int n) 232 { 233 struct mvsoctmr_softc *sc; 234 unsigned int cur_tick, initial_tick; 235 int remaining; 236 237 sc = mvsoctmr_sc; 238 #ifdef DEBUG 239 if (sc == NULL) { 240 printf("%s: called before start mvsoctmr\n", __func__); 241 return; 242 } 243 #endif 244 245 /* 246 * Read the counter first, so that the rest of the setup overhead is 247 * counted. 248 */ 249 initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 250 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 251 252 if (n <= UINT_MAX / mvTclk) { 253 /* 254 * For unsigned arithmetic, division can be replaced with 255 * multiplication with the inverse and a shift. 256 */ 257 remaining = n * mvTclk / 1000000; 258 } else { 259 /* 260 * This is a very long delay. 261 * Being slow here doesn't matter. 262 */ 263 remaining = (unsigned long long) n * mvTclk / 1000000; 264 } 265 266 while (remaining > 0) { 267 cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 268 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 269 if (cur_tick > initial_tick) 270 remaining -= 0xffffffff - cur_tick + initial_tick; 271 else 272 remaining -= (initial_tick - cur_tick); 273 initial_tick = cur_tick; 274 } 275 } 276 277 static u_int 278 mvsoctmr_get_timecount(struct timecounter *tc) 279 { 280 struct mvsoctmr_softc *sc = tc->tc_priv; 281 282 return 0xffffffff - bus_space_read_4(sc->sc_iot, sc->sc_ioh, 283 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 284 } 285 286 static void 287 mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en, 288 int autoen) 289 { 290 uint32_t ctrl; 291 292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), 293 ticks); 294 295 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks); 296 297 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR); 298 if (en) 299 ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num); 300 else 301 ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num); 302 if (autoen) 303 ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num); 304 else 305 ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num); 306 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl); 307 } 308 309 static int 310 mvsoctmr_wdog_setmode(struct sysmon_wdog *smw) 311 { 312 struct mvsoctmr_softc *sc = smw->smw_cookie; 313 314 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 315 sc->sc_wdog_armed = 0; 316 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 317 } else { 318 sc->sc_wdog_armed = 1; 319 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 320 smw->smw_period = MVSOC_WDOG_MAX_PERIOD; 321 else if (smw->smw_period > MVSOC_WDOG_MAX_PERIOD || 322 smw->smw_period <= 0) 323 return (EOPNOTSUPP); 324 sc->sc_wdog_period = smw->smw_period * mvTclk; 325 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 326 } 327 328 return (0); 329 } 330 331 static int 332 mvsoctmr_wdog_tickle(struct sysmon_wdog *smw) 333 { 334 struct mvsoctmr_softc *sc = smw->smw_cookie; 335 336 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 337 338 return (0); 339 } 340 341 #ifdef DDB 342 static void 343 mvsoctmr_wdog_ddb_trap(int enter) 344 { 345 struct mvsoctmr_softc *sc = mvsoctmr_sc; 346 347 if (sc == NULL) 348 return; 349 350 if (sc->sc_wdog_armed) { 351 if (enter) 352 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 353 else 354 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 355 sc->sc_wdog_period, 1, 0); 356 } 357 } 358 #endif 359
Indexes created Tue Sep 30 06:09:59 GMT 2025