mvsoctmr.c revision 1.3.2.1
1 /* $NetBSD: mvsoctmr.c,v 1.3.2.1 2013/01/13 19:03:05 bouyer Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.3.2.1 2013/01/13 19:03:05 bouyer Exp $"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/atomic.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/errno.h> 37 #include <sys/kernel.h> 38 #include <sys/time.h> 39 #include <sys/timetc.h> 40 #include <sys/systm.h> 41 #include <sys/wdog.h> 42 43 #include <machine/intr.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <arm/marvell/mvsocreg.h> 48 #include <arm/marvell/mvsocvar.h> 49 #include <arm/marvell/mvsoctmrreg.h> 50 51 #include <dev/marvell/marvellvar.h> 52 53 #include <dev/sysmon/sysmonvar.h> 54 55 #ifdef DDB 56 #include <machine/db_machdep.h> 57 #include <ddb/db_extern.h> 58 #endif 59 60 61 struct mvsoctmr_softc { 62 device_t sc_dev; 63 64 struct sysmon_wdog sc_wdog; 65 uint32_t sc_wdog_period; 66 uint32_t sc_wdog_armed; 67 68 bus_space_tag_t sc_iot; 69 bus_space_handle_t sc_ioh; 70 }; 71 72 73 static int mvsoctmr_match(device_t, struct cfdata *, void *); 74 static void mvsoctmr_attach(device_t, device_t, void *); 75 76 static int clockhandler(void *); 77 78 static u_int mvsoctmr_get_timecount(struct timecounter *); 79 80 static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int); 81 82 static int mvsoctmr_wdog_tickle(struct sysmon_wdog *); 83 static int mvsoctmr_wdog_setmode(struct sysmon_wdog *); 84 85 #ifdef DDB 86 static void mvsoctmr_wdog_ddb_trap(int); 87 #endif 88 89 #define MVSOC_WDOG_MAX_PERIOD (0xffffffff / mvTclk) 90 91 static struct mvsoctmr_softc *mvsoctmr_sc; 92 static struct timecounter mvsoctmr_timecounter = { 93 mvsoctmr_get_timecount, /* get_timecount */ 94 0, /* no poll_pps */ 95 ~0u, /* counter_mask */ 96 0, /* frequency (set by cpu_initclocks()) */ 97 "mvsoctmr", /* name */ 98 100, /* quality */ 99 NULL, /* prev */ 100 NULL, /* next */ 101 }; 102 103 CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc), 104 mvsoctmr_match, mvsoctmr_attach, NULL, NULL); 105 106 107 /* ARGSUSED */ 108 static int 109 mvsoctmr_match(device_t parent, struct cfdata *match, void *aux) 110 { 111 struct marvell_attach_args *mva = aux; 112 113 if (strcmp(mva->mva_name, match->cf_name) != 0) 114 return 0; 115 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 116 return 0; 117 118 mva->mva_size = MVSOCTMR_SIZE; 119 return 1; 120 } 121 122 /* ARGSUSED */ 123 static void 124 mvsoctmr_attach(device_t parent, device_t self, void *aux) 125 { 126 struct mvsoctmr_softc *sc = device_private(self); 127 struct marvell_attach_args *mva = aux; 128 uint32_t rstoutn; 129 130 aprint_naive("\n"); 131 aprint_normal(": Marvell SoC Timer\n"); 132 133 if (mvsoctmr_sc == NULL) 134 mvsoctmr_sc = sc; 135 136 sc->sc_dev = self; 137 sc->sc_iot = mva->mva_iot; 138 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 139 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) 140 panic("%s: Cannot map registers", device_xname(self)); 141 142 mvsoctmr_timecounter.tc_name = device_xname(self); 143 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1); 144 145 /* 146 * stop watchdog timer, enable watchdog timer resets 147 */ 148 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 149 rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR); 150 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 151 rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN); 152 153 #ifdef DDB 154 db_trap_callback = mvsoctmr_wdog_ddb_trap; 155 #endif 156 157 sc->sc_wdog.smw_name = device_xname(self); 158 sc->sc_wdog.smw_cookie = sc; 159 sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode; 160 sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle; 161 sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD; 162 163 if (sysmon_wdog_register(&sc->sc_wdog) != 0) 164 aprint_error_dev(self, 165 "unable to register watchdog with sysmon\n"); 166 } 167 168 /* 169 * clockhandler: 170 * 171 * Handle the hardclock interrupt. 172 */ 173 static int 174 clockhandler(void *arg) 175 { 176 struct clockframe *frame = arg; 177 178 hardclock(frame); 179 180 return 1; 181 } 182 183 /* 184 * setstatclockrate: 185 * 186 * Set the rate of the statistics clock. 187 */ 188 /* ARGSUSED */ 189 void 190 setstatclockrate(int newhz) 191 { 192 } 193 194 /* 195 * cpu_initclocks: 196 * 197 * Initialize the clock and get them going. 198 */ 199 void 200 cpu_initclocks(void) 201 { 202 struct mvsoctmr_softc *sc; 203 void *clock_ih; 204 const int en = 1, autoen = 1; 205 uint32_t timer0_tval; 206 207 sc = mvsoctmr_sc; 208 if (sc == NULL) 209 panic("cpu_initclocks: mvsoctmr not found"); 210 211 mvsoctmr_timecounter.tc_priv = sc; 212 mvsoctmr_timecounter.tc_frequency = mvTclk; 213 214 timer0_tval = (mvTclk * 2) / (u_long) hz; 215 timer0_tval = (timer0_tval / 2) + (timer0_tval & 1); 216 217 mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen); 218 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen); 219 220 clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, 221 IPL_CLOCK, clockhandler, NULL); 222 if (clock_ih == NULL) 223 panic("cpu_initclocks: unable to register timer interrupt"); 224 225 tc_init(&mvsoctmr_timecounter); 226 } 227 228 void 229 delay(unsigned int n) 230 { 231 struct mvsoctmr_softc *sc; 232 unsigned int cur_tick, initial_tick; 233 int remaining; 234 235 sc = mvsoctmr_sc; 236 #ifdef DEBUG 237 if (sc == NULL) { 238 printf("%s: called before start mvsoctmr\n", __func__); 239 return; 240 } 241 #endif 242 243 /* 244 * Read the counter first, so that the rest of the setup overhead is 245 * counted. 246 */ 247 initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 248 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 249 250 if (n <= UINT_MAX / mvTclk) { 251 /* 252 * For unsigned arithmetic, division can be replaced with 253 * multiplication with the inverse and a shift. 254 */ 255 remaining = n * mvTclk / 1000000; 256 } else { 257 /* 258 * This is a very long delay. 259 * Being slow here doesn't matter. 260 */ 261 remaining = (unsigned long long) n * mvTclk / 1000000; 262 } 263 264 while (remaining > 0) { 265 cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 266 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 267 if (cur_tick > initial_tick) 268 remaining -= 0xffffffff - cur_tick + initial_tick; 269 else 270 remaining -= (initial_tick - cur_tick); 271 initial_tick = cur_tick; 272 } 273 } 274 275 static u_int 276 mvsoctmr_get_timecount(struct timecounter *tc) 277 { 278 struct mvsoctmr_softc *sc = tc->tc_priv; 279 280 return 0xffffffff - bus_space_read_4(sc->sc_iot, sc->sc_ioh, 281 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 282 } 283 284 static void 285 mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en, 286 int autoen) 287 { 288 uint32_t ctrl; 289 290 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), 291 ticks); 292 293 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks); 294 295 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR); 296 if (en) 297 ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num); 298 else 299 ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num); 300 if (autoen) 301 ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num); 302 else 303 ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num); 304 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl); 305 } 306 307 static int 308 mvsoctmr_wdog_setmode(struct sysmon_wdog *smw) 309 { 310 struct mvsoctmr_softc *sc = smw->smw_cookie; 311 312 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 313 sc->sc_wdog_armed = 0; 314 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 315 } else { 316 sc->sc_wdog_armed = 1; 317 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 318 smw->smw_period = MVSOC_WDOG_MAX_PERIOD; 319 else if (smw->smw_period > MVSOC_WDOG_MAX_PERIOD || 320 smw->smw_period <= 0) 321 return (EOPNOTSUPP); 322 sc->sc_wdog_period = smw->smw_period * mvTclk; 323 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 324 } 325 326 return (0); 327 } 328 329 static int 330 mvsoctmr_wdog_tickle(struct sysmon_wdog *smw) 331 { 332 struct mvsoctmr_softc *sc = smw->smw_cookie; 333 334 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 335 336 return (0); 337 } 338 339 #ifdef DDB 340 static void 341 mvsoctmr_wdog_ddb_trap(int enter) 342 { 343 struct mvsoctmr_softc *sc = mvsoctmr_sc; 344 345 if (sc == NULL) 346 return; 347 348 if (sc->sc_wdog_armed) { 349 if (enter) 350 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 351 else 352 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 353 sc->sc_wdog_period, 1, 0); 354 } 355 } 356 #endif 357
Indexes created Tue Sep 30 06:09:59 GMT 2025