mvsoctmr.c revision 1.9.4.1
1 /* $NetBSD: mvsoctmr.c,v 1.9.4.1 2014/05/18 17:44:58 rmind Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.9.4.1 2014/05/18 17:44:58 rmind Exp $"); 29 30 #include "opt_ddb.h" 31 #include "opt_mvsoc.h" 32 33 #include <sys/param.h> 34 #include <sys/atomic.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/kernel.h> 39 #include <sys/time.h> 40 #include <sys/timetc.h> 41 #include <sys/systm.h> 42 #include <sys/wdog.h> 43 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/marvell/mvsocreg.h> 49 #include <arm/marvell/mvsocvar.h> 50 #include <arm/marvell/mvsoctmrreg.h> 51 52 #include <dev/marvell/marvellreg.h> 53 #include <dev/marvell/marvellvar.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 #ifdef DDB 58 #include <machine/db_machdep.h> 59 #include <ddb/db_extern.h> 60 #endif 61 62 63 struct mvsoctmr_softc { 64 device_t sc_dev; 65 66 struct sysmon_wdog sc_wdog; 67 uint32_t sc_wdog_period; 68 uint32_t sc_wdog_armed; 69 70 bus_space_tag_t sc_iot; 71 bus_space_handle_t sc_ioh; 72 int sc_irq; 73 74 #define TMR_FLAGS_NOBRIDGE (1 << 0) 75 #define TMR_FLAGS_25MHZ (1 << 1) 76 #define TMR_FLAGS_SYSCLK (1 << 2) 77 int sc_flags; 78 }; 79 80 81 static int mvsoctmr_match(device_t, struct cfdata *, void *); 82 static void mvsoctmr_attach(device_t, device_t, void *); 83 84 static int clockhandler(void *); 85 86 static u_int mvsoctmr_get_timecount(struct timecounter *); 87 88 static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int); 89 90 static int mvsoctmr_wdog_tickle(struct sysmon_wdog *); 91 static int mvsoctmr_wdog_setmode(struct sysmon_wdog *); 92 93 #ifdef DDB 94 static void mvsoctmr_wdog_ddb_trap(int); 95 #endif 96 97 static int mvsoctmr_freq; 98 99 #define MVSOC_WDOG_MAX_PERIOD (0xffffffff / mvsoctmr_freq) 100 101 static struct mvsoctmr_softc *mvsoctmr_sc; 102 static struct timecounter mvsoctmr_timecounter = { 103 mvsoctmr_get_timecount, /* get_timecount */ 104 0, /* no poll_pps */ 105 ~0u, /* counter_mask */ 106 0, /* frequency (set by cpu_initclocks()) */ 107 "mvsoctmr", /* name */ 108 100, /* quality */ 109 NULL, /* prev */ 110 NULL, /* next */ 111 }; 112 113 CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc), 114 mvsoctmr_match, mvsoctmr_attach, NULL, NULL); 115 116 117 /* ARGSUSED */ 118 static int 119 mvsoctmr_match(device_t parent, struct cfdata *match, void *aux) 120 { 121 struct marvell_attach_args *mva = aux; 122 123 if (strcmp(mva->mva_name, match->cf_name) != 0) 124 return 0; 125 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 126 mva->mva_irq == MVA_IRQ_DEFAULT) 127 return 0; 128 129 mva->mva_size = MVSOCTMR_SIZE; 130 return 1; 131 } 132 133 /* ARGSUSED */ 134 static void 135 mvsoctmr_attach(device_t parent, device_t self, void *aux) 136 { 137 struct mvsoctmr_softc *sc = device_private(self); 138 struct marvell_attach_args *mva = aux; 139 uint32_t rstoutn; 140 141 aprint_naive("\n"); 142 aprint_normal(": Marvell SoC Timer\n"); 143 144 if (mvsoctmr_sc == NULL) 145 mvsoctmr_sc = sc; 146 147 sc->sc_dev = self; 148 sc->sc_iot = mva->mva_iot; 149 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 150 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) 151 panic("%s: Cannot map registers", device_xname(self)); 152 sc->sc_irq = mva->mva_irq; 153 154 switch (mva->mva_model) { 155 case MARVELL_ARMADAXP_MV78130: 156 case MARVELL_ARMADAXP_MV78160: 157 case MARVELL_ARMADAXP_MV78230: 158 case MARVELL_ARMADAXP_MV78260: 159 case MARVELL_ARMADAXP_MV78460: 160 sc->sc_flags = TMR_FLAGS_25MHZ | TMR_FLAGS_NOBRIDGE; 161 break; 162 case MARVELL_ARMADA370_MV6707: 163 case MARVELL_ARMADA370_MV6710: 164 case MARVELL_ARMADA370_MV6W11: 165 sc->sc_flags = TMR_FLAGS_NOBRIDGE | TMR_FLAGS_SYSCLK; 166 break; 167 } 168 169 mvsoctmr_timecounter.tc_name = device_xname(self); 170 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1); 171 172 /* 173 * stop watchdog timer, enable watchdog timer resets 174 */ 175 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 176 write_mlmbreg(MVSOC_MLMB_MLMBICR, 177 ~(1<<MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ)); 178 rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR); 179 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 180 rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN); 181 182 #ifdef DDB 183 db_trap_callback = mvsoctmr_wdog_ddb_trap; 184 #endif 185 186 if (sc->sc_flags & TMR_FLAGS_25MHZ) 187 /* We set global timer and counter to 25 MHz mode */ 188 mvsoctmr_freq = 25000000; 189 else if (sc->sc_flags & TMR_FLAGS_SYSCLK) 190 mvsoctmr_freq = mvSysclk; 191 else 192 mvsoctmr_freq = mvTclk; 193 194 sc->sc_wdog.smw_name = device_xname(self); 195 sc->sc_wdog.smw_cookie = sc; 196 sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode; 197 sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle; 198 sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD; 199 200 if (sysmon_wdog_register(&sc->sc_wdog) != 0) 201 aprint_error_dev(self, 202 "unable to register watchdog with sysmon\n"); 203 } 204 205 /* 206 * clockhandler: 207 * 208 * Handle the hardclock interrupt. 209 */ 210 static int 211 clockhandler(void *arg) 212 { 213 struct clockframe *frame = arg; 214 215 #if defined(ARMADAXP) 216 KASSERT(mvsoctmr_sc != NULL); 217 218 if (mvsoctmr_sc->sc_flags & TMR_FLAGS_NOBRIDGE) 219 /* Acknowledge all timers-related interrupts */ 220 bus_space_write_4(mvsoctmr_sc->sc_iot, mvsoctmr_sc->sc_ioh, 221 MVSOCTMR_TESR, 0x0); 222 #endif 223 224 hardclock(frame); 225 226 return 1; 227 } 228 229 /* 230 * setstatclockrate: 231 * 232 * Set the rate of the statistics clock. 233 */ 234 /* ARGSUSED */ 235 void 236 setstatclockrate(int newhz) 237 { 238 } 239 240 /* 241 * cpu_initclocks: 242 * 243 * Initialize the clock and get them going. 244 */ 245 void 246 cpu_initclocks(void) 247 { 248 struct mvsoctmr_softc *sc; 249 void *clock_ih; 250 const int en = 1, autoen = 1; 251 uint32_t timer0_tval; 252 253 sc = mvsoctmr_sc; 254 if (sc == NULL) 255 panic("cpu_initclocks: mvsoctmr not found"); 256 257 mvsoctmr_timecounter.tc_priv = sc; 258 mvsoctmr_timecounter.tc_frequency = mvsoctmr_freq; 259 260 timer0_tval = (mvsoctmr_freq * 2) / (u_long) hz; 261 timer0_tval = (timer0_tval / 2) + (timer0_tval & 1); 262 263 mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen); 264 mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen); 265 266 if (sc->sc_flags & TMR_FLAGS_NOBRIDGE) { 267 /* 268 * Establishing timer interrupts is slightly different for 269 * Armada XP than for other supported SoCs from Marvell. 270 * Timer interrupt is no different from any other interrupt 271 * in Armada XP, so we use generic marvell_intr_establish(). 272 */ 273 clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK, 274 clockhandler, NULL); 275 } else 276 clock_ih = mvsoc_bridge_intr_establish( 277 MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, IPL_CLOCK, clockhandler, 278 NULL); 279 if (clock_ih == NULL) 280 panic("cpu_initclocks: unable to register timer interrupt"); 281 282 tc_init(&mvsoctmr_timecounter); 283 } 284 285 void 286 delay(unsigned int n) 287 { 288 struct mvsoctmr_softc *sc; 289 unsigned int cur_tick, initial_tick; 290 int remaining; 291 292 sc = mvsoctmr_sc; 293 #ifdef DEBUG 294 if (sc == NULL) { 295 printf("%s: called before start mvsoctmr\n", __func__); 296 return; 297 } 298 #endif 299 300 /* 301 * Read the counter first, so that the rest of the setup overhead is 302 * counted. 303 */ 304 initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 305 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 306 307 if (n <= UINT_MAX / mvsoctmr_freq) { 308 /* 309 * For unsigned arithmetic, division can be replaced with 310 * multiplication with the inverse and a shift. 311 */ 312 remaining = n * mvsoctmr_freq / 1000000; 313 } else { 314 /* 315 * This is a very long delay. 316 * Being slow here doesn't matter. 317 */ 318 remaining = (unsigned long long) n * mvsoctmr_freq / 1000000; 319 } 320 321 while (remaining > 0) { 322 cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 323 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 324 if (cur_tick > initial_tick) 325 remaining -= 0xffffffff - cur_tick + initial_tick; 326 else 327 remaining -= (initial_tick - cur_tick); 328 initial_tick = cur_tick; 329 } 330 } 331 332 static u_int 333 mvsoctmr_get_timecount(struct timecounter *tc) 334 { 335 struct mvsoctmr_softc *sc = tc->tc_priv; 336 337 return 0xffffffff - bus_space_read_4(sc->sc_iot, sc->sc_ioh, 338 MVSOCTMR_TIMER(MVSOCTMR_TIMER1)); 339 } 340 341 static void 342 mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en, 343 int autoen) 344 { 345 uint32_t ctrl; 346 347 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), ticks); 348 349 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks); 350 351 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR); 352 if (en) 353 ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num); 354 else 355 ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num); 356 if (autoen) 357 ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num); 358 else 359 ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num); 360 if (sc->sc_flags & TMR_FLAGS_25MHZ) 361 /* Set timer and counter to 25MHz mode */ 362 ctrl |= MVSOCTMR_CTCR_25MHZEN(num); 363 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl); 364 } 365 366 static int 367 mvsoctmr_wdog_setmode(struct sysmon_wdog *smw) 368 { 369 struct mvsoctmr_softc *sc = smw->smw_cookie; 370 371 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 372 sc->sc_wdog_armed = 0; 373 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 374 } else { 375 sc->sc_wdog_armed = 1; 376 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 377 smw->smw_period = MVSOC_WDOG_MAX_PERIOD; 378 else if (smw->smw_period > MVSOC_WDOG_MAX_PERIOD || 379 smw->smw_period <= 0) 380 return (EOPNOTSUPP); 381 sc->sc_wdog_period = smw->smw_period * mvsoctmr_freq; 382 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 383 } 384 385 return (0); 386 } 387 388 static int 389 mvsoctmr_wdog_tickle(struct sysmon_wdog *smw) 390 { 391 struct mvsoctmr_softc *sc = smw->smw_cookie; 392 393 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, sc->sc_wdog_period, 1, 0); 394 395 return (0); 396 } 397 398 #ifdef DDB 399 static void 400 mvsoctmr_wdog_ddb_trap(int enter) 401 { 402 struct mvsoctmr_softc *sc = mvsoctmr_sc; 403 404 if (sc == NULL) 405 return; 406 407 if (sc->sc_wdog_armed) { 408 if (enter) 409 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); 410 else 411 mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 412 sc->sc_wdog_period, 1, 0); 413 } 414 } 415 #endif 416
Indexes created Tue Sep 30 06:09:59 GMT 2025