pci_machdep.c revision 1.10
1 /* $NetBSD: pci_machdep.c,v 1.10 2016/07/12 13:43:18 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.10 2016/07/12 13:43:18 kiyohara Exp $"); 30 31 #include "opt_mvsoc.h" 32 #include "gtpci.h" 33 #include "mvpex.h" 34 #include "pci.h" 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pciconf.h> 42 43 #include <arm/marvell/mvsocreg.h> 44 #include <arm/marvell/mvsocvar.h> 45 #include <arm/marvell/mvsocgppvar.h> 46 #if NGTPCI > 0 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #endif 50 #if NMVPEX > 0 51 #include <dev/marvell/mvpexreg.h> 52 #include <dev/marvell/mvpexvar.h> 53 #endif 54 55 #include <machine/pci_machdep.h> 56 57 #if defined(ORION) 58 #include <arm/marvell/orionreg.h> 59 #endif 60 #if defined(KIRKWOOD) 61 #include <arm/marvell/kirkwoodreg.h> 62 #endif 63 #include <dev/marvell/marvellreg.h> 64 65 66 #if NGTPCI > 0 67 #if NGTPCI_MBUS > 0 68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int); 69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t); 70 #endif 71 static int gtpci_gpp_intr_map(const struct pci_attach_args *, 72 pci_intr_handle_t *); 73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t, 74 char *, size_t); 75 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t); 76 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *); 77 static void gtpci_gpp_intr_disestablish(void *, void *); 78 79 struct arm32_pci_chipset arm32_gtpci_chipset = { 80 NULL, /* conf_v */ 81 gtpci_attach_hook, 82 gtpci_bus_maxdevs, 83 gtpci_make_tag, 84 gtpci_decompose_tag, 85 #if NGTPCI_MBUS > 0 86 gtpci_mbus_conf_read, /* XXXX: always this functions */ 87 gtpci_mbus_conf_write, 88 #else 89 gtpci_conf_read, 90 gtpci_conf_write, 91 #endif 92 NULL, /* intr_v */ 93 gtpci_gpp_intr_map, 94 gtpci_gpp_intr_string, 95 gtpci_gpp_intr_evcnt, 96 gtpci_gpp_intr_establish, 97 gtpci_gpp_intr_disestablish, 98 #ifdef __HAVE_PCI_CONF_HOOK 99 gtpci_conf_hook, 100 #endif 101 gtpci_conf_interrupt, 102 }; 103 #endif 104 105 #if NMVPEX > 0 106 #if NMVPEX_MBUS > 0 107 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int); 108 #endif 109 110 struct arm32_pci_chipset arm32_mvpex0_chipset = { 111 NULL, /* conf_v */ 112 mvpex_attach_hook, 113 mvpex_bus_maxdevs, 114 mvpex_make_tag, 115 mvpex_decompose_tag, 116 #if NMVPEX_MBUS > 0 117 mvpex_mbus_conf_read, /* XXXX: always this functions */ 118 #else 119 mvpex_conf_read, 120 #endif 121 mvpex_conf_write, 122 NULL, /* intr_v */ 123 mvpex_intr_map, 124 mvpex_intr_string, 125 mvpex_intr_evcnt, 126 mvpex_intr_establish, 127 mvpex_intr_disestablish, 128 #ifdef __HAVE_PCI_CONF_HOOK 129 mvpex_conf_hook, 130 #endif 131 mvpex_conf_interrupt, 132 }; 133 struct arm32_pci_chipset arm32_mvpex1_chipset = { 134 NULL, /* conf_v */ 135 mvpex_attach_hook, 136 mvpex_bus_maxdevs, 137 mvpex_make_tag, 138 mvpex_decompose_tag, 139 #if NMVPEX_MBUS > 0 140 mvpex_mbus_conf_read, /* XXXX: always this functions */ 141 #else 142 mvpex_conf_read, 143 #endif 144 mvpex_conf_write, 145 NULL, /* intr_v */ 146 mvpex_intr_map, 147 mvpex_intr_string, 148 mvpex_intr_evcnt, 149 mvpex_intr_establish, 150 mvpex_intr_disestablish, 151 #ifdef __HAVE_PCI_CONF_HOOK 152 mvpex_conf_hook, 153 #endif 154 mvpex_conf_interrupt, 155 }; 156 struct arm32_pci_chipset arm32_mvpex2_chipset = { 157 NULL, /* conf_v */ 158 mvpex_attach_hook, 159 mvpex_bus_maxdevs, 160 mvpex_make_tag, 161 mvpex_decompose_tag, 162 #if NMVPEX_MBUS > 0 163 mvpex_mbus_conf_read, /* XXXX: always this functions */ 164 #else 165 mvpex_conf_read, 166 #endif 167 mvpex_conf_write, 168 NULL, /* intr_v */ 169 mvpex_intr_map, 170 mvpex_intr_string, 171 mvpex_intr_evcnt, 172 mvpex_intr_establish, 173 mvpex_intr_disestablish, 174 #ifdef __HAVE_PCI_CONF_HOOK 175 mvpex_conf_hook, 176 #endif 177 mvpex_conf_interrupt, 178 }; 179 struct arm32_pci_chipset arm32_mvpex3_chipset = { 180 NULL, /* conf_v */ 181 mvpex_attach_hook, 182 mvpex_bus_maxdevs, 183 mvpex_make_tag, 184 mvpex_decompose_tag, 185 #if NMVPEX_MBUS > 0 186 mvpex_mbus_conf_read, /* XXXX: always this functions */ 187 #else 188 mvpex_conf_read, 189 #endif 190 mvpex_conf_write, 191 NULL, /* intr_v */ 192 mvpex_intr_map, 193 mvpex_intr_string, 194 mvpex_intr_evcnt, 195 mvpex_intr_establish, 196 mvpex_intr_disestablish, 197 #ifdef __HAVE_PCI_CONF_HOOK 198 mvpex_conf_hook, 199 #endif 200 mvpex_conf_interrupt, 201 }; 202 struct arm32_pci_chipset arm32_mvpex4_chipset = { 203 NULL, /* conf_v */ 204 mvpex_attach_hook, 205 mvpex_bus_maxdevs, 206 mvpex_make_tag, 207 mvpex_decompose_tag, 208 #if NMVPEX_MBUS > 0 209 mvpex_mbus_conf_read, /* XXXX: always this functions */ 210 #else 211 mvpex_conf_read, 212 #endif 213 mvpex_conf_write, 214 NULL, /* intr_v */ 215 mvpex_intr_map, 216 mvpex_intr_string, 217 mvpex_intr_evcnt, 218 mvpex_intr_establish, 219 mvpex_intr_disestablish, 220 #ifdef __HAVE_PCI_CONF_HOOK 221 mvpex_conf_hook, 222 #endif 223 mvpex_conf_interrupt, 224 }; 225 struct arm32_pci_chipset arm32_mvpex5_chipset = { 226 NULL, /* conf_v */ 227 mvpex_attach_hook, 228 mvpex_bus_maxdevs, 229 mvpex_make_tag, 230 mvpex_decompose_tag, 231 #if NMVPEX_MBUS > 0 232 mvpex_mbus_conf_read, /* XXXX: always this functions */ 233 #else 234 mvpex_conf_read, 235 #endif 236 mvpex_conf_write, 237 NULL, /* intr_v */ 238 mvpex_intr_map, 239 mvpex_intr_string, 240 mvpex_intr_evcnt, 241 mvpex_intr_establish, 242 mvpex_intr_disestablish, 243 #ifdef __HAVE_PCI_CONF_HOOK 244 mvpex_conf_hook, 245 #endif 246 mvpex_conf_interrupt, 247 }; 248 #endif /* NMVPEX > 0 */ 249 250 #if NGTPCI > 0 251 /* ARGSUSED */ 252 void 253 gtpci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, int *iline) 254 { 255 256 /* nothing */ 257 } 258 259 #if NGTPCI_MBUS > 0 260 #define GTPCI_MBUS_CA 0x0c78 /* Configuration Address */ 261 #define GTPCI_MBUS_CD 0x0c7c /* Configuration Data */ 262 263 static pcireg_t 264 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg) 265 { 266 struct gtpci_softc *sc = v; 267 const pcireg_t addr = tag | reg; 268 269 if ((unsigned int)reg >= PCI_CONF_SIZE) 270 return -1; 271 272 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 273 addr | GTPCI_CA_CONFIGEN); 274 if ((addr | GTPCI_CA_CONFIGEN) != 275 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 276 return -1; 277 278 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD); 279 } 280 281 static void 282 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 283 { 284 struct gtpci_softc *sc = v; 285 pcireg_t addr = tag | (reg & 0xfc); 286 287 if ((unsigned int)reg >= PCI_CONF_SIZE) 288 return; 289 290 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 291 addr | GTPCI_CA_CONFIGEN); 292 if ((addr | GTPCI_CA_CONFIGEN) != 293 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 294 return; 295 296 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data); 297 } 298 #endif /* NGTPCI_MBUS */ 299 300 /* 301 * We assume to use GPP interrupt as PCI interrupts. 302 * pci_intr_map() shall returns number of GPP between 0 and 31. However 303 * returns 0xff, because we do not know the connected pin number for GPP 304 * of your board. 305 * pci_intr_string() shall returns string "gpp <num>". 306 * pci_intr_establish() established interrupt in the pin of all GPP. 307 * Moreover, the return value will be disregarded. For instance, the 308 * setting for interrupt is not done. 309 */ 310 311 /* ARGSUSED */ 312 static int 313 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 314 { 315 316 *ihp = pa->pa_intrpin; 317 return 0; 318 } 319 320 /* ARGSUSED */ 321 static const char * 322 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin, char *buf, size_t len) 323 { 324 struct gtpci_softc *sc = v; 325 prop_array_t int2gpp; 326 prop_object_t gpp; 327 328 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 329 gpp = prop_array_get(int2gpp, pin); 330 snprintf(buf, len, "gpp %d", (int)prop_number_integer_value(gpp)); 331 332 return buf; 333 } 334 335 /* ARGSUSED */ 336 static const struct evcnt * 337 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin) 338 { 339 340 return NULL; 341 } 342 343 static void * 344 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl, 345 int (*intrhand)(void *), void *intrarg) 346 { 347 struct gtpci_softc *sc = v; 348 prop_array_t int2gpp; 349 prop_object_t gpp; 350 int gpp_pin; 351 352 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 353 gpp = prop_array_get(int2gpp, int_pin); 354 gpp_pin = prop_number_integer_value(gpp); 355 return mvsocgpp_intr_establish(gpp_pin, ipl, IST_LEVEL_LOW, intrhand, 356 intrarg); 357 } 358 359 static void 360 gtpci_gpp_intr_disestablish(void *v, void *ih) 361 { 362 363 mvsocgpp_intr_disestablish(ih); 364 } 365 #endif 366 367 #if NMVPEX_MBUS > 0 368 /* ARGSUSED */ 369 void 370 mvpex_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 371 { 372 373 /* nothing */ 374 } 375 376 static pcireg_t 377 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg) 378 { 379 struct mvpex_softc *sc = v; 380 pcireg_t addr, data, pci_cs; 381 uint32_t stat; 382 int bus, dev, func, pexbus, pexdev; 383 384 if ((unsigned int)reg >= PCI_CONF_SIZE) 385 return -1; 386 387 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 388 389 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 390 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 391 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 392 if (bus != pexbus || dev != pexdev) 393 if (stat & MVPEX_STAT_DLDOWN) 394 return -1; 395 396 if (bus == pexbus) { 397 if (pexdev == 0) { 398 if (dev != 1 && dev != pexdev) 399 return -1; 400 } else { 401 if (dev != 0 && dev != pexdev) 402 return -1; 403 } 404 if (func != 0) 405 return -1; 406 } 407 408 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 409 410 #if defined(ORION) 411 /* 412 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration 413 * This guideline is relevant for all devices except of the following 414 * devices: 415 * 88F5281-BO and above, and 88F5181L-A0 and above 416 */ 417 if ((bus != pexbus || dev != pexdev) && 418 !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) && 419 !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) { 420 421 /* PCI-Express configuration read work-around */ 422 /* 423 * We will use one of the Punit (AHBToMbus) windows to 424 * access the xbar and read the data from there 425 * 426 * Need to configure the 2 free Punit (AHB to MBus bridge) 427 * address decoding windows: 428 * Configure the flash Window to handle Configuration space 429 * requests for PEX0/1: 430 * 431 * Configuration transactions from the CPU should write/read 432 * the data to/from address of the form: 433 * addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1) 434 * addr[27:24]: extended register number 435 * addr[23:16]: bus number 436 * addr[15:11]: device number 437 * addr[10: 8]: function number 438 * addr[ 7: 0]: register number 439 */ 440 441 struct mvsoc_softc *soc = 442 device_private(device_parent(sc->sc_dev));; 443 bus_space_handle_t pcicfg_ioh; 444 uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size; 445 int window, target, attr, base, size, s; 446 const int pex_pcicfg_tag = 447 (sc->sc_model == MARVELL_ORION_1_88F1181) ? 448 ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM; 449 450 window = mvsoc_target(pex_pcicfg_tag, 451 &target, &attr, &base, &size); 452 if (window >= nwindow) { 453 aprint_error_dev(sc->sc_dev, 454 "can't read pcicfg space\n"); 455 return -1; 456 } 457 458 s = splhigh(); 459 460 remapl = remaph = 0; 461 if (window == 0 || window == 1) { 462 remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window)); 463 remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window)); 464 } 465 466 wc = 467 MVSOC_MLMB_WCR_WINEN | 468 MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG) | 469 MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16); 470 if (sc->sc_model == MARVELL_ORION_1_88F1181) { 471 pcicfg_addr = base; 472 pcicfg_size = size; 473 } else if (sc->sc_model == MARVELL_ORION_1_88F5182) { 474 #define PEX_PCICFG_RW_WA_BASE 0x50000000 475 #define PEX_PCICFG_RW_WA_5182_BASE 0xf0000000 476 #define PEX_PCICFG_RW_WA_SIZE (16 * 1024 * 1024) 477 pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE; 478 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 479 } else { 480 pcicfg_addr = PEX_PCICFG_RW_WA_BASE; 481 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 482 } 483 write_mlmbreg(MVSOC_MLMB_WCR(window), 484 wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size)); 485 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr); 486 487 if (window == 0 || window == 1) { 488 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr); 489 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 490 } 491 492 if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0, 493 &pcicfg_ioh) == 0) { 494 data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr); 495 bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size); 496 } else 497 data = -1; 498 499 write_mlmbreg(MVSOC_MLMB_WCR(window), 500 MVSOC_MLMB_WCR_WINEN | 501 MVSOC_MLMB_WCR_ATTR(attr) | 502 MVSOC_MLMB_WCR_TARGET(target) | 503 MVSOC_MLMB_WCR_SIZE(size)); 504 write_mlmbreg(MVSOC_MLMB_WBR(window), base); 505 if (window == 0 || window == 1) { 506 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl); 507 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph); 508 } 509 510 splx(s); 511 #else 512 if (0) { 513 #endif 514 } else { 515 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 516 addr | MVPEX_CA_CONFIGEN); 517 if ((addr | MVPEX_CA_CONFIGEN) != 518 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 519 return -1; 520 521 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 522 PCI_COMMAND_STATUS_REG); 523 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 524 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 525 526 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 527 } 528 529 return data; 530 } 531 #endif 532
Indexes created Mon Sep 29 21:09:56 GMT 2025