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History log of /src/sys/arch/arm/marvell/pci_machdep.c
RevisionDateAuthorComments
 1.16  14-May-2020  msaitoh Remove extra semicolon.
 1.15  26-Nov-2018  jmcneill Switch to designated initializers
 1.14  16-Nov-2018  jmcneill Add intr_establish_xname support to arm and expose it to intrctl
 1.13  03-Nov-2018  jmcneill Fix build
 1.12  19-Apr-2017  jmcneill branches: 1.12.10; 1.12.12;
Initialize intr_setattr of arm32_pci_chipset
 1.11  10-Mar-2017  skrll Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0
 1.10  12-Jul-2016  kiyohara branches: 1.10.2; 1.10.4;
Fix intr_establish. PCI interrupt is LEVEL LOW.
 1.9  02-Oct-2015  msaitoh PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific
 1.8  30-Mar-2014  christos branches: 1.8.6;
wrap a few lines
 1.7  29-Mar-2014  christos make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.
 1.6  26-Mar-2014  christos kill sprintf
 1.5  01-May-2013  rkujawa branches: 1.5.4;
Handle situations where we can have more pexes, like Armada XP.

Obtained from Marvell, Semihalf.
 1.4  07-Sep-2012  matt branches: 1.4.2;
Fix pci_conf_hook/interrupt for ARM.
 1.3  07-Sep-2012  matt Fix more pci_conf_interrupt/pci_conf_hook problems
 1.2  04-Apr-2011  dyoung branches: 1.2.4;
Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'
 1.1  03-Oct-2010  kiyohara branches: 1.1.2; 1.1.4; 1.1.6; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
 1.1.10.3  21-Apr-2011  rmind sync with head
 1.1.10.2  05-Mar-2011  rmind sync with head
 1.1.10.1  03-Oct-2010  rmind file pci_machdep.c was added on branch rmind-uvmplock on 2011-03-05 20:49:37 +0000
 1.1.6.1  06-Jun-2011  jruoho Sync with HEAD.
 1.1.4.2  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.1.4.1  03-Oct-2010  uebayasi file pci_machdep.c was added on branch uebayasi-xip on 2010-10-22 09:23:12 +0000
 1.1.2.2  09-Oct-2010  yamt sync with head
 1.1.2.1  03-Oct-2010  yamt file pci_machdep.c was added on branch yamt-nfs-mp on 2010-10-09 03:31:40 +0000
 1.2.4.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.2.4.1  30-Oct-2012  yamt sync with head
 1.4.2.3  03-Dec-2017  jdolecek update from HEAD
 1.4.2.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.4.2.1  23-Jun-2013  tls resync from head
 1.5.4.1  18-May-2014  rmind sync with head
 1.8.6.3  28-Aug-2017  skrll Sync with HEAD
 1.8.6.2  05-Oct-2016  skrll Sync with HEAD
 1.8.6.1  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.10.4.1  21-Apr-2017  bouyer Sync with HEAD
 1.10.2.2  26-Apr-2017  pgoyette Sync with HEAD
 1.10.2.1  20-Mar-2017  pgoyette Sync with HEAD
 1.12.12.1  10-Jun-2019  christos Sync with HEAD
 1.12.10.2  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.12.10.1  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts

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