pci_machdep.c revision 1.11
1 /* $NetBSD: pci_machdep.c,v 1.11 2017/03/10 15:44:24 skrll Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.11 2017/03/10 15:44:24 skrll Exp $"); 30 31 #include "opt_mvsoc.h" 32 #include "gtpci.h" 33 #include "mvpex.h" 34 #include "pci.h" 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pciconf.h> 42 43 #include <arm/marvell/mvsocreg.h> 44 #include <arm/marvell/mvsocvar.h> 45 #include <arm/marvell/mvsocgppvar.h> 46 #if NGTPCI > 0 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #endif 50 #if NMVPEX > 0 51 #include <dev/marvell/mvpexreg.h> 52 #include <dev/marvell/mvpexvar.h> 53 #endif 54 55 #include <machine/pci_machdep.h> 56 57 #if defined(ORION) 58 #include <arm/marvell/orionreg.h> 59 #endif 60 #if defined(KIRKWOOD) 61 #include <arm/marvell/kirkwoodreg.h> 62 #endif 63 #include <dev/marvell/marvellreg.h> 64 65 66 #if NGTPCI > 0 67 #if NGTPCI_MBUS > 0 68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int); 69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t); 70 #endif 71 static int gtpci_gpp_intr_map(const struct pci_attach_args *, 72 pci_intr_handle_t *); 73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t, 74 char *, size_t); 75 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t); 76 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *); 77 static void gtpci_gpp_intr_disestablish(void *, void *); 78 79 struct arm32_pci_chipset arm32_gtpci_chipset = { 80 NULL, /* conf_v */ 81 gtpci_attach_hook, 82 gtpci_bus_maxdevs, 83 gtpci_make_tag, 84 gtpci_decompose_tag, 85 #if NGTPCI_MBUS > 0 86 gtpci_mbus_conf_read, /* XXXX: always this functions */ 87 gtpci_mbus_conf_write, 88 #else 89 gtpci_conf_read, 90 gtpci_conf_write, 91 #endif 92 NULL, /* intr_v */ 93 gtpci_gpp_intr_map, 94 gtpci_gpp_intr_string, 95 gtpci_gpp_intr_evcnt, 96 gtpci_gpp_intr_establish, 97 gtpci_gpp_intr_disestablish, 98 #ifdef __HAVE_PCI_CONF_HOOK 99 gtpci_conf_hook, 100 #endif 101 gtpci_conf_interrupt, 102 }; 103 #endif 104 105 #if NMVPEX > 0 106 #if NMVPEX_MBUS > 0 107 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int); 108 #endif 109 110 struct arm32_pci_chipset arm32_mvpex0_chipset = { 111 NULL, /* conf_v */ 112 mvpex_attach_hook, 113 mvpex_bus_maxdevs, 114 mvpex_make_tag, 115 mvpex_decompose_tag, 116 #if NMVPEX_MBUS > 0 117 mvpex_mbus_conf_read, /* XXXX: always this functions */ 118 #else 119 mvpex_conf_read, 120 #endif 121 mvpex_conf_write, 122 NULL, /* intr_v */ 123 mvpex_intr_map, 124 mvpex_intr_string, 125 mvpex_intr_evcnt, 126 mvpex_intr_establish, 127 mvpex_intr_disestablish, 128 #ifdef __HAVE_PCI_CONF_HOOK 129 mvpex_conf_hook, 130 #endif 131 mvpex_conf_interrupt, 132 }; 133 struct arm32_pci_chipset arm32_mvpex1_chipset = { 134 NULL, /* conf_v */ 135 mvpex_attach_hook, 136 mvpex_bus_maxdevs, 137 mvpex_make_tag, 138 mvpex_decompose_tag, 139 #if NMVPEX_MBUS > 0 140 mvpex_mbus_conf_read, /* XXXX: always this functions */ 141 #else 142 mvpex_conf_read, 143 #endif 144 mvpex_conf_write, 145 NULL, /* intr_v */ 146 mvpex_intr_map, 147 mvpex_intr_string, 148 mvpex_intr_evcnt, 149 mvpex_intr_establish, 150 mvpex_intr_disestablish, 151 #ifdef __HAVE_PCI_CONF_HOOK 152 mvpex_conf_hook, 153 #endif 154 mvpex_conf_interrupt, 155 }; 156 struct arm32_pci_chipset arm32_mvpex2_chipset = { 157 NULL, /* conf_v */ 158 mvpex_attach_hook, 159 mvpex_bus_maxdevs, 160 mvpex_make_tag, 161 mvpex_decompose_tag, 162 #if NMVPEX_MBUS > 0 163 mvpex_mbus_conf_read, /* XXXX: always this functions */ 164 #else 165 mvpex_conf_read, 166 #endif 167 mvpex_conf_write, 168 NULL, /* intr_v */ 169 mvpex_intr_map, 170 mvpex_intr_string, 171 mvpex_intr_evcnt, 172 mvpex_intr_establish, 173 mvpex_intr_disestablish, 174 #ifdef __HAVE_PCI_CONF_HOOK 175 mvpex_conf_hook, 176 #endif 177 mvpex_conf_interrupt, 178 }; 179 struct arm32_pci_chipset arm32_mvpex3_chipset = { 180 NULL, /* conf_v */ 181 mvpex_attach_hook, 182 mvpex_bus_maxdevs, 183 mvpex_make_tag, 184 mvpex_decompose_tag, 185 #if NMVPEX_MBUS > 0 186 mvpex_mbus_conf_read, /* XXXX: always this functions */ 187 #else 188 mvpex_conf_read, 189 #endif 190 mvpex_conf_write, 191 NULL, /* intr_v */ 192 mvpex_intr_map, 193 mvpex_intr_string, 194 mvpex_intr_evcnt, 195 mvpex_intr_establish, 196 mvpex_intr_disestablish, 197 #ifdef __HAVE_PCI_CONF_HOOK 198 mvpex_conf_hook, 199 #endif 200 mvpex_conf_interrupt, 201 }; 202 struct arm32_pci_chipset arm32_mvpex4_chipset = { 203 NULL, /* conf_v */ 204 mvpex_attach_hook, 205 mvpex_bus_maxdevs, 206 mvpex_make_tag, 207 mvpex_decompose_tag, 208 #if NMVPEX_MBUS > 0 209 mvpex_mbus_conf_read, /* XXXX: always this functions */ 210 #else 211 mvpex_conf_read, 212 #endif 213 mvpex_conf_write, 214 NULL, /* intr_v */ 215 mvpex_intr_map, 216 mvpex_intr_string, 217 mvpex_intr_evcnt, 218 mvpex_intr_establish, 219 mvpex_intr_disestablish, 220 #ifdef __HAVE_PCI_CONF_HOOK 221 mvpex_conf_hook, 222 #endif 223 mvpex_conf_interrupt, 224 }; 225 struct arm32_pci_chipset arm32_mvpex5_chipset = { 226 NULL, /* conf_v */ 227 mvpex_attach_hook, 228 mvpex_bus_maxdevs, 229 mvpex_make_tag, 230 mvpex_decompose_tag, 231 #if NMVPEX_MBUS > 0 232 mvpex_mbus_conf_read, /* XXXX: always this functions */ 233 #else 234 mvpex_conf_read, 235 #endif 236 mvpex_conf_write, 237 NULL, /* intr_v */ 238 mvpex_intr_map, 239 mvpex_intr_string, 240 mvpex_intr_evcnt, 241 mvpex_intr_establish, 242 mvpex_intr_disestablish, 243 #ifdef __HAVE_PCI_CONF_HOOK 244 mvpex_conf_hook, 245 #endif 246 mvpex_conf_interrupt, 247 }; 248 struct arm32_pci_chipset arm32_mvpex6_chipset = { 249 NULL, /* conf_v */ 250 mvpex_attach_hook, 251 mvpex_bus_maxdevs, 252 mvpex_make_tag, 253 mvpex_decompose_tag, 254 #if NMVPEX_MBUS > 0 255 mvpex_mbus_conf_read, /* XXXX: always this functions */ 256 #else 257 mvpex_conf_read, 258 #endif 259 mvpex_conf_write, 260 NULL, /* intr_v */ 261 mvpex_intr_map, 262 mvpex_intr_string, 263 mvpex_intr_evcnt, 264 mvpex_intr_establish, 265 mvpex_intr_disestablish, 266 #ifdef __HAVE_PCI_CONF_HOOK 267 mvpex_conf_hook, 268 #endif 269 mvpex_conf_interrupt, 270 }; 271 #endif /* NMVPEX > 0 */ 272 273 #if NGTPCI > 0 274 /* ARGSUSED */ 275 void 276 gtpci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, int *iline) 277 { 278 279 /* nothing */ 280 } 281 282 #if NGTPCI_MBUS > 0 283 #define GTPCI_MBUS_CA 0x0c78 /* Configuration Address */ 284 #define GTPCI_MBUS_CD 0x0c7c /* Configuration Data */ 285 286 static pcireg_t 287 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg) 288 { 289 struct gtpci_softc *sc = v; 290 const pcireg_t addr = tag | reg; 291 292 if ((unsigned int)reg >= PCI_CONF_SIZE) 293 return -1; 294 295 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 296 addr | GTPCI_CA_CONFIGEN); 297 if ((addr | GTPCI_CA_CONFIGEN) != 298 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 299 return -1; 300 301 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD); 302 } 303 304 static void 305 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 306 { 307 struct gtpci_softc *sc = v; 308 pcireg_t addr = tag | (reg & 0xfc); 309 310 if ((unsigned int)reg >= PCI_CONF_SIZE) 311 return; 312 313 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 314 addr | GTPCI_CA_CONFIGEN); 315 if ((addr | GTPCI_CA_CONFIGEN) != 316 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 317 return; 318 319 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data); 320 } 321 #endif /* NGTPCI_MBUS */ 322 323 /* 324 * We assume to use GPP interrupt as PCI interrupts. 325 * pci_intr_map() shall returns number of GPP between 0 and 31. However 326 * returns 0xff, because we do not know the connected pin number for GPP 327 * of your board. 328 * pci_intr_string() shall returns string "gpp <num>". 329 * pci_intr_establish() established interrupt in the pin of all GPP. 330 * Moreover, the return value will be disregarded. For instance, the 331 * setting for interrupt is not done. 332 */ 333 334 /* ARGSUSED */ 335 static int 336 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 337 { 338 339 *ihp = pa->pa_intrpin; 340 return 0; 341 } 342 343 /* ARGSUSED */ 344 static const char * 345 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin, char *buf, size_t len) 346 { 347 struct gtpci_softc *sc = v; 348 prop_array_t int2gpp; 349 prop_object_t gpp; 350 351 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 352 gpp = prop_array_get(int2gpp, pin); 353 snprintf(buf, len, "gpp %d", (int)prop_number_integer_value(gpp)); 354 355 return buf; 356 } 357 358 /* ARGSUSED */ 359 static const struct evcnt * 360 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin) 361 { 362 363 return NULL; 364 } 365 366 static void * 367 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl, 368 int (*intrhand)(void *), void *intrarg) 369 { 370 struct gtpci_softc *sc = v; 371 prop_array_t int2gpp; 372 prop_object_t gpp; 373 int gpp_pin; 374 375 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 376 gpp = prop_array_get(int2gpp, int_pin); 377 gpp_pin = prop_number_integer_value(gpp); 378 return mvsocgpp_intr_establish(gpp_pin, ipl, IST_LEVEL_LOW, intrhand, 379 intrarg); 380 } 381 382 static void 383 gtpci_gpp_intr_disestablish(void *v, void *ih) 384 { 385 386 mvsocgpp_intr_disestablish(ih); 387 } 388 #endif 389 390 #if NMVPEX_MBUS > 0 391 /* ARGSUSED */ 392 void 393 mvpex_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 394 { 395 396 /* nothing */ 397 } 398 399 static pcireg_t 400 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg) 401 { 402 struct mvpex_softc *sc = v; 403 pcireg_t addr, data, pci_cs; 404 uint32_t stat; 405 int bus, dev, func, pexbus, pexdev; 406 407 if ((unsigned int)reg >= PCI_CONF_SIZE) 408 return -1; 409 410 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 411 412 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 413 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 414 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 415 if (bus != pexbus || dev != pexdev) 416 if (stat & MVPEX_STAT_DLDOWN) 417 return -1; 418 419 if (bus == pexbus) { 420 if (pexdev == 0) { 421 if (dev != 1 && dev != pexdev) 422 return -1; 423 } else { 424 if (dev != 0 && dev != pexdev) 425 return -1; 426 } 427 if (func != 0) 428 return -1; 429 } 430 431 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 432 433 #if defined(ORION) 434 /* 435 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration 436 * This guideline is relevant for all devices except of the following 437 * devices: 438 * 88F5281-BO and above, and 88F5181L-A0 and above 439 */ 440 if ((bus != pexbus || dev != pexdev) && 441 !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) && 442 !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) { 443 444 /* PCI-Express configuration read work-around */ 445 /* 446 * We will use one of the Punit (AHBToMbus) windows to 447 * access the xbar and read the data from there 448 * 449 * Need to configure the 2 free Punit (AHB to MBus bridge) 450 * address decoding windows: 451 * Configure the flash Window to handle Configuration space 452 * requests for PEX0/1: 453 * 454 * Configuration transactions from the CPU should write/read 455 * the data to/from address of the form: 456 * addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1) 457 * addr[27:24]: extended register number 458 * addr[23:16]: bus number 459 * addr[15:11]: device number 460 * addr[10: 8]: function number 461 * addr[ 7: 0]: register number 462 */ 463 464 struct mvsoc_softc *soc = 465 device_private(device_parent(sc->sc_dev));; 466 bus_space_handle_t pcicfg_ioh; 467 uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size; 468 int window, target, attr, base, size, s; 469 const int pex_pcicfg_tag = 470 (sc->sc_model == MARVELL_ORION_1_88F1181) ? 471 ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM; 472 473 window = mvsoc_target(pex_pcicfg_tag, 474 &target, &attr, &base, &size); 475 if (window >= nwindow) { 476 aprint_error_dev(sc->sc_dev, 477 "can't read pcicfg space\n"); 478 return -1; 479 } 480 481 s = splhigh(); 482 483 remapl = remaph = 0; 484 if (window == 0 || window == 1) { 485 remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window)); 486 remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window)); 487 } 488 489 wc = 490 MVSOC_MLMB_WCR_WINEN | 491 MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG) | 492 MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16); 493 if (sc->sc_model == MARVELL_ORION_1_88F1181) { 494 pcicfg_addr = base; 495 pcicfg_size = size; 496 } else if (sc->sc_model == MARVELL_ORION_1_88F5182) { 497 #define PEX_PCICFG_RW_WA_BASE 0x50000000 498 #define PEX_PCICFG_RW_WA_5182_BASE 0xf0000000 499 #define PEX_PCICFG_RW_WA_SIZE (16 * 1024 * 1024) 500 pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE; 501 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 502 } else { 503 pcicfg_addr = PEX_PCICFG_RW_WA_BASE; 504 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 505 } 506 write_mlmbreg(MVSOC_MLMB_WCR(window), 507 wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size)); 508 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr); 509 510 if (window == 0 || window == 1) { 511 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr); 512 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 513 } 514 515 if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0, 516 &pcicfg_ioh) == 0) { 517 data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr); 518 bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size); 519 } else 520 data = -1; 521 522 write_mlmbreg(MVSOC_MLMB_WCR(window), 523 MVSOC_MLMB_WCR_WINEN | 524 MVSOC_MLMB_WCR_ATTR(attr) | 525 MVSOC_MLMB_WCR_TARGET(target) | 526 MVSOC_MLMB_WCR_SIZE(size)); 527 write_mlmbreg(MVSOC_MLMB_WBR(window), base); 528 if (window == 0 || window == 1) { 529 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl); 530 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph); 531 } 532 533 splx(s); 534 #else 535 if (0) { 536 #endif 537 } else { 538 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 539 addr | MVPEX_CA_CONFIGEN); 540 if ((addr | MVPEX_CA_CONFIGEN) != 541 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 542 return -1; 543 544 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 545 PCI_COMMAND_STATUS_REG); 546 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 547 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 548 549 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 550 } 551 552 return data; 553 } 554 #endif 555
Indexes created Mon Sep 29 18:09:42 GMT 2025