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pci_machdep.c revision 1.4 
      1 /*	$NetBSD: pci_machdep.c,v 1.4 2012/09/07 04:25:36 matt Exp $	*/
      2 /*
      3  * Copyright (c) 2008 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.4 2012/09/07 04:25:36 matt Exp $");
     30 
     31 #include "opt_mvsoc.h"
     32 #include "gtpci.h"
     33 #include "mvpex.h"
     34 #include "pci.h"
     35 
     36 #include <sys/param.h>
     37 #include <sys/device.h>
     38 #include <sys/extent.h>
     39 
     40 #include <dev/pci/pcivar.h>
     41 #include <dev/pci/pciconf.h>
     42 
     43 #include <arm/marvell/mvsocreg.h>
     44 #include <arm/marvell/mvsocvar.h>
     45 #include <arm/marvell/mvsocgppvar.h>
     46 #if NGTPCI > 0
     47 #include <dev/marvell/gtpcireg.h>
     48 #include <dev/marvell/gtpcivar.h>
     49 #endif
     50 #if NMVPEX > 0
     51 #include <dev/marvell/mvpexreg.h>
     52 #include <dev/marvell/mvpexvar.h>
     53 #endif
     54 
     55 #include <machine/pci_machdep.h>
     56 
     57 #if defined(ORION)
     58 #include <arm/marvell/orionreg.h>
     59 #endif
     60 #if defined(KIRKWOOD)
     61 #include <arm/marvell/kirkwoodreg.h>
     62 #endif
     63 #include <dev/marvell/marvellreg.h>
     64 
     65 
     66 #if NGTPCI > 0
     67 #if NGTPCI_MBUS > 0
     68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int);
     69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t);
     70 #endif
     71 static int gtpci_gpp_intr_map(const struct pci_attach_args *,
     72     pci_intr_handle_t *);
     73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t);
     74 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t);
     75 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *);
     76 static void gtpci_gpp_intr_disestablish(void *, void *);
     77 
     78 struct arm32_pci_chipset arm32_gtpci_chipset = {
     79 	NULL,	/* conf_v */
     80 	gtpci_attach_hook,
     81 	gtpci_bus_maxdevs,
     82 	gtpci_make_tag,
     83 	gtpci_decompose_tag,
     84 #if NGTPCI_MBUS > 0
     85 	gtpci_mbus_conf_read,		/* XXXX: always this functions */
     86 	gtpci_mbus_conf_write,
     87 #else
     88 	gtpci_conf_read,
     89 	gtpci_conf_write,
     90 #endif
     91 	NULL,	/* intr_v */
     92 	gtpci_gpp_intr_map,
     93 	gtpci_gpp_intr_string,
     94 	gtpci_gpp_intr_evcnt,
     95 	gtpci_gpp_intr_establish,
     96 	gtpci_gpp_intr_disestablish,
     97 #ifdef __HAVE_PCI_CONF_HOOK
     98 	gtpci_conf_hook,
     99 #endif
    100 	gtpci_conf_interrupt,
    101 };
    102 #endif
    103 
    104 #if NMVPEX > 0
    105 #if NMVPEX_MBUS > 0
    106 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int);
    107 #endif
    108 
    109 struct arm32_pci_chipset arm32_mvpex0_chipset = {
    110 	NULL,	/* conf_v */
    111 	mvpex_attach_hook,
    112 	mvpex_bus_maxdevs,
    113 	mvpex_make_tag,
    114 	mvpex_decompose_tag,
    115 #if NMVPEX_MBUS > 0
    116 	mvpex_mbus_conf_read,		/* XXXX: always this functions */
    117 #else
    118 	mvpex_conf_read,
    119 #endif
    120 	mvpex_conf_write,
    121 	NULL,	/* intr_v */
    122 	mvpex_intr_map,
    123 	mvpex_intr_string,
    124 	mvpex_intr_evcnt,
    125 	mvpex_intr_establish,
    126 	mvpex_intr_disestablish,
    127 #ifdef __HAVE_PCI_CONF_HOOK
    128 	mvpex_conf_hook,
    129 #endif
    130 };
    131 struct arm32_pci_chipset arm32_mvpex1_chipset = {
    132 	NULL,	/* conf_v */
    133 	mvpex_attach_hook,
    134 	mvpex_bus_maxdevs,
    135 	mvpex_make_tag,
    136 	mvpex_decompose_tag,
    137 #if NMVPEX_MBUS > 0
    138 	mvpex_mbus_conf_read,		/* XXXX: always this functions */
    139 #else
    140 	mvpex_conf_read,
    141 #endif
    142 	mvpex_conf_write,
    143 	NULL,	/* intr_v */
    144 	mvpex_intr_map,
    145 	mvpex_intr_string,
    146 	mvpex_intr_evcnt,
    147 	mvpex_intr_establish,
    148 	mvpex_intr_disestablish,
    149 #ifdef __HAVE_PCI_CONF_HOOK
    150 	mvpex_conf_hook,
    151 #endif
    152 	mvpex_conf_interrupt,
    153 };
    154 #endif
    155 
    156 
    157 #if NGTPCI > 0
    158 /* ARGSUSED */
    159 void
    160 gtpci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, int *iline)
    161 {
    162 
    163 	/* nothing */
    164 }
    165 
    166 #if NGTPCI_MBUS > 0
    167 #define GTPCI_MBUS_CA		0x0c78	/* Configuration Address */
    168 #define GTPCI_MBUS_CD		0x0c7c	/* Configuration Data */
    169 
    170 static pcireg_t
    171 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg)
    172 {
    173 	struct gtpci_softc *sc = v;
    174 	const pcireg_t addr = tag | reg;
    175 
    176 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
    177 	    addr | GTPCI_CA_CONFIGEN);
    178 	if ((addr | GTPCI_CA_CONFIGEN) !=
    179 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
    180 		return -1;
    181 
    182 	return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD);
    183 }
    184 
    185 static void
    186 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
    187 {
    188 	struct gtpci_softc *sc = v;
    189 	pcireg_t addr = tag | (reg & 0xfc);
    190 
    191 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
    192 	    addr | GTPCI_CA_CONFIGEN);
    193 	if ((addr | GTPCI_CA_CONFIGEN) !=
    194 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
    195 		return;
    196 
    197 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data);
    198 }
    199 #endif	/* NGTPCI_MBUS */
    200 
    201 /*
    202  * We assume to use GPP interrupt as PCI interrupts.
    203  *   pci_intr_map() shall returns number of GPP between 0 and 31.  However
    204  *   returns 0xff, because we do not know the connected pin number for GPP
    205  *   of your board.
    206  *   pci_intr_string() shall returns string "gpp <num>".
    207  *   pci_intr_establish() established interrupt in the pin of all GPP.
    208  *   Moreover, the return value will be disregarded.  For instance, the
    209  *   setting for interrupt is not done.
    210  */
    211 
    212 /* ARGSUSED */
    213 static int
    214 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    215 {
    216 
    217 	*ihp = pa->pa_intrpin;
    218 	return 0;
    219 }
    220 
    221 /* ARGSUSED */
    222 static const char *
    223 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin)
    224 {
    225 	struct gtpci_softc *sc = v;
    226 	prop_array_t int2gpp;
    227 	prop_object_t gpp;
    228 	static char intrstr[8];
    229 
    230 	int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
    231 	gpp = prop_array_get(int2gpp, pin);
    232 	sprintf(intrstr, "gpp %d", (int)prop_number_integer_value(gpp));
    233 
    234 	return intrstr;
    235 }
    236 
    237 /* ARGSUSED */
    238 static const struct evcnt *
    239 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin)
    240 {
    241 
    242 	return NULL;
    243 }
    244 
    245 static void *
    246 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl,
    247 		         int (*intrhand)(void *), void *intrarg)
    248 {
    249 	struct gtpci_softc *sc = v;
    250 	prop_array_t int2gpp;
    251 	prop_object_t gpp;
    252 	int gpp_pin;
    253 
    254 	int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
    255 	gpp = prop_array_get(int2gpp, int_pin);
    256 	gpp_pin = prop_number_integer_value(gpp);
    257 	return mvsocgpp_intr_establish(gpp_pin, ipl, 0, intrhand, intrarg);
    258 }
    259 
    260 static void
    261 gtpci_gpp_intr_disestablish(void *v, void *ih)
    262 {
    263 
    264 	mvsocgpp_intr_disestablish(ih);
    265 }
    266 #endif
    267 
    268 #if NMVPEX_MBUS > 0
    269 /* ARGSUSED */
    270 void
    271 mvpex_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep)
    272 {
    273 
    274 	/* nothing */
    275 }
    276 
    277 static pcireg_t
    278 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg)
    279 {
    280 	struct mvpex_softc *sc = v;
    281 	pcireg_t addr, data, pci_cs;
    282 	uint32_t stat;
    283 	int bus, dev, func, pexbus, pexdev;
    284 
    285 	mvpex_decompose_tag(v, tag, &bus, &dev, &func);
    286 
    287 	stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
    288 	pexbus = MVPEX_STAT_PEXBUSNUM(stat);
    289 	pexdev = MVPEX_STAT_PEXDEVNUM(stat);
    290 	if (bus != pexbus || dev != pexdev)
    291 		if (stat & MVPEX_STAT_DLDOWN)
    292 			return -1;
    293 
    294 	if (bus == pexbus) {
    295 		if (pexdev == 0) {
    296 			if (dev != 1 && dev != pexdev)
    297 				return -1;
    298 		} else {
    299 			if (dev != 0 && dev != pexdev)
    300 				return -1;
    301 		}
    302 		if (func != 0)
    303 			return -1;
    304 	}
    305 
    306 	addr = ((reg & 0xf00) << 24)  | tag | (reg & 0xfc);
    307 
    308 #if defined(ORION)
    309 	/*
    310 	 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration
    311 	 * This guideline is relevant for all devices except of the following
    312 	 * devices:
    313 	 *     88F5281-BO and above, and 88F5181L-A0 and above
    314 	 */
    315 	if ((bus != pexbus || dev != pexdev) &&
    316 	    !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) &&
    317 	    !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) {
    318 
    319 		/* PCI-Express configuration read work-around */
    320 		/*
    321 		 * We will use one of the Punit (AHBToMbus) windows to
    322 		 * access the xbar and read the data from there
    323 		 *
    324 		 * Need to configure the 2 free Punit (AHB to MBus bridge)
    325 		 * address decoding windows:
    326 		 * Configure the flash Window to handle Configuration space
    327 		 * requests for PEX0/1:
    328 		 *
    329 		 * Configuration transactions from the CPU should write/read
    330 		 * the data to/from address of the form:
    331 		 *	addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1)
    332 		 *	addr[27:24]: extended register number
    333 		 *	addr[23:16]: bus number
    334 		 *	addr[15:11]: device number
    335 		 *	addr[10: 8]: function number
    336 		 *	addr[ 7: 0]: register number
    337 		 */
    338 
    339 		struct mvsoc_softc *soc =
    340 		    device_private(device_parent(sc->sc_dev));;
    341 		bus_space_handle_t pcicfg_ioh;
    342 		uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size;
    343 		int window, target, attr, base, size, s;
    344 		const int pex_pcicfg_tag =
    345 		    (sc->sc_model == MARVELL_ORION_1_88F1181) ?
    346 		    ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM;
    347 
    348 		window = mvsoc_target(pex_pcicfg_tag,
    349 		    &target, &attr, &base, &size);
    350 		if (window >= nwindow) {
    351 			aprint_error_dev(sc->sc_dev,
    352 			    "can't read pcicfg space\n");
    353 			return -1;
    354 		}
    355 
    356 		s = splhigh();
    357 
    358 		remapl = remaph = 0;
    359 		if (window == 0 || window == 1) {
    360 			remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window));
    361 			remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window));
    362 		}
    363 
    364 		wc =
    365 		    MVSOC_MLMB_WCR_WINEN			|
    366 		    MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG)	|
    367 		    MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16);
    368 		if (sc->sc_model == MARVELL_ORION_1_88F1181) {
    369 			pcicfg_addr = base;
    370 			pcicfg_size = size;
    371 		} else if (sc->sc_model == MARVELL_ORION_1_88F5182) {
    372 #define PEX_PCICFG_RW_WA_BASE		0x50000000
    373 #define PEX_PCICFG_RW_WA_5182_BASE	0xf0000000
    374 #define PEX_PCICFG_RW_WA_SIZE		(16 * 1024 * 1024)
    375 			pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE;
    376 			pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
    377 		} else {
    378 			pcicfg_addr = PEX_PCICFG_RW_WA_BASE;
    379 			pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
    380 		}
    381 		write_mlmbreg(MVSOC_MLMB_WCR(window),
    382 		    wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size));
    383 		write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr);
    384 
    385 		if (window == 0 || window == 1) {
    386 			write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr);
    387 			write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
    388 		}
    389 
    390 		if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0,
    391 		    &pcicfg_ioh) == 0) {
    392 			data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr);
    393 			bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size);
    394 		} else
    395 			data = -1;
    396 
    397 		write_mlmbreg(MVSOC_MLMB_WCR(window),
    398 		    MVSOC_MLMB_WCR_WINEN		|
    399 		    MVSOC_MLMB_WCR_ATTR(attr)		|
    400 		    MVSOC_MLMB_WCR_TARGET(target)	|
    401 		    MVSOC_MLMB_WCR_SIZE(size));
    402 		write_mlmbreg(MVSOC_MLMB_WBR(window), base);
    403 		if (window == 0 || window == 1) {
    404 			write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl);
    405 			write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph);
    406 		}
    407 
    408 		splx(s);
    409 #else
    410 	if (0) {
    411 #endif
    412 	} else {
    413 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA,
    414 		    addr | MVPEX_CA_CONFIGEN);
    415 		if ((addr | MVPEX_CA_CONFIGEN) !=
    416 		    bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA))
    417 			return -1;
    418 
    419 		pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
    420 		    PCI_COMMAND_STATUS_REG);
    421 		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
    422 		    PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT);
    423 
    424 		data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD);
    425 	}
    426 
    427 	return data;
    428 }
    429 #endif
    430