pci_machdep.c revision 1.5
1 /* $NetBSD: pci_machdep.c,v 1.5 2013/05/01 12:38:06 rkujawa Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.5 2013/05/01 12:38:06 rkujawa Exp $"); 30 31 #include "opt_mvsoc.h" 32 #include "gtpci.h" 33 #include "mvpex.h" 34 #include "pci.h" 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pciconf.h> 42 43 #include <arm/marvell/mvsocreg.h> 44 #include <arm/marvell/mvsocvar.h> 45 #include <arm/marvell/mvsocgppvar.h> 46 #if NGTPCI > 0 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #endif 50 #if NMVPEX > 0 51 #include <dev/marvell/mvpexreg.h> 52 #include <dev/marvell/mvpexvar.h> 53 #endif 54 55 #include <machine/pci_machdep.h> 56 57 #if defined(ORION) 58 #include <arm/marvell/orionreg.h> 59 #endif 60 #if defined(KIRKWOOD) 61 #include <arm/marvell/kirkwoodreg.h> 62 #endif 63 #include <dev/marvell/marvellreg.h> 64 65 66 #if NGTPCI > 0 67 #if NGTPCI_MBUS > 0 68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int); 69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t); 70 #endif 71 static int gtpci_gpp_intr_map(const struct pci_attach_args *, 72 pci_intr_handle_t *); 73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t); 74 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t); 75 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *); 76 static void gtpci_gpp_intr_disestablish(void *, void *); 77 78 struct arm32_pci_chipset arm32_gtpci_chipset = { 79 NULL, /* conf_v */ 80 gtpci_attach_hook, 81 gtpci_bus_maxdevs, 82 gtpci_make_tag, 83 gtpci_decompose_tag, 84 #if NGTPCI_MBUS > 0 85 gtpci_mbus_conf_read, /* XXXX: always this functions */ 86 gtpci_mbus_conf_write, 87 #else 88 gtpci_conf_read, 89 gtpci_conf_write, 90 #endif 91 NULL, /* intr_v */ 92 gtpci_gpp_intr_map, 93 gtpci_gpp_intr_string, 94 gtpci_gpp_intr_evcnt, 95 gtpci_gpp_intr_establish, 96 gtpci_gpp_intr_disestablish, 97 #ifdef __HAVE_PCI_CONF_HOOK 98 gtpci_conf_hook, 99 #endif 100 gtpci_conf_interrupt, 101 }; 102 #endif 103 104 #if NMVPEX > 0 105 #if NMVPEX_MBUS > 0 106 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int); 107 #endif 108 109 struct arm32_pci_chipset arm32_mvpex0_chipset = { 110 NULL, /* conf_v */ 111 mvpex_attach_hook, 112 mvpex_bus_maxdevs, 113 mvpex_make_tag, 114 mvpex_decompose_tag, 115 #if NMVPEX_MBUS > 0 116 mvpex_mbus_conf_read, /* XXXX: always this functions */ 117 #else 118 mvpex_conf_read, 119 #endif 120 mvpex_conf_write, 121 NULL, /* intr_v */ 122 mvpex_intr_map, 123 mvpex_intr_string, 124 mvpex_intr_evcnt, 125 mvpex_intr_establish, 126 mvpex_intr_disestablish, 127 #ifdef __HAVE_PCI_CONF_HOOK 128 mvpex_conf_hook, 129 #endif 130 mvpex_conf_interrupt, 131 }; 132 struct arm32_pci_chipset arm32_mvpex1_chipset = { 133 NULL, /* conf_v */ 134 mvpex_attach_hook, 135 mvpex_bus_maxdevs, 136 mvpex_make_tag, 137 mvpex_decompose_tag, 138 #if NMVPEX_MBUS > 0 139 mvpex_mbus_conf_read, /* XXXX: always this functions */ 140 #else 141 mvpex_conf_read, 142 #endif 143 mvpex_conf_write, 144 NULL, /* intr_v */ 145 mvpex_intr_map, 146 mvpex_intr_string, 147 mvpex_intr_evcnt, 148 mvpex_intr_establish, 149 mvpex_intr_disestablish, 150 #ifdef __HAVE_PCI_CONF_HOOK 151 mvpex_conf_hook, 152 #endif 153 mvpex_conf_interrupt, 154 }; 155 struct arm32_pci_chipset arm32_mvpex2_chipset = { 156 NULL, /* conf_v */ 157 mvpex_attach_hook, 158 mvpex_bus_maxdevs, 159 mvpex_make_tag, 160 mvpex_decompose_tag, 161 #if NMVPEX_MBUS > 0 162 mvpex_mbus_conf_read, /* XXXX: always this functions */ 163 #else 164 mvpex_conf_read, 165 #endif 166 mvpex_conf_write, 167 NULL, /* intr_v */ 168 mvpex_intr_map, 169 mvpex_intr_string, 170 mvpex_intr_evcnt, 171 mvpex_intr_establish, 172 mvpex_intr_disestablish, 173 #ifdef __HAVE_PCI_CONF_HOOK 174 mvpex_conf_hook, 175 #endif 176 mvpex_conf_interrupt, 177 }; 178 struct arm32_pci_chipset arm32_mvpex3_chipset = { 179 NULL, /* conf_v */ 180 mvpex_attach_hook, 181 mvpex_bus_maxdevs, 182 mvpex_make_tag, 183 mvpex_decompose_tag, 184 #if NMVPEX_MBUS > 0 185 mvpex_mbus_conf_read, /* XXXX: always this functions */ 186 #else 187 mvpex_conf_read, 188 #endif 189 mvpex_conf_write, 190 NULL, /* intr_v */ 191 mvpex_intr_map, 192 mvpex_intr_string, 193 mvpex_intr_evcnt, 194 mvpex_intr_establish, 195 mvpex_intr_disestablish, 196 #ifdef __HAVE_PCI_CONF_HOOK 197 mvpex_conf_hook, 198 #endif 199 mvpex_conf_interrupt, 200 }; 201 struct arm32_pci_chipset arm32_mvpex4_chipset = { 202 NULL, /* conf_v */ 203 mvpex_attach_hook, 204 mvpex_bus_maxdevs, 205 mvpex_make_tag, 206 mvpex_decompose_tag, 207 #if NMVPEX_MBUS > 0 208 mvpex_mbus_conf_read, /* XXXX: always this functions */ 209 #else 210 mvpex_conf_read, 211 #endif 212 mvpex_conf_write, 213 NULL, /* intr_v */ 214 mvpex_intr_map, 215 mvpex_intr_string, 216 mvpex_intr_evcnt, 217 mvpex_intr_establish, 218 mvpex_intr_disestablish, 219 #ifdef __HAVE_PCI_CONF_HOOK 220 mvpex_conf_hook, 221 #endif 222 mvpex_conf_interrupt, 223 }; 224 struct arm32_pci_chipset arm32_mvpex5_chipset = { 225 NULL, /* conf_v */ 226 mvpex_attach_hook, 227 mvpex_bus_maxdevs, 228 mvpex_make_tag, 229 mvpex_decompose_tag, 230 #if NMVPEX_MBUS > 0 231 mvpex_mbus_conf_read, /* XXXX: always this functions */ 232 #else 233 mvpex_conf_read, 234 #endif 235 mvpex_conf_write, 236 NULL, /* intr_v */ 237 mvpex_intr_map, 238 mvpex_intr_string, 239 mvpex_intr_evcnt, 240 mvpex_intr_establish, 241 mvpex_intr_disestablish, 242 #ifdef __HAVE_PCI_CONF_HOOK 243 mvpex_conf_hook, 244 #endif 245 mvpex_conf_interrupt, 246 }; 247 #endif /* NMVPEX > 0 */ 248 249 #if NGTPCI > 0 250 /* ARGSUSED */ 251 void 252 gtpci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, int *iline) 253 { 254 255 /* nothing */ 256 } 257 258 #if NGTPCI_MBUS > 0 259 #define GTPCI_MBUS_CA 0x0c78 /* Configuration Address */ 260 #define GTPCI_MBUS_CD 0x0c7c /* Configuration Data */ 261 262 static pcireg_t 263 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg) 264 { 265 struct gtpci_softc *sc = v; 266 const pcireg_t addr = tag | reg; 267 268 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 269 addr | GTPCI_CA_CONFIGEN); 270 if ((addr | GTPCI_CA_CONFIGEN) != 271 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 272 return -1; 273 274 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD); 275 } 276 277 static void 278 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 279 { 280 struct gtpci_softc *sc = v; 281 pcireg_t addr = tag | (reg & 0xfc); 282 283 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA, 284 addr | GTPCI_CA_CONFIGEN); 285 if ((addr | GTPCI_CA_CONFIGEN) != 286 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA)) 287 return; 288 289 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data); 290 } 291 #endif /* NGTPCI_MBUS */ 292 293 /* 294 * We assume to use GPP interrupt as PCI interrupts. 295 * pci_intr_map() shall returns number of GPP between 0 and 31. However 296 * returns 0xff, because we do not know the connected pin number for GPP 297 * of your board. 298 * pci_intr_string() shall returns string "gpp <num>". 299 * pci_intr_establish() established interrupt in the pin of all GPP. 300 * Moreover, the return value will be disregarded. For instance, the 301 * setting for interrupt is not done. 302 */ 303 304 /* ARGSUSED */ 305 static int 306 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 307 { 308 309 *ihp = pa->pa_intrpin; 310 return 0; 311 } 312 313 /* ARGSUSED */ 314 static const char * 315 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin) 316 { 317 struct gtpci_softc *sc = v; 318 prop_array_t int2gpp; 319 prop_object_t gpp; 320 static char intrstr[8]; 321 322 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 323 gpp = prop_array_get(int2gpp, pin); 324 sprintf(intrstr, "gpp %d", (int)prop_number_integer_value(gpp)); 325 326 return intrstr; 327 } 328 329 /* ARGSUSED */ 330 static const struct evcnt * 331 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin) 332 { 333 334 return NULL; 335 } 336 337 static void * 338 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl, 339 int (*intrhand)(void *), void *intrarg) 340 { 341 struct gtpci_softc *sc = v; 342 prop_array_t int2gpp; 343 prop_object_t gpp; 344 int gpp_pin; 345 346 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp"); 347 gpp = prop_array_get(int2gpp, int_pin); 348 gpp_pin = prop_number_integer_value(gpp); 349 return mvsocgpp_intr_establish(gpp_pin, ipl, 0, intrhand, intrarg); 350 } 351 352 static void 353 gtpci_gpp_intr_disestablish(void *v, void *ih) 354 { 355 356 mvsocgpp_intr_disestablish(ih); 357 } 358 #endif 359 360 #if NMVPEX_MBUS > 0 361 /* ARGSUSED */ 362 void 363 mvpex_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 364 { 365 366 /* nothing */ 367 } 368 369 static pcireg_t 370 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg) 371 { 372 struct mvpex_softc *sc = v; 373 pcireg_t addr, data, pci_cs; 374 uint32_t stat; 375 int bus, dev, func, pexbus, pexdev; 376 377 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 378 379 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 380 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 381 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 382 if (bus != pexbus || dev != pexdev) 383 if (stat & MVPEX_STAT_DLDOWN) 384 return -1; 385 386 if (bus == pexbus) { 387 if (pexdev == 0) { 388 if (dev != 1 && dev != pexdev) 389 return -1; 390 } else { 391 if (dev != 0 && dev != pexdev) 392 return -1; 393 } 394 if (func != 0) 395 return -1; 396 } 397 398 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 399 400 #if defined(ORION) 401 /* 402 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration 403 * This guideline is relevant for all devices except of the following 404 * devices: 405 * 88F5281-BO and above, and 88F5181L-A0 and above 406 */ 407 if ((bus != pexbus || dev != pexdev) && 408 !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) && 409 !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) { 410 411 /* PCI-Express configuration read work-around */ 412 /* 413 * We will use one of the Punit (AHBToMbus) windows to 414 * access the xbar and read the data from there 415 * 416 * Need to configure the 2 free Punit (AHB to MBus bridge) 417 * address decoding windows: 418 * Configure the flash Window to handle Configuration space 419 * requests for PEX0/1: 420 * 421 * Configuration transactions from the CPU should write/read 422 * the data to/from address of the form: 423 * addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1) 424 * addr[27:24]: extended register number 425 * addr[23:16]: bus number 426 * addr[15:11]: device number 427 * addr[10: 8]: function number 428 * addr[ 7: 0]: register number 429 */ 430 431 struct mvsoc_softc *soc = 432 device_private(device_parent(sc->sc_dev));; 433 bus_space_handle_t pcicfg_ioh; 434 uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size; 435 int window, target, attr, base, size, s; 436 const int pex_pcicfg_tag = 437 (sc->sc_model == MARVELL_ORION_1_88F1181) ? 438 ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM; 439 440 window = mvsoc_target(pex_pcicfg_tag, 441 &target, &attr, &base, &size); 442 if (window >= nwindow) { 443 aprint_error_dev(sc->sc_dev, 444 "can't read pcicfg space\n"); 445 return -1; 446 } 447 448 s = splhigh(); 449 450 remapl = remaph = 0; 451 if (window == 0 || window == 1) { 452 remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window)); 453 remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window)); 454 } 455 456 wc = 457 MVSOC_MLMB_WCR_WINEN | 458 MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG) | 459 MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16); 460 if (sc->sc_model == MARVELL_ORION_1_88F1181) { 461 pcicfg_addr = base; 462 pcicfg_size = size; 463 } else if (sc->sc_model == MARVELL_ORION_1_88F5182) { 464 #define PEX_PCICFG_RW_WA_BASE 0x50000000 465 #define PEX_PCICFG_RW_WA_5182_BASE 0xf0000000 466 #define PEX_PCICFG_RW_WA_SIZE (16 * 1024 * 1024) 467 pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE; 468 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 469 } else { 470 pcicfg_addr = PEX_PCICFG_RW_WA_BASE; 471 pcicfg_size = PEX_PCICFG_RW_WA_SIZE; 472 } 473 write_mlmbreg(MVSOC_MLMB_WCR(window), 474 wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size)); 475 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr); 476 477 if (window == 0 || window == 1) { 478 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr); 479 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 480 } 481 482 if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0, 483 &pcicfg_ioh) == 0) { 484 data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr); 485 bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size); 486 } else 487 data = -1; 488 489 write_mlmbreg(MVSOC_MLMB_WCR(window), 490 MVSOC_MLMB_WCR_WINEN | 491 MVSOC_MLMB_WCR_ATTR(attr) | 492 MVSOC_MLMB_WCR_TARGET(target) | 493 MVSOC_MLMB_WCR_SIZE(size)); 494 write_mlmbreg(MVSOC_MLMB_WBR(window), base); 495 if (window == 0 || window == 1) { 496 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl); 497 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph); 498 } 499 500 splx(s); 501 #else 502 if (0) { 503 #endif 504 } else { 505 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 506 addr | MVPEX_CA_CONFIGEN); 507 if ((addr | MVPEX_CA_CONFIGEN) != 508 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 509 return -1; 510 511 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 512 PCI_COMMAND_STATUS_REG); 513 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 514 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 515 516 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 517 } 518 519 return data; 520 } 521 #endif 522
Indexes created Sat Sep 27 22:09:54 GMT 2025