tegra124_car.c revision 1.1
1 /* $NetBSD: tegra124_car.c,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.1 2015/12/22 22:10:36 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra124_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra124_car_match(device_t, cfdata_t, void *); 54 static void tegra124_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra124_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 59 .decode = tegra124_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra124_car_clock_id { 64 u_int id; 65 const char *name; 66 } tegra124_car_clock_ids[] = { 67 { 3, "ispb" }, 68 { 4, "rtc" }, 69 { 5, "timer" }, 70 { 6, "uarta" }, 71 { 9, "sdmmc2" }, 72 { 11, "i2s1" }, 73 { 12, "i2c1" }, 74 { 14, "sdmmc1" }, 75 { 15, "sdmmc4" }, 76 { 17, "pwm" }, 77 { 18, "i2s2" }, 78 { 22, "usbd" }, 79 { 23, "isp" }, 80 { 26, "disp2" }, 81 { 27, "disp1" }, 82 { 28, "host1x" }, 83 { 29, "vcp" }, 84 { 30, "i2s0" }, 85 { 32, "mc" }, 86 { 34, "apbdma" }, 87 { 36, "kbc" }, 88 { 40, "kfuse" }, 89 { 41, "sbc1" }, 90 { 42, "nor" }, 91 { 44, "sbc2" }, 92 { 46, "sbc3" }, 93 { 47, "i2c5" }, 94 { 48, "dsia" }, 95 { 50, "mipi" }, 96 { 51, "hdmi" }, 97 { 52, "csi" }, 98 { 54, "i2c2" }, 99 { 55, "uartc" }, 100 { 56, "mipi_cal" }, 101 { 57, "emc" }, 102 { 58, "usb2" }, 103 { 59, "usb3" }, 104 { 61, "vde" }, 105 { 62, "bsea" }, 106 { 63, "bsev" }, 107 { 65, "uartd" }, 108 { 67, "i2c3" }, 109 { 68, "sbc4" }, 110 { 69, "sdmmc3" }, 111 { 70, "pcie" }, 112 { 71, "owr" }, 113 { 72, "afi" }, 114 { 73, "csite" }, 115 { 76, "la" }, 116 { 77, "trace" }, 117 { 78, "soc_therm" }, 118 { 79, "dtv" }, 119 { 81, "i2cslow" }, 120 { 82, "dsib" }, 121 { 83, "tsec" }, 122 { 89, "xusb_host" }, 123 { 91, "msenc" }, 124 { 92, "csus" }, 125 { 99, "mselect" }, 126 { 100, "tsensor" }, 127 { 101, "i2s3" }, 128 { 102, "i2s4" }, 129 { 103, "i2c4" }, 130 { 104, "sbc5" }, 131 { 105, "sbc6" }, 132 { 106, "d_audio" }, 133 { 107, "apbif" }, 134 { 108, "dam0" }, 135 { 109, "dam1" }, 136 { 110, "dam2" }, 137 { 111, "hda2codec_2x" }, 138 { 113, "audio0_2x" }, 139 { 114, "audio1_2x" }, 140 { 115, "audio2_2x" }, 141 { 116, "audio3_2x" }, 142 { 117, "audio4_2x" }, 143 { 118, "spdif_2x" }, 144 { 119, "actmon" }, 145 { 120, "extern1" }, 146 { 121, "extern2" }, 147 { 122, "extern3" }, 148 { 123, "sata_oob" }, 149 { 124, "sata" }, 150 { 125, "hda" }, 151 { 127, "se" }, 152 { 128, "hda2hdmi" }, 153 { 129, "sata_cold" }, 154 { 144, "cilab" }, 155 { 145, "cilcd" }, 156 { 146, "cile" }, 157 { 147, "dsialp" }, 158 { 148, "dsiblp" }, 159 { 149, "entropy" }, 160 { 150, "dds" }, 161 { 152, "dp2" }, 162 { 153, "amx" }, 163 { 154, "adx" }, 164 { 156, "xusb_ss" }, 165 { 166, "i2c6" }, 166 { 171, "vim2_clk" }, 167 { 176, "hdmi_audio" }, 168 { 177, "clk72mhz" }, 169 { 178, "vic03" }, 170 { 180, "adx1" }, 171 { 181, "dpaux" }, 172 { 182, "sor0" }, 173 { 184, "gpu" }, 174 { 185, "amx1" }, 175 { 192, "uartb" }, 176 { 193, "vfir" }, 177 { 194, "spdif_in" }, 178 { 195, "spdif_out" }, 179 { 196, "vi" }, 180 { 197, "vi_sensor" }, 181 { 198, "fuse" }, 182 { 199, "fuse_burn" }, 183 { 200, "clk_32k" }, 184 { 201, "clk_m" }, 185 { 202, "clk_m_div2" }, 186 { 203, "clk_m_div4" }, 187 { 204, "pll_ref" }, 188 { 205, "pll_c" }, 189 { 206, "pll_c_out1" }, 190 { 207, "pll_c2" }, 191 { 208, "pll_c3" }, 192 { 209, "pll_m" }, 193 { 210, "pll_m_out1" }, 194 { 211, "pll_p" }, 195 { 212, "pll_p_out1" }, 196 { 213, "pll_p_out2" }, 197 { 214, "pll_p_out3" }, 198 { 215, "pll_p_out4" }, 199 { 216, "pll_a" }, 200 { 217, "pll_a_out0" }, 201 { 218, "pll_d" }, 202 { 219, "pll_d_out0" }, 203 { 220, "pll_d2" }, 204 { 221, "pll_d2_out0" }, 205 { 222, "pll_u" }, 206 { 223, "pll_u_480m" }, 207 { 224, "pll_u_60m" }, 208 { 225, "pll_u_48m" }, 209 { 226, "pll_u_12m" }, 210 { 229, "pll_re_vco" }, 211 { 230, "pll_re_out" }, 212 { 231, "pll_e" }, 213 { 232, "spdif_in_sync" }, 214 { 233, "i2s0_sync" }, 215 { 234, "i2s1_sync" }, 216 { 235, "i2s2_sync" }, 217 { 236, "i2s3_sync" }, 218 { 237, "i2s4_sync" }, 219 { 238, "vimclk_sync" }, 220 { 239, "audio0" }, 221 { 240, "audio1" }, 222 { 241, "audio2" }, 223 { 242, "audio3" }, 224 { 243, "audio4" }, 225 { 244, "spdif" }, 226 { 245, "clk_out_1" }, 227 { 246, "clk_out_2" }, 228 { 247, "clk_out_3" }, 229 { 248, "blink" }, 230 { 252, "xusb_host_src" }, 231 { 253, "xusb_falcon_src" }, 232 { 254, "xusb_fs_src" }, 233 { 255, "xusb_ss_src" }, 234 { 256, "xusb_dev_src" }, 235 { 257, "xusb_dev" }, 236 { 258, "xusb_hs_src" }, 237 { 259, "sclk" }, 238 { 260, "hclk" }, 239 { 261, "pclk" }, 240 { 264, "dfll_ref" }, 241 { 265, "dfll_soc" }, 242 { 266, "vi_sensor2" }, 243 { 267, "pll_p_out5" }, 244 { 268, "cml0" }, 245 { 269, "cml1" }, 246 { 270, "pll_c4" }, 247 { 271, "pll_dp" }, 248 { 272, "pll_e_mux" }, 249 { 273, "pll_d_dsi_out" }, 250 { 300, "audio0_mux" }, 251 { 301, "audio1_mux" }, 252 { 302, "audio2_mux" }, 253 { 303, "audio3_mux" }, 254 { 304, "audio4_mux" }, 255 { 305, "spdif_mux" }, 256 { 306, "clk_out_1_mux" }, 257 { 307, "clk_out_2_mux" }, 258 { 308, "clk_out_3_mux" }, 259 { 311, "sor0_lvds" }, 260 { 312, "xusb_ss_div2" }, 261 { 313, "pll_m_ud" }, 262 { 314, "pll_c_ud" }, 263 { 227, "pll_x" }, 264 { 228, "pll_x_out0" }, 265 { 262, "cclk_g" }, 266 { 263, "cclk_lp" }, 267 { 315, "clk_max" }, 268 }; 269 270 static struct clk *tegra124_car_clock_get(void *, const char *); 271 static void tegra124_car_clock_put(void *, struct clk *); 272 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 273 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 274 static int tegra124_car_clock_enable(void *, struct clk *); 275 static int tegra124_car_clock_disable(void *, struct clk *); 276 static int tegra124_car_clock_set_parent(void *, struct clk *, 277 struct clk *); 278 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 279 280 static const struct clk_funcs tegra124_car_clock_funcs = { 281 .get = tegra124_car_clock_get, 282 .put = tegra124_car_clock_put, 283 .get_rate = tegra124_car_clock_get_rate, 284 .set_rate = tegra124_car_clock_set_rate, 285 .enable = tegra124_car_clock_enable, 286 .disable = tegra124_car_clock_disable, 287 .set_parent = tegra124_car_clock_set_parent, 288 .get_parent = tegra124_car_clock_get_parent, 289 }; 290 291 #define CLK_FIXED(_name, _rate) { \ 292 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 293 .u = { .fixed = { .rate = (_rate) } } \ 294 } 295 296 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 297 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 298 .parent = (_parent), \ 299 .u = { \ 300 .pll = { \ 301 .base_reg = (_base), \ 302 .divm_mask = (_divm), \ 303 .divn_mask = (_divn), \ 304 .divp_mask = (_divp), \ 305 } \ 306 } \ 307 } 308 309 #define CLK_MUX(_name, _reg, _bits, _p) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 311 .u = { \ 312 .mux = { \ 313 .nparents = __arraycount(_p), \ 314 .parents = (_p), \ 315 .reg = (_reg), \ 316 .bits = (_bits) \ 317 } \ 318 } \ 319 } 320 321 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 322 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 323 .parent = (_parent), \ 324 .u = { \ 325 .fixed_div = { \ 326 .div = (_div) \ 327 } \ 328 } \ 329 } 330 331 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 332 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 333 .parent = (_parent), \ 334 .u = { \ 335 .div = { \ 336 .reg = (_reg), \ 337 .bits = (_bits) \ 338 } \ 339 } \ 340 } 341 342 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 343 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 344 .type = TEGRA_CLK_GATE, \ 345 .parent = (_parent), \ 346 .u = { \ 347 .gate = { \ 348 .set_reg = (_set), \ 349 .clr_reg = (_clr), \ 350 .bits = (_bits), \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE_L(_name, _parent, _bits) \ 356 CLK_GATE(_name, _parent, \ 357 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 358 _bits) 359 360 #define CLK_GATE_H(_name, _parent, _bits) \ 361 CLK_GATE(_name, _parent, \ 362 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 363 _bits) 364 365 #define CLK_GATE_U(_name, _parent, _bits) \ 366 CLK_GATE(_name, _parent, \ 367 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 368 _bits) 369 370 #define CLK_GATE_V(_name, _parent, _bits) \ 371 CLK_GATE(_name, _parent, \ 372 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 373 _bits) 374 375 #define CLK_GATE_W(_name, _parent, _bits) \ 376 CLK_GATE(_name, _parent, \ 377 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 378 _bits) 379 380 #define CLK_GATE_X(_name, _parent, _bits) \ 381 CLK_GATE(_name, _parent, \ 382 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 383 _bits) 384 385 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 386 CLK_GATE(_name, _parent, _reg, _reg, _bits) 387 388 static const char *mux_uart_p[] = 389 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 390 "pll_m_out0", NULL, "clk_m" }; 391 static const char *mux_sdmmc_p[] = 392 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 393 "pll_m_out0", "pll_e_out0", "clk_m" }; 394 static const char *mux_i2c_p[] = 395 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 396 "pll_m_out0", NULL, "clk_m" }; 397 static const char *mux_sata_p[] = 398 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 399 static const char *mux_hda_p[] = 400 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 401 "pll_m_out0", NULL, "clk_m" }; 402 static const char *mux_tsensor_p[] = 403 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 404 NULL, "clk_s" }; 405 static const char *mux_soc_therm_p[] = 406 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 407 "pll_c3_out0" }; 408 static const char *mux_host1x_p[] = 409 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 410 "pll_p_out0", NULL, "pll_a_out0" }; 411 static const char *mux_disp_p[] = 412 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 413 "pll_d2_out0", "clk_m" }; 414 static const char *mux_hdmi_p[] = 415 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 416 "pll_d2_out0", "clk_m" }; 417 418 static struct tegra_clk tegra124_car_clocks[] = { 419 CLK_FIXED("clk_m", TEGRA_REF_FREQ), 420 421 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 422 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 423 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 424 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 425 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 426 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 427 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 428 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 429 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 430 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 431 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 432 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 433 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 434 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 435 436 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 437 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 438 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 439 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 440 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 441 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 442 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 443 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 444 445 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 446 mux_uart_p), 447 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 448 mux_uart_p), 449 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 450 mux_uart_p), 451 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 452 mux_uart_p), 453 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 454 mux_sdmmc_p), 455 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 456 mux_sdmmc_p), 457 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 458 mux_sdmmc_p), 459 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 460 mux_sdmmc_p), 461 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 462 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 463 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 464 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 465 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 466 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 467 CLK_MUX("mux_sata_oob", 468 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 469 CLK_MUX("mux_sata", 470 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 471 CLK_MUX("mux_hda2codec_2x", 472 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 473 mux_hda_p), 474 CLK_MUX("mux_hda", 475 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 476 CLK_MUX("mux_soc_therm", 477 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 478 mux_soc_therm_p), 479 CLK_MUX("mux_tsensor", 480 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 481 mux_tsensor_p), 482 CLK_MUX("mux_host1x", 483 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 484 mux_host1x_p), 485 CLK_MUX("mux_disp1", 486 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 487 mux_disp_p), 488 CLK_MUX("mux_disp2", 489 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 490 mux_disp_p), 491 CLK_MUX("mux_hdmi", 492 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 493 mux_hdmi_p), 494 495 CLK_DIV("div_uarta", "mux_uarta", 496 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 497 CLK_DIV("div_uartb", "mux_uartb", 498 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 499 CLK_DIV("div_uartc", "mux_uartc", 500 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 501 CLK_DIV("div_uartd", "mux_uartd", 502 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 503 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 504 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 505 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 506 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 507 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 508 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 509 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 510 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 511 CLK_DIV("div_i2c1", "mux_i2c1", 512 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 513 CLK_DIV("div_i2c2", "mux_i2c2", 514 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 515 CLK_DIV("div_i2c3", "mux_i2c3", 516 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 517 CLK_DIV("div_i2c4", "mux_i2c4", 518 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 519 CLK_DIV("div_i2c5", "mux_i2c5", 520 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 521 CLK_DIV("div_i2c6", "mux_i2c6", 522 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 523 CLK_DIV("div_sata_oob", "mux_sata_oob", 524 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 525 CLK_DIV("div_sata", "mux_sata", 526 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 527 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 528 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 529 CLK_DIV("div_hda", "mux_hda", 530 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 531 CLK_DIV("div_soc_therm", "mux_soc_therm", 532 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 533 CLK_DIV("div_tsensor", "mux_tsensor", 534 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 535 CLK_DIV("div_host1x", "mux_host1x", 536 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 537 CLK_DIV("div_hdmi", "mux_hdmi", 538 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 539 CLK_DIV("div_pll_p_out5", "pll_p", 540 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 541 542 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 543 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 544 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 545 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 546 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 547 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 548 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 549 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 550 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 551 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 552 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 553 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 554 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 555 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 556 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 557 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 558 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 559 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 560 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 561 CLK_GATE_SIMPLE("cml0", "pll_e", 562 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 563 CLK_GATE_SIMPLE("cml1", "pll_e", 564 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 565 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 566 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 567 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 568 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 569 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 570 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 571 CLK_GATE_SIMPLE("watchdog", "clk_m", CAR_RST_SOURCE_REG, 572 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN), 573 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 574 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 575 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 576 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 577 CLK_GATE_SIMPLE("pll_p_out5", "div_pllp_out5", 578 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 579 }; 580 581 struct tegra124_car_rst { 582 u_int set_reg; 583 u_int clr_reg; 584 u_int mask; 585 }; 586 587 static struct tegra124_car_reset_reg { 588 u_int set_reg; 589 u_int clr_reg; 590 } tegra124_car_reset_regs[] = { 591 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 592 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 593 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 594 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 595 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 596 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 597 }; 598 599 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 600 static void tegra124_car_reset_release(device_t, void *); 601 static int tegra124_car_reset_assert(device_t, void *); 602 static int tegra124_car_reset_deassert(device_t, void *); 603 604 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 605 .acquire = tegra124_car_reset_acquire, 606 .release = tegra124_car_reset_release, 607 .reset_assert = tegra124_car_reset_assert, 608 .reset_deassert = tegra124_car_reset_deassert, 609 }; 610 611 struct tegra124_car_softc { 612 device_t sc_dev; 613 bus_space_tag_t sc_bst; 614 bus_space_handle_t sc_bsh; 615 616 u_int sc_clock_cells; 617 u_int sc_reset_cells; 618 619 kmutex_t sc_intr_lock; 620 kmutex_t sc_rnd_lock; 621 u_int sc_bytes_wanted; 622 void *sc_sih; 623 krndsource_t sc_rndsource; 624 }; 625 626 static void tegra124_car_init(struct tegra124_car_softc *); 627 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 628 629 static void tegra124_car_rnd_attach(device_t); 630 static void tegra124_car_rnd_intr(void *); 631 static void tegra124_car_rnd_callback(size_t, void *); 632 633 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 634 tegra124_car_match, tegra124_car_attach, NULL, NULL); 635 636 static int 637 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 638 { 639 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 640 struct fdt_attach_args * const faa = aux; 641 642 #if 0 643 return of_match_compatible(faa->faa_phandle, compatible); 644 #else 645 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 646 return 0; 647 648 return 999; 649 #endif 650 } 651 652 static void 653 tegra124_car_attach(device_t parent, device_t self, void *aux) 654 { 655 struct tegra124_car_softc * const sc = device_private(self); 656 struct fdt_attach_args * const faa = aux; 657 const int phandle = faa->faa_phandle; 658 bus_addr_t addr; 659 bus_size_t size; 660 int error; 661 662 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 663 aprint_error(": couldn't get registers\n"); 664 return; 665 } 666 667 sc->sc_dev = self; 668 sc->sc_bst = faa->faa_bst; 669 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 670 if (error) { 671 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 672 return; 673 } 674 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 675 sc->sc_clock_cells = 1; 676 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 677 sc->sc_reset_cells = 1; 678 679 aprint_naive("\n"); 680 aprint_normal(": CAR\n"); 681 682 clk_backend_register("tegra124", &tegra124_car_clock_funcs, sc); 683 684 fdtbus_register_clock_controller(self, phandle, 685 &tegra124_car_fdtclock_funcs); 686 fdtbus_register_reset_controller(self, phandle, 687 &tegra124_car_fdtreset_funcs); 688 689 tegra124_car_init(sc); 690 691 config_interrupts(self, tegra124_car_rnd_attach); 692 } 693 694 static void 695 tegra124_car_init(struct tegra124_car_softc *sc) 696 { 697 tegra124_car_utmip_init(sc); 698 } 699 700 static void 701 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 702 { 703 bus_space_tag_t bst = sc->sc_bst; 704 bus_space_handle_t bsh = sc->sc_bsh; 705 706 const u_int enable_dly_count = 0x02; 707 const u_int stable_count = 0x2f; 708 const u_int active_dly_count = 0x04; 709 const u_int xtal_freq_count = 0x76; 710 711 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 712 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 713 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 714 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 715 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 716 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 717 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 718 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 719 720 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 721 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 722 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 723 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 724 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 725 726 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 727 0, 728 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 729 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 730 731 } 732 733 static void 734 tegra124_car_rnd_attach(device_t self) 735 { 736 struct tegra124_car_softc * const sc = device_private(self); 737 738 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL); 739 mutex_init(&sc->sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL); 740 sc->sc_bytes_wanted = 0; 741 sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE, 742 tegra124_car_rnd_intr, sc); 743 if (sc->sc_sih == NULL) { 744 aprint_error_dev(sc->sc_dev, "couldn't establish softint\n"); 745 return; 746 } 747 748 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 749 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 750 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 751 } 752 753 static void 754 tegra124_car_rnd_intr(void *priv) 755 { 756 struct tegra124_car_softc * const sc = priv; 757 uint16_t buf[512]; 758 uint32_t cnt; 759 760 mutex_enter(&sc->sc_intr_lock); 761 while (sc->sc_bytes_wanted) { 762 const u_int nbytes = MIN(sc->sc_bytes_wanted, 1024); 763 for (cnt = 0; cnt < sc->sc_bytes_wanted / 2; cnt++) { 764 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 765 CAR_PLL_LFSR_REG) & 0xffff; 766 } 767 mutex_exit(&sc->sc_intr_lock); 768 mutex_enter(&sc->sc_rnd_lock); 769 rnd_add_data(&sc->sc_rndsource, buf, nbytes, nbytes * NBBY); 770 mutex_exit(&sc->sc_rnd_lock); 771 mutex_enter(&sc->sc_intr_lock); 772 sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, nbytes); 773 } 774 explicit_memset(buf, 0, sizeof(buf)); 775 mutex_exit(&sc->sc_intr_lock); 776 } 777 778 static void 779 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 780 { 781 struct tegra124_car_softc * const sc = priv; 782 783 mutex_enter(&sc->sc_intr_lock); 784 if (sc->sc_bytes_wanted == 0) { 785 softint_schedule(sc->sc_sih); 786 } 787 if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) { 788 sc->sc_bytes_wanted = UINT_MAX; 789 } else { 790 sc->sc_bytes_wanted += bytes_wanted; 791 } 792 mutex_exit(&sc->sc_intr_lock); 793 } 794 795 static struct tegra_clk * 796 tegra124_car_clock_find(const char *name) 797 { 798 u_int n; 799 800 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 801 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 802 return &tegra124_car_clocks[n]; 803 } 804 } 805 806 return NULL; 807 } 808 809 static struct tegra_clk * 810 tegra124_car_clock_find_by_id(u_int clock_id) 811 { 812 u_int n; 813 814 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 815 if (tegra124_car_clock_ids[n].id == clock_id) { 816 const char *name = tegra124_car_clock_ids[n].name; 817 return tegra124_car_clock_find(name); 818 } 819 } 820 821 return NULL; 822 } 823 824 static struct clk * 825 tegra124_car_clock_decode(device_t dev, const void *data, size_t len) 826 { 827 struct tegra124_car_softc * const sc = device_private(dev); 828 struct tegra_clk *tclk; 829 830 if (len != sc->sc_clock_cells * 4) { 831 return NULL; 832 } 833 834 const u_int clock_id = be32dec(data); 835 836 tclk = tegra124_car_clock_find_by_id(clock_id); 837 if (tclk) 838 return TEGRA_CLK_BASE(tclk); 839 840 return NULL; 841 } 842 843 static struct clk * 844 tegra124_car_clock_get(void *priv, const char *name) 845 { 846 struct tegra_clk *tclk; 847 848 tclk = tegra124_car_clock_find(name); 849 if (tclk == NULL) 850 return NULL; 851 852 atomic_inc_uint(&tclk->refcnt); 853 854 return TEGRA_CLK_BASE(tclk); 855 } 856 857 static void 858 tegra124_car_clock_put(void *priv, struct clk *clk) 859 { 860 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 861 862 KASSERT(tclk->refcnt > 0); 863 864 atomic_dec_uint(&tclk->refcnt); 865 } 866 867 static u_int 868 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 869 struct tegra_clk *tclk) 870 { 871 struct tegra_pll_clk *tpll = &tclk->u.pll; 872 struct tegra_clk *tclk_parent; 873 bus_space_tag_t bst = sc->sc_bst; 874 bus_space_handle_t bsh = sc->sc_bsh; 875 u_int divm, divn, divp; 876 uint64_t rate; 877 878 KASSERT(tclk->type == TEGRA_CLK_PLL); 879 880 tclk_parent = tegra124_car_clock_find(tclk->parent); 881 KASSERT(tclk_parent != NULL); 882 883 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 884 TEGRA_CLK_BASE(tclk_parent)); 885 886 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 887 divm = __SHIFTOUT(base, tpll->divm_mask); 888 divn = __SHIFTOUT(base, tpll->divn_mask); 889 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 890 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 891 } else { 892 divp = __SHIFTOUT(base, tpll->divp_mask); 893 } 894 895 rate = (uint64_t)rate_parent * divn; 896 return rate / (divm << divp); 897 } 898 899 static int 900 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 901 struct tegra_clk *tclk, u_int rate) 902 { 903 struct tegra_pll_clk *tpll = &tclk->u.pll; 904 bus_space_tag_t bst = sc->sc_bst; 905 bus_space_handle_t bsh = sc->sc_bsh; 906 struct clk *clk_parent; 907 uint32_t bp, base; 908 909 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 910 if (clk_parent == NULL) 911 return EIO; 912 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 913 if (rate_parent == 0) 914 return EIO; 915 916 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 917 const u_int divm = 1; 918 const u_int divn = rate / rate_parent; 919 const u_int divp = 0; 920 921 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 922 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 923 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 924 CAR_CCLKG_BURST_POLICY_CPU_STATE); 925 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 926 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 927 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 928 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 929 930 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 931 base &= ~CAR_PLLX_BASE_DIVM; 932 base &= ~CAR_PLLX_BASE_DIVN; 933 base &= ~CAR_PLLX_BASE_DIVP; 934 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 935 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 936 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 937 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 938 939 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 940 CAR_PLLX_MISC_LOCK_ENABLE, 0); 941 do { 942 delay(2); 943 base = bus_space_read_4(bst, bsh, tpll->base_reg); 944 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 945 delay(100); 946 947 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 948 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 949 CAR_CCLKG_BURST_POLICY_CPU_STATE); 950 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 951 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 952 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 953 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 954 955 return 0; 956 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 957 const u_int divm = 1; 958 const u_int pldiv = 1; 959 const u_int divn = (rate << pldiv) / rate_parent; 960 961 /* Set frequency */ 962 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 963 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 964 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 965 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 966 CAR_PLLD2_BASE_REF_SRC_SEL | 967 CAR_PLLD2_BASE_DIVM | 968 CAR_PLLD2_BASE_DIVN | 969 CAR_PLLD2_BASE_DIVP); 970 971 return 0; 972 } else { 973 /* TODO */ 974 return EOPNOTSUPP; 975 } 976 } 977 978 static int 979 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 980 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 981 { 982 struct tegra_mux_clk *tmux = &tclk->u.mux; 983 bus_space_tag_t bst = sc->sc_bst; 984 bus_space_handle_t bsh = sc->sc_bsh; 985 uint32_t v; 986 u_int src; 987 988 KASSERT(tclk->type == TEGRA_CLK_MUX); 989 990 for (src = 0; src < tmux->nparents; src++) { 991 if (tmux->parents[src] == NULL) { 992 continue; 993 } 994 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 995 break; 996 } 997 } 998 if (src == tmux->nparents) { 999 return EINVAL; 1000 } 1001 1002 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1003 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1004 /* Change IDDQ from 1 to 0 */ 1005 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1006 0, CAR_PLLD2_BASE_IDDQ); 1007 delay(2); 1008 1009 /* Enable lock */ 1010 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1011 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1012 1013 /* Enable PLLD2 */ 1014 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1015 CAR_PLLD2_BASE_ENABLE, 0); 1016 1017 /* Wait for lock */ 1018 do { 1019 delay(2); 1020 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1021 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1022 1023 delay(200); 1024 } 1025 1026 v = bus_space_read_4(bst, bsh, tmux->reg); 1027 v &= ~tmux->bits; 1028 v |= __SHIFTIN(src, tmux->bits); 1029 bus_space_write_4(bst, bsh, tmux->reg, v); 1030 1031 return 0; 1032 } 1033 1034 static struct tegra_clk * 1035 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1036 struct tegra_clk *tclk) 1037 { 1038 struct tegra_mux_clk *tmux = &tclk->u.mux; 1039 bus_space_tag_t bst = sc->sc_bst; 1040 bus_space_handle_t bsh = sc->sc_bsh; 1041 1042 KASSERT(tclk->type == TEGRA_CLK_MUX); 1043 1044 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1045 const u_int src = __SHIFTOUT(v, tmux->bits); 1046 1047 KASSERT(src < tmux->nparents); 1048 1049 if (tmux->parents[src] == NULL) { 1050 return NULL; 1051 } 1052 1053 return tegra124_car_clock_find(tmux->parents[src]); 1054 } 1055 1056 static u_int 1057 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1058 struct tegra_clk *tclk) 1059 { 1060 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1061 struct clk *clk_parent; 1062 1063 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1064 if (clk_parent == NULL) 1065 return 0; 1066 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1067 1068 return parent_rate / tfixed_div->div; 1069 } 1070 1071 static u_int 1072 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1073 struct tegra_clk *tclk) 1074 { 1075 struct tegra_div_clk *tdiv = &tclk->u.div; 1076 bus_space_tag_t bst = sc->sc_bst; 1077 bus_space_handle_t bsh = sc->sc_bsh; 1078 struct clk *clk_parent; 1079 u_int div; 1080 1081 KASSERT(tclk->type == TEGRA_CLK_DIV); 1082 1083 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1084 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1085 1086 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1087 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1088 1089 switch (tdiv->reg) { 1090 case CAR_CLKSRC_UARTA_REG: 1091 case CAR_CLKSRC_UARTB_REG: 1092 case CAR_CLKSRC_UARTC_REG: 1093 case CAR_CLKSRC_UARTD_REG: 1094 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1095 div = raw_div * 2; 1096 } else { 1097 div = 2; 1098 } 1099 break; 1100 default: 1101 div = raw_div * 2; 1102 break; 1103 } 1104 1105 return (parent_rate * 2) / div; 1106 } 1107 1108 static int 1109 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1110 struct tegra_clk *tclk, u_int rate) 1111 { 1112 struct tegra_div_clk *tdiv = &tclk->u.div; 1113 bus_space_tag_t bst = sc->sc_bst; 1114 bus_space_handle_t bsh = sc->sc_bsh; 1115 struct clk *clk_parent; 1116 uint32_t v; 1117 1118 KASSERT(tclk->type == TEGRA_CLK_DIV); 1119 1120 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1121 if (clk_parent == NULL) 1122 return EINVAL; 1123 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1124 1125 v = bus_space_read_4(bst, bsh, tdiv->reg); 1126 1127 switch (tdiv->reg) { 1128 case CAR_CLKSRC_UARTA_REG: 1129 case CAR_CLKSRC_UARTB_REG: 1130 case CAR_CLKSRC_UARTC_REG: 1131 case CAR_CLKSRC_UARTD_REG: 1132 if (rate == parent_rate) { 1133 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1134 } else { 1135 v |= CAR_CLKSRC_UART_DIV_ENB; 1136 } 1137 break; 1138 case CAR_CLKSRC_SATA_REG: 1139 if (rate) { 1140 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1141 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1142 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1143 } else { 1144 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1145 } 1146 break; 1147 case CAR_CLKSRC_HDMI_REG: 1148 1149 break; 1150 } 1151 1152 const u_int raw_div = rate ? howmany(parent_rate * 2, rate) - 2 : 0; 1153 //const u_int raw_div = rate ? (parent_rate * 2) / rate - 2 : 0; 1154 1155 v &= ~tdiv->bits; 1156 v |= __SHIFTIN(raw_div, tdiv->bits); 1157 1158 bus_space_write_4(bst, bsh, tdiv->reg, v); 1159 1160 return 0; 1161 } 1162 1163 static int 1164 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1165 struct tegra_clk *tclk, bool enable) 1166 { 1167 struct tegra_gate_clk *tgate = &tclk->u.gate; 1168 bus_space_tag_t bst = sc->sc_bst; 1169 bus_space_handle_t bsh = sc->sc_bsh; 1170 bus_size_t reg; 1171 1172 KASSERT(tclk->type == TEGRA_CLK_GATE); 1173 1174 if (tgate->set_reg == tgate->clr_reg) { 1175 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1176 if (enable) { 1177 v |= tgate->bits; 1178 } else { 1179 v &= ~tgate->bits; 1180 } 1181 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1182 } else { 1183 if (enable) { 1184 reg = tgate->set_reg; 1185 } else { 1186 reg = tgate->clr_reg; 1187 } 1188 1189 if (reg == CAR_CLK_ENB_V_SET_REG && 1190 tgate->bits == CAR_DEV_V_SATA) { 1191 /* De-assert reset to SATA PADPLL */ 1192 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1193 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1194 delay(15); 1195 } 1196 bus_space_write_4(bst, bsh, reg, tgate->bits); 1197 } 1198 1199 return 0; 1200 } 1201 1202 static u_int 1203 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1204 { 1205 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1206 struct clk *clk_parent; 1207 1208 switch (tclk->type) { 1209 case TEGRA_CLK_FIXED: 1210 return tclk->u.fixed.rate; 1211 case TEGRA_CLK_PLL: 1212 return tegra124_car_clock_get_rate_pll(priv, tclk); 1213 case TEGRA_CLK_MUX: 1214 case TEGRA_CLK_GATE: 1215 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1216 if (clk_parent == NULL) 1217 return EINVAL; 1218 return tegra124_car_clock_get_rate(priv, clk_parent); 1219 case TEGRA_CLK_FIXED_DIV: 1220 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1221 case TEGRA_CLK_DIV: 1222 return tegra124_car_clock_get_rate_div(priv, tclk); 1223 default: 1224 panic("tegra124: unknown tclk type %d", tclk->type); 1225 } 1226 } 1227 1228 static int 1229 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1230 { 1231 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1232 struct clk *clk_parent; 1233 1234 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1235 1236 switch (tclk->type) { 1237 case TEGRA_CLK_FIXED: 1238 case TEGRA_CLK_MUX: 1239 return EIO; 1240 case TEGRA_CLK_FIXED_DIV: 1241 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1242 if (clk_parent == NULL) 1243 return EIO; 1244 return tegra124_car_clock_set_rate(priv, clk_parent, 1245 rate * tclk->u.fixed_div.div); 1246 case TEGRA_CLK_GATE: 1247 return EINVAL; 1248 case TEGRA_CLK_PLL: 1249 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1250 case TEGRA_CLK_DIV: 1251 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1252 default: 1253 panic("tegra124: unknown tclk type %d", tclk->type); 1254 } 1255 } 1256 1257 static int 1258 tegra124_car_clock_enable(void *priv, struct clk *clk) 1259 { 1260 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1261 struct clk *clk_parent; 1262 1263 if (tclk->type != TEGRA_CLK_GATE) { 1264 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1265 if (clk_parent == NULL) 1266 return 0; 1267 return tegra124_car_clock_enable(priv, clk_parent); 1268 } 1269 1270 return tegra124_car_clock_enable_gate(priv, tclk, true); 1271 } 1272 1273 static int 1274 tegra124_car_clock_disable(void *priv, struct clk *clk) 1275 { 1276 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1277 1278 if (tclk->type != TEGRA_CLK_GATE) 1279 return EINVAL; 1280 1281 return tegra124_car_clock_enable_gate(priv, tclk, false); 1282 } 1283 1284 static int 1285 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1286 struct clk *clk_parent) 1287 { 1288 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1289 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1290 struct clk *nclk_parent; 1291 1292 if (tclk->type != TEGRA_CLK_MUX) { 1293 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1294 if (nclk_parent == clk_parent || nclk_parent == NULL) 1295 return EINVAL; 1296 return tegra124_car_clock_set_parent(priv, nclk_parent, 1297 clk_parent); 1298 } 1299 1300 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1301 } 1302 1303 static struct clk * 1304 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1305 { 1306 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1307 struct tegra_clk *tclk_parent = NULL; 1308 1309 switch (tclk->type) { 1310 case TEGRA_CLK_FIXED: 1311 case TEGRA_CLK_PLL: 1312 case TEGRA_CLK_FIXED_DIV: 1313 case TEGRA_CLK_DIV: 1314 case TEGRA_CLK_GATE: 1315 if (tclk->parent) { 1316 tclk_parent = tegra124_car_clock_find(tclk->parent); 1317 } 1318 break; 1319 case TEGRA_CLK_MUX: 1320 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1321 break; 1322 } 1323 1324 if (tclk_parent == NULL) 1325 return NULL; 1326 1327 return TEGRA_CLK_BASE(tclk_parent); 1328 } 1329 1330 static void * 1331 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1332 { 1333 struct tegra124_car_softc * const sc = device_private(dev); 1334 struct tegra124_car_rst *rst; 1335 1336 if (len != sc->sc_reset_cells * 4) 1337 return NULL; 1338 1339 const u_int reset_id = be32dec(data); 1340 1341 if (reset_id > __arraycount(tegra124_car_reset_regs) * 32) 1342 return NULL; 1343 1344 const u_int reg = reset_id / 32; 1345 1346 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1347 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1348 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1349 rst->mask = __BIT(reset_id % 32); 1350 1351 return rst; 1352 } 1353 1354 static void 1355 tegra124_car_reset_release(device_t dev, void *priv) 1356 { 1357 struct tegra124_car_rst *rst = priv; 1358 1359 kmem_free(rst, sizeof(*rst)); 1360 } 1361 1362 static int 1363 tegra124_car_reset_assert(device_t dev, void *priv) 1364 { 1365 struct tegra124_car_softc * const sc = device_private(dev); 1366 struct tegra124_car_rst *rst = priv; 1367 1368 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1369 1370 return 0; 1371 } 1372 1373 static int 1374 tegra124_car_reset_deassert(device_t dev, void *priv) 1375 { 1376 struct tegra124_car_softc * const sc = device_private(dev); 1377 struct tegra124_car_rst *rst = priv; 1378 1379 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1380 1381 return 0; 1382 } 1383
Indexes created Tue Sep 30 20:09:53 GMT 2025