tegra124_car.c revision 1.10
1 /* $NetBSD: tegra124_car.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra124_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra124_car_match(device_t, cfdata_t, void *); 54 static void tegra124_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra124_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 59 .decode = tegra124_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra124_car_clock_id { 64 u_int id; 65 const char *name; 66 } tegra124_car_clock_ids[] = { 67 { 3, "ispb" }, 68 { 4, "rtc" }, 69 { 5, "timer" }, 70 { 6, "uarta" }, 71 { 9, "sdmmc2" }, 72 { 11, "i2s1" }, 73 { 12, "i2c1" }, 74 { 14, "sdmmc1" }, 75 { 15, "sdmmc4" }, 76 { 17, "pwm" }, 77 { 18, "i2s2" }, 78 { 22, "usbd" }, 79 { 23, "isp" }, 80 { 26, "disp2" }, 81 { 27, "disp1" }, 82 { 28, "host1x" }, 83 { 29, "vcp" }, 84 { 30, "i2s0" }, 85 { 32, "mc" }, 86 { 34, "apbdma" }, 87 { 36, "kbc" }, 88 { 40, "kfuse" }, 89 { 41, "spi1" }, 90 { 42, "nor" }, 91 { 44, "spi2" }, 92 { 46, "spi3" }, 93 { 47, "i2c5" }, 94 { 48, "dsia" }, 95 { 50, "mipi" }, 96 { 51, "hdmi" }, 97 { 52, "csi" }, 98 { 54, "i2c2" }, 99 { 55, "uartc" }, 100 { 56, "mipi_cal" }, 101 { 57, "emc" }, 102 { 58, "usb2" }, 103 { 59, "usb3" }, 104 { 61, "vde" }, 105 { 62, "bsea" }, 106 { 63, "bsev" }, 107 { 65, "uartd" }, 108 { 67, "i2c3" }, 109 { 68, "spi4" }, 110 { 69, "sdmmc3" }, 111 { 70, "pcie" }, 112 { 71, "owr" }, 113 { 72, "afi" }, 114 { 73, "csite" }, 115 { 76, "la" }, 116 { 77, "trace" }, 117 { 78, "soc_therm" }, 118 { 79, "dtv" }, 119 { 81, "i2cslow" }, 120 { 82, "dsib" }, 121 { 83, "tsec" }, 122 { 89, "xusb_host" }, 123 { 91, "msenc" }, 124 { 92, "csus" }, 125 { 99, "mselect" }, 126 { 100, "tsensor" }, 127 { 101, "i2s3" }, 128 { 102, "i2s4" }, 129 { 103, "i2c4" }, 130 { 104, "spi5" }, 131 { 105, "spi6" }, 132 { 106, "d_audio" }, 133 { 107, "apbif" }, 134 { 108, "dam0" }, 135 { 109, "dam1" }, 136 { 110, "dam2" }, 137 { 111, "hda2codec_2x" }, 138 { 113, "audio0_2x" }, 139 { 114, "audio1_2x" }, 140 { 115, "audio2_2x" }, 141 { 116, "audio3_2x" }, 142 { 117, "audio4_2x" }, 143 { 118, "spdif_2x" }, 144 { 119, "actmon" }, 145 { 120, "extern1" }, 146 { 121, "extern2" }, 147 { 122, "extern3" }, 148 { 123, "sata_oob" }, 149 { 124, "sata" }, 150 { 125, "hda" }, 151 { 127, "se" }, 152 { 128, "hda2hdmi" }, 153 { 129, "sata_cold" }, 154 { 144, "cilab" }, 155 { 145, "cilcd" }, 156 { 146, "cile" }, 157 { 147, "dsialp" }, 158 { 148, "dsiblp" }, 159 { 149, "entropy" }, 160 { 150, "dds" }, 161 { 152, "dp2" }, 162 { 153, "amx" }, 163 { 154, "adx" }, 164 { 156, "xusb_ss" }, 165 { 166, "i2c6" }, 166 { 171, "vim2_clk" }, 167 { 176, "hdmi_audio" }, 168 { 177, "clk72mhz" }, 169 { 178, "vic03" }, 170 { 180, "adx1" }, 171 { 181, "dpaux" }, 172 { 182, "sor0" }, 173 { 184, "gpu" }, 174 { 185, "amx1" }, 175 { 192, "uartb" }, 176 { 193, "vfir" }, 177 { 194, "spdif_in" }, 178 { 195, "spdif_out" }, 179 { 196, "vi" }, 180 { 197, "vi_sensor" }, 181 { 198, "fuse" }, 182 { 199, "fuse_burn" }, 183 { 200, "clk_32k" }, 184 { 201, "clk_m" }, 185 { 202, "clk_m_div2" }, 186 { 203, "clk_m_div4" }, 187 { 204, "pll_ref" }, 188 { 205, "pll_c" }, 189 { 206, "pll_c_out1" }, 190 { 207, "pll_c2" }, 191 { 208, "pll_c3" }, 192 { 209, "pll_m" }, 193 { 210, "pll_m_out1" }, 194 { 211, "pll_p_out0" }, 195 { 212, "pll_p_out1" }, 196 { 213, "pll_p_out2" }, 197 { 214, "pll_p_out3" }, 198 { 215, "pll_p_out4" }, 199 { 216, "pll_a" }, 200 { 217, "pll_a_out0" }, 201 { 218, "pll_d" }, 202 { 219, "pll_d_out0" }, 203 { 220, "pll_d2" }, 204 { 221, "pll_d2_out0" }, 205 { 222, "pll_u" }, 206 { 223, "pll_u_480m" }, 207 { 224, "pll_u_60m" }, 208 { 225, "pll_u_48m" }, 209 { 226, "pll_u_12m" }, 210 { 229, "pll_re_vco" }, 211 { 230, "pll_re_out" }, 212 { 231, "pll_e" }, 213 { 232, "spdif_in_sync" }, 214 { 233, "i2s0_sync" }, 215 { 234, "i2s1_sync" }, 216 { 235, "i2s2_sync" }, 217 { 236, "i2s3_sync" }, 218 { 237, "i2s4_sync" }, 219 { 238, "vimclk_sync" }, 220 { 239, "audio0" }, 221 { 240, "audio1" }, 222 { 241, "audio2" }, 223 { 242, "audio3" }, 224 { 243, "audio4" }, 225 { 244, "spdif" }, 226 { 245, "clk_out_1" }, 227 { 246, "clk_out_2" }, 228 { 247, "clk_out_3" }, 229 { 248, "blink" }, 230 { 252, "xusb_host_src" }, 231 { 253, "xusb_falcon_src" }, 232 { 254, "xusb_fs_src" }, 233 { 255, "xusb_ss_src" }, 234 { 256, "xusb_dev_src" }, 235 { 257, "xusb_dev" }, 236 { 258, "xusb_hs_src" }, 237 { 259, "sclk" }, 238 { 260, "hclk" }, 239 { 261, "pclk" }, 240 { 264, "dfll_ref" }, 241 { 265, "dfll_soc" }, 242 { 266, "vi_sensor2" }, 243 { 267, "pll_p_out5" }, 244 { 268, "cml0" }, 245 { 269, "cml1" }, 246 { 270, "pll_c4" }, 247 { 271, "pll_dp" }, 248 { 272, "pll_e_mux" }, 249 { 273, "pll_d_dsi_out" }, 250 { 300, "audio0_mux" }, 251 { 301, "audio1_mux" }, 252 { 302, "audio2_mux" }, 253 { 303, "audio3_mux" }, 254 { 304, "audio4_mux" }, 255 { 305, "spdif_mux" }, 256 { 306, "clk_out_1_mux" }, 257 { 307, "clk_out_2_mux" }, 258 { 308, "clk_out_3_mux" }, 259 { 311, "sor0_lvds" }, 260 { 312, "xusb_ss_div2" }, 261 { 313, "pll_m_ud" }, 262 { 314, "pll_c_ud" }, 263 { 227, "pll_x" }, 264 { 228, "pll_x_out0" }, 265 { 262, "cclk_g" }, 266 { 263, "cclk_lp" }, 267 { 315, "clk_max" }, 268 }; 269 270 static struct clk *tegra124_car_clock_get(void *, const char *); 271 static void tegra124_car_clock_put(void *, struct clk *); 272 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 273 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 274 static int tegra124_car_clock_enable(void *, struct clk *); 275 static int tegra124_car_clock_disable(void *, struct clk *); 276 static int tegra124_car_clock_set_parent(void *, struct clk *, 277 struct clk *); 278 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 279 280 static const struct clk_funcs tegra124_car_clock_funcs = { 281 .get = tegra124_car_clock_get, 282 .put = tegra124_car_clock_put, 283 .get_rate = tegra124_car_clock_get_rate, 284 .set_rate = tegra124_car_clock_set_rate, 285 .enable = tegra124_car_clock_enable, 286 .disable = tegra124_car_clock_disable, 287 .set_parent = tegra124_car_clock_set_parent, 288 .get_parent = tegra124_car_clock_get_parent, 289 }; 290 291 #define CLK_FIXED(_name, _rate) { \ 292 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 293 .u = { .fixed = { .rate = (_rate) } } \ 294 } 295 296 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 297 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 298 .parent = (_parent), \ 299 .u = { \ 300 .pll = { \ 301 .base_reg = (_base), \ 302 .divm_mask = (_divm), \ 303 .divn_mask = (_divn), \ 304 .divp_mask = (_divp), \ 305 } \ 306 } \ 307 } 308 309 #define CLK_MUX(_name, _reg, _bits, _p) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 311 .u = { \ 312 .mux = { \ 313 .nparents = __arraycount(_p), \ 314 .parents = (_p), \ 315 .reg = (_reg), \ 316 .bits = (_bits) \ 317 } \ 318 } \ 319 } 320 321 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 322 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 323 .parent = (_parent), \ 324 .u = { \ 325 .fixed_div = { \ 326 .div = (_div) \ 327 } \ 328 } \ 329 } 330 331 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 332 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 333 .parent = (_parent), \ 334 .u = { \ 335 .div = { \ 336 .reg = (_reg), \ 337 .bits = (_bits) \ 338 } \ 339 } \ 340 } 341 342 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 343 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 344 .type = TEGRA_CLK_GATE, \ 345 .parent = (_parent), \ 346 .u = { \ 347 .gate = { \ 348 .set_reg = (_set), \ 349 .clr_reg = (_clr), \ 350 .bits = (_bits), \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE_L(_name, _parent, _bits) \ 356 CLK_GATE(_name, _parent, \ 357 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 358 _bits) 359 360 #define CLK_GATE_H(_name, _parent, _bits) \ 361 CLK_GATE(_name, _parent, \ 362 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 363 _bits) 364 365 #define CLK_GATE_U(_name, _parent, _bits) \ 366 CLK_GATE(_name, _parent, \ 367 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 368 _bits) 369 370 #define CLK_GATE_V(_name, _parent, _bits) \ 371 CLK_GATE(_name, _parent, \ 372 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 373 _bits) 374 375 #define CLK_GATE_W(_name, _parent, _bits) \ 376 CLK_GATE(_name, _parent, \ 377 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 378 _bits) 379 380 #define CLK_GATE_X(_name, _parent, _bits) \ 381 CLK_GATE(_name, _parent, \ 382 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 383 _bits) 384 385 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 386 CLK_GATE(_name, _parent, _reg, _reg, _bits) 387 388 static const char *mux_uart_p[] = 389 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 390 "pll_m_out0", NULL, "clk_m" }; 391 static const char *mux_sdmmc_p[] = 392 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 393 "pll_m_out0", "pll_e_out0", "clk_m" }; 394 static const char *mux_i2c_p[] = 395 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 396 "pll_m_out0", NULL, "clk_m" }; 397 static const char *mux_spi_p[] = 398 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 399 "pll_m_out0", NULL, "clk_m" }; 400 static const char *mux_sata_p[] = 401 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 402 static const char *mux_hda_p[] = 403 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 404 "pll_m_out0", NULL, "clk_m" }; 405 static const char *mux_tsensor_p[] = 406 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 407 NULL, "clk_s" }; 408 static const char *mux_soc_therm_p[] = 409 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 410 "pll_c3_out0" }; 411 static const char *mux_host1x_p[] = 412 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 413 "pll_p_out0", NULL, "pll_a_out0" }; 414 static const char *mux_disp_p[] = 415 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 416 "pll_d2_out0", "clk_m" }; 417 static const char *mux_hdmi_p[] = 418 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 419 "pll_d2_out0", "clk_m" }; 420 static const char *mux_xusb_host_p[] = 421 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 422 "pll_re_out" }; 423 static const char *mux_xusb_ss_p[] = 424 { "clk_m", "pll_re_out", "clk_s", "pll_u_480", 425 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL }; 426 static const char *mux_xusb_fs_p[] = 427 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" }; 428 429 static struct tegra_clk tegra124_car_clocks[] = { 430 CLK_FIXED("clk_m", TEGRA_REF_FREQ), 431 432 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 433 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 434 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 435 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 436 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 437 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 438 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 439 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 440 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 441 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 442 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 443 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 444 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 445 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 446 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG, 447 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 448 449 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 450 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 451 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 452 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 453 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 454 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 455 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 456 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 457 CLK_FIXED_DIV("pll_re_out", "pll_re", 1), 458 459 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 460 mux_uart_p), 461 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 462 mux_uart_p), 463 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 464 mux_uart_p), 465 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 466 mux_uart_p), 467 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 468 mux_sdmmc_p), 469 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 470 mux_sdmmc_p), 471 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc_p), 473 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc_p), 475 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 476 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 477 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 478 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 479 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 480 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 482 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 483 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 484 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 485 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 486 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 487 CLK_MUX("mux_sata_oob", 488 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 489 CLK_MUX("mux_sata", 490 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 491 CLK_MUX("mux_hda2codec_2x", 492 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 493 mux_hda_p), 494 CLK_MUX("mux_hda", 495 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 496 CLK_MUX("mux_soc_therm", 497 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 498 mux_soc_therm_p), 499 CLK_MUX("mux_tsensor", 500 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 501 mux_tsensor_p), 502 CLK_MUX("mux_host1x", 503 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 504 mux_host1x_p), 505 CLK_MUX("mux_disp1", 506 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 507 mux_disp_p), 508 CLK_MUX("mux_disp2", 509 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 510 mux_disp_p), 511 CLK_MUX("mux_hdmi", 512 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 513 mux_hdmi_p), 514 CLK_MUX("mux_xusb_host", 515 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 516 mux_xusb_host_p), 517 CLK_MUX("mux_xusb_falcon", 518 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 519 mux_xusb_host_p), 520 CLK_MUX("mux_xusb_ss", 521 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 522 mux_xusb_ss_p), 523 CLK_MUX("mux_xusb_fs", 524 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 525 mux_xusb_fs_p), 526 527 CLK_DIV("div_uarta", "mux_uarta", 528 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 529 CLK_DIV("div_uartb", "mux_uartb", 530 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 531 CLK_DIV("div_uartc", "mux_uartc", 532 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 533 CLK_DIV("div_uartd", "mux_uartd", 534 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 535 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 536 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 537 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 538 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 539 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 540 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 541 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 542 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 543 CLK_DIV("div_i2c1", "mux_i2c1", 544 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 545 CLK_DIV("div_i2c2", "mux_i2c2", 546 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 547 CLK_DIV("div_i2c3", "mux_i2c3", 548 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 549 CLK_DIV("div_i2c4", "mux_i2c4", 550 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 551 CLK_DIV("div_i2c5", "mux_i2c5", 552 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 553 CLK_DIV("div_i2c6", "mux_i2c6", 554 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 555 CLK_DIV("div_spi1", "mux_spi1", 556 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV), 557 CLK_DIV("div_spi2", "mux_spi2", 558 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV), 559 CLK_DIV("div_spi3", "mux_spi3", 560 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV), 561 CLK_DIV("div_spi4", "mux_spi4", 562 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV), 563 CLK_DIV("div_spi5", "mux_spi5", 564 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV), 565 CLK_DIV("div_spi6", "mux_spi6", 566 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV), 567 CLK_DIV("div_sata_oob", "mux_sata_oob", 568 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 569 CLK_DIV("div_sata", "mux_sata", 570 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 571 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 572 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 573 CLK_DIV("div_hda", "mux_hda", 574 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 575 CLK_DIV("div_soc_therm", "mux_soc_therm", 576 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 577 CLK_DIV("div_tsensor", "mux_tsensor", 578 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 579 CLK_DIV("div_host1x", "mux_host1x", 580 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 581 CLK_DIV("div_hdmi", "mux_hdmi", 582 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 583 CLK_DIV("div_pll_p_out5", "pll_p", 584 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 585 CLK_DIV("xusb_host_src", "mux_xusb_host", 586 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 587 CLK_DIV("xusb_ss_src", "mux_xusb_ss", 588 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 589 CLK_DIV("xusb_fs_src", "mux_xusb_fs", 590 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 591 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon", 592 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 593 594 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 595 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 596 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 597 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 598 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 599 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 600 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 601 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 602 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 603 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 604 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 605 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 606 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 607 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 608 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1), 609 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2), 610 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3), 611 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4), 612 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5), 613 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6), 614 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 615 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 616 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 617 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 618 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 619 CLK_GATE_SIMPLE("cml0", "pll_e", 620 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 621 CLK_GATE_SIMPLE("cml1", "pll_e", 622 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 623 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 624 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 625 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 626 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 627 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 628 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 629 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 630 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 631 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 632 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 633 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5", 634 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 635 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST), 636 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS), 637 CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU), 638 }; 639 640 struct tegra124_init_parent { 641 const char *clock; 642 const char *parent; 643 } tegra124_init_parents[] = { 644 { "sata_oob", "pll_p_out0" }, 645 { "sata", "pll_p_out0" }, 646 { "hda", "pll_p_out0" }, 647 { "hda2codec_2x", "pll_p_out0" }, 648 { "soc_therm", "pll_p_out0" }, 649 { "tsensor", "clk_m" }, 650 { "xusb_host_src", "pll_p_out0" }, 651 { "xusb_falcon_src", "pll_p_out0" }, 652 { "xusb_ss_src", "pll_u_480" }, 653 { "xusb_fs_src", "pll_u_48" }, 654 }; 655 656 struct tegra124_car_rst { 657 u_int set_reg; 658 u_int clr_reg; 659 u_int mask; 660 }; 661 662 static struct tegra124_car_reset_reg { 663 u_int set_reg; 664 u_int clr_reg; 665 } tegra124_car_reset_regs[] = { 666 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 667 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 668 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 669 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 670 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 671 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 672 }; 673 674 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 675 static void tegra124_car_reset_release(device_t, void *); 676 static int tegra124_car_reset_assert(device_t, void *); 677 static int tegra124_car_reset_deassert(device_t, void *); 678 679 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 680 .acquire = tegra124_car_reset_acquire, 681 .release = tegra124_car_reset_release, 682 .reset_assert = tegra124_car_reset_assert, 683 .reset_deassert = tegra124_car_reset_deassert, 684 }; 685 686 struct tegra124_car_softc { 687 device_t sc_dev; 688 bus_space_tag_t sc_bst; 689 bus_space_handle_t sc_bsh; 690 691 struct clk_domain sc_clkdom; 692 693 u_int sc_clock_cells; 694 u_int sc_reset_cells; 695 696 kmutex_t sc_rndlock; 697 krndsource_t sc_rndsource; 698 }; 699 700 static void tegra124_car_init(struct tegra124_car_softc *); 701 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 702 static void tegra124_car_xusb_init(struct tegra124_car_softc *); 703 static void tegra124_car_watchdog_init(struct tegra124_car_softc *); 704 static void tegra124_car_parent_init(struct tegra124_car_softc *); 705 706 static void tegra124_car_rnd_attach(device_t); 707 static void tegra124_car_rnd_callback(size_t, void *); 708 709 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 710 tegra124_car_match, tegra124_car_attach, NULL, NULL); 711 712 static int 713 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 714 { 715 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 716 struct fdt_attach_args * const faa = aux; 717 718 #if 0 719 return of_match_compatible(faa->faa_phandle, compatible); 720 #else 721 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 722 return 0; 723 724 return 999; 725 #endif 726 } 727 728 static void 729 tegra124_car_attach(device_t parent, device_t self, void *aux) 730 { 731 struct tegra124_car_softc * const sc = device_private(self); 732 struct fdt_attach_args * const faa = aux; 733 const int phandle = faa->faa_phandle; 734 bus_addr_t addr; 735 bus_size_t size; 736 int error, n; 737 738 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 739 aprint_error(": couldn't get registers\n"); 740 return; 741 } 742 743 sc->sc_dev = self; 744 sc->sc_bst = faa->faa_bst; 745 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 746 if (error) { 747 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 748 return; 749 } 750 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 751 sc->sc_clock_cells = 1; 752 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 753 sc->sc_reset_cells = 1; 754 755 aprint_naive("\n"); 756 aprint_normal(": CAR\n"); 757 758 sc->sc_clkdom.funcs = &tegra124_car_clock_funcs; 759 sc->sc_clkdom.priv = sc; 760 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) 761 tegra124_car_clocks[n].base.domain = &sc->sc_clkdom; 762 763 fdtbus_register_clock_controller(self, phandle, 764 &tegra124_car_fdtclock_funcs); 765 fdtbus_register_reset_controller(self, phandle, 766 &tegra124_car_fdtreset_funcs); 767 768 tegra124_car_init(sc); 769 770 config_interrupts(self, tegra124_car_rnd_attach); 771 } 772 773 static void 774 tegra124_car_init(struct tegra124_car_softc *sc) 775 { 776 tegra124_car_parent_init(sc); 777 tegra124_car_utmip_init(sc); 778 tegra124_car_xusb_init(sc); 779 tegra124_car_watchdog_init(sc); 780 } 781 782 static void 783 tegra124_car_parent_init(struct tegra124_car_softc *sc) 784 { 785 struct clk *clk, *clk_parent; 786 int error; 787 u_int n; 788 789 for (n = 0; n < __arraycount(tegra124_init_parents); n++) { 790 clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock); 791 KASSERT(clk != NULL); 792 clk_parent = clk_get(&sc->sc_clkdom, 793 tegra124_init_parents[n].parent); 794 KASSERT(clk_parent != NULL); 795 796 error = clk_set_parent(clk, clk_parent); 797 if (error) { 798 aprint_error_dev(sc->sc_dev, 799 "couldn't set '%s' parent to '%s': %d\n", 800 clk->name, clk_parent->name, error); 801 } 802 clk_put(clk_parent); 803 clk_put(clk); 804 } 805 } 806 807 static void 808 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 809 { 810 bus_space_tag_t bst = sc->sc_bst; 811 bus_space_handle_t bsh = sc->sc_bsh; 812 813 const u_int enable_dly_count = 0x02; 814 const u_int stable_count = 0x2f; 815 const u_int active_dly_count = 0x04; 816 const u_int xtal_freq_count = 0x76; 817 818 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 819 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 820 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 821 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 822 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 823 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 824 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 825 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 826 827 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 828 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 829 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 830 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 831 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 832 833 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 834 0, 835 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 836 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 837 838 } 839 840 static void 841 tegra124_car_xusb_init(struct tegra124_car_softc *sc) 842 { 843 const bus_space_tag_t bst = sc->sc_bst; 844 const bus_space_handle_t bsh = sc->sc_bsh; 845 uint32_t val; 846 847 /* XXX do this all better */ 848 849 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 850 851 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 852 0, CAR_PLLREFE_MISC_IDDQ); 853 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 854 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 855 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 856 857 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 858 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 859 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 860 CAR_PLLREFE_BASE_ENABLE, 0); 861 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 862 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 863 864 do { 865 delay(2); 866 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 867 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 868 869 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 870 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 871 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 872 CAR_PLLE_BASE_ENABLE, 0); 873 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 874 CAR_PLLE_MISC_LOCK_ENABLE, 0); 875 876 do { 877 delay(2); 878 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 879 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 880 881 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 882 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 883 } 884 885 static void 886 tegra124_car_watchdog_init(struct tegra124_car_softc *sc) 887 { 888 const bus_space_tag_t bst = sc->sc_bst; 889 const bus_space_handle_t bsh = sc->sc_bsh; 890 891 /* Enable watchdog timer reset for system */ 892 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 893 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 894 } 895 896 static void 897 tegra124_car_rnd_attach(device_t self) 898 { 899 struct tegra124_car_softc * const sc = device_private(self); 900 901 mutex_init(&sc->sc_rndlock, MUTEX_DEFAULT, IPL_VM); 902 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 903 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 904 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 905 tegra124_car_rnd_callback(RND_POOLBITS / NBBY, sc); 906 } 907 908 static void 909 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 910 { 911 struct tegra124_car_softc * const sc = priv; 912 uint16_t buf[512]; 913 uint32_t cnt; 914 915 mutex_enter(&sc->sc_rndlock); 916 while (bytes_wanted) { 917 const u_int nbytes = MIN(bytes_wanted, 1024); 918 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) { 919 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 920 CAR_PLL_LFSR_REG) & 0xffff; 921 } 922 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes, 923 nbytes * NBBY); 924 bytes_wanted -= MIN(bytes_wanted, nbytes); 925 } 926 explicit_memset(buf, 0, sizeof(buf)); 927 mutex_exit(&sc->sc_rndlock); 928 } 929 930 static struct tegra_clk * 931 tegra124_car_clock_find(const char *name) 932 { 933 u_int n; 934 935 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 936 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 937 return &tegra124_car_clocks[n]; 938 } 939 } 940 941 return NULL; 942 } 943 944 static struct tegra_clk * 945 tegra124_car_clock_find_by_id(u_int clock_id) 946 { 947 u_int n; 948 949 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 950 if (tegra124_car_clock_ids[n].id == clock_id) { 951 const char *name = tegra124_car_clock_ids[n].name; 952 return tegra124_car_clock_find(name); 953 } 954 } 955 956 return NULL; 957 } 958 959 static struct clk * 960 tegra124_car_clock_decode(device_t dev, const void *data, size_t len) 961 { 962 struct tegra124_car_softc * const sc = device_private(dev); 963 struct tegra_clk *tclk; 964 965 if (len != sc->sc_clock_cells * 4) { 966 return NULL; 967 } 968 969 const u_int clock_id = be32dec(data); 970 971 tclk = tegra124_car_clock_find_by_id(clock_id); 972 if (tclk) 973 return TEGRA_CLK_BASE(tclk); 974 975 return NULL; 976 } 977 978 static struct clk * 979 tegra124_car_clock_get(void *priv, const char *name) 980 { 981 struct tegra_clk *tclk; 982 983 tclk = tegra124_car_clock_find(name); 984 if (tclk == NULL) 985 return NULL; 986 987 atomic_inc_uint(&tclk->refcnt); 988 989 return TEGRA_CLK_BASE(tclk); 990 } 991 992 static void 993 tegra124_car_clock_put(void *priv, struct clk *clk) 994 { 995 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 996 997 KASSERT(tclk->refcnt > 0); 998 999 atomic_dec_uint(&tclk->refcnt); 1000 } 1001 1002 static u_int 1003 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 1004 struct tegra_clk *tclk) 1005 { 1006 struct tegra_pll_clk *tpll = &tclk->u.pll; 1007 struct tegra_clk *tclk_parent; 1008 bus_space_tag_t bst = sc->sc_bst; 1009 bus_space_handle_t bsh = sc->sc_bsh; 1010 u_int divm, divn, divp; 1011 uint64_t rate; 1012 1013 KASSERT(tclk->type == TEGRA_CLK_PLL); 1014 1015 tclk_parent = tegra124_car_clock_find(tclk->parent); 1016 KASSERT(tclk_parent != NULL); 1017 1018 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 1019 TEGRA_CLK_BASE(tclk_parent)); 1020 1021 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1022 divm = __SHIFTOUT(base, tpll->divm_mask); 1023 divn = __SHIFTOUT(base, tpll->divn_mask); 1024 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1025 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1026 } else { 1027 divp = __SHIFTOUT(base, tpll->divp_mask); 1028 } 1029 1030 rate = (uint64_t)rate_parent * divn; 1031 return rate / (divm << divp); 1032 } 1033 1034 static int 1035 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 1036 struct tegra_clk *tclk, u_int rate) 1037 { 1038 struct tegra_pll_clk *tpll = &tclk->u.pll; 1039 bus_space_tag_t bst = sc->sc_bst; 1040 bus_space_handle_t bsh = sc->sc_bsh; 1041 struct clk *clk_parent; 1042 uint32_t bp, base; 1043 1044 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1045 if (clk_parent == NULL) 1046 return EIO; 1047 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 1048 if (rate_parent == 0) 1049 return EIO; 1050 1051 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1052 const u_int divm = 1; 1053 const u_int divn = rate / rate_parent; 1054 const u_int divp = 0; 1055 1056 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1057 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1058 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1059 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1060 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1061 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1062 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1063 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1064 1065 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1066 base &= ~CAR_PLLX_BASE_DIVM; 1067 base &= ~CAR_PLLX_BASE_DIVN; 1068 base &= ~CAR_PLLX_BASE_DIVP; 1069 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1070 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1071 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1072 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1073 1074 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1075 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1076 do { 1077 delay(2); 1078 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1079 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1080 delay(100); 1081 1082 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1083 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1084 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1085 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1086 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1087 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1088 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1089 1090 return 0; 1091 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1092 const u_int divm = 1; 1093 const u_int pldiv = 1; 1094 const u_int divn = (rate << pldiv) / rate_parent; 1095 1096 /* Set frequency */ 1097 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1098 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1099 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1100 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1101 CAR_PLLD2_BASE_REF_SRC_SEL | 1102 CAR_PLLD2_BASE_DIVM | 1103 CAR_PLLD2_BASE_DIVN | 1104 CAR_PLLD2_BASE_DIVP); 1105 1106 return 0; 1107 } else { 1108 /* TODO */ 1109 return EOPNOTSUPP; 1110 } 1111 } 1112 1113 static int 1114 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 1115 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1116 { 1117 struct tegra_mux_clk *tmux = &tclk->u.mux; 1118 bus_space_tag_t bst = sc->sc_bst; 1119 bus_space_handle_t bsh = sc->sc_bsh; 1120 uint32_t v; 1121 u_int src; 1122 1123 KASSERT(tclk->type == TEGRA_CLK_MUX); 1124 1125 for (src = 0; src < tmux->nparents; src++) { 1126 if (tmux->parents[src] == NULL) { 1127 continue; 1128 } 1129 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1130 break; 1131 } 1132 } 1133 if (src == tmux->nparents) { 1134 return EINVAL; 1135 } 1136 1137 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1138 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1139 /* Change IDDQ from 1 to 0 */ 1140 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1141 0, CAR_PLLD2_BASE_IDDQ); 1142 delay(2); 1143 1144 /* Enable lock */ 1145 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1146 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1147 1148 /* Enable PLLD2 */ 1149 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1150 CAR_PLLD2_BASE_ENABLE, 0); 1151 1152 /* Wait for lock */ 1153 do { 1154 delay(2); 1155 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1156 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1157 1158 delay(200); 1159 } 1160 1161 v = bus_space_read_4(bst, bsh, tmux->reg); 1162 v &= ~tmux->bits; 1163 v |= __SHIFTIN(src, tmux->bits); 1164 bus_space_write_4(bst, bsh, tmux->reg, v); 1165 1166 return 0; 1167 } 1168 1169 static struct tegra_clk * 1170 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1171 struct tegra_clk *tclk) 1172 { 1173 struct tegra_mux_clk *tmux = &tclk->u.mux; 1174 bus_space_tag_t bst = sc->sc_bst; 1175 bus_space_handle_t bsh = sc->sc_bsh; 1176 1177 KASSERT(tclk->type == TEGRA_CLK_MUX); 1178 1179 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1180 const u_int src = __SHIFTOUT(v, tmux->bits); 1181 1182 KASSERT(src < tmux->nparents); 1183 1184 if (tmux->parents[src] == NULL) { 1185 return NULL; 1186 } 1187 1188 return tegra124_car_clock_find(tmux->parents[src]); 1189 } 1190 1191 static u_int 1192 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1193 struct tegra_clk *tclk) 1194 { 1195 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1196 struct clk *clk_parent; 1197 1198 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1199 if (clk_parent == NULL) 1200 return 0; 1201 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1202 1203 return parent_rate / tfixed_div->div; 1204 } 1205 1206 static u_int 1207 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1208 struct tegra_clk *tclk) 1209 { 1210 struct tegra_div_clk *tdiv = &tclk->u.div; 1211 bus_space_tag_t bst = sc->sc_bst; 1212 bus_space_handle_t bsh = sc->sc_bsh; 1213 struct clk *clk_parent; 1214 u_int rate; 1215 1216 KASSERT(tclk->type == TEGRA_CLK_DIV); 1217 1218 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1219 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1220 1221 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1222 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1223 1224 switch (tdiv->reg) { 1225 case CAR_CLKSRC_I2C1_REG: 1226 case CAR_CLKSRC_I2C2_REG: 1227 case CAR_CLKSRC_I2C3_REG: 1228 case CAR_CLKSRC_I2C4_REG: 1229 case CAR_CLKSRC_I2C5_REG: 1230 case CAR_CLKSRC_I2C6_REG: 1231 rate = parent_rate * 1 / (raw_div + 1); 1232 break; 1233 case CAR_CLKSRC_UARTA_REG: 1234 case CAR_CLKSRC_UARTB_REG: 1235 case CAR_CLKSRC_UARTC_REG: 1236 case CAR_CLKSRC_UARTD_REG: 1237 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1238 rate = parent_rate * 2 / (raw_div + 2); 1239 } else { 1240 rate = parent_rate; 1241 } 1242 break; 1243 default: 1244 rate = parent_rate * 2 / (raw_div + 2); 1245 break; 1246 } 1247 1248 return rate; 1249 } 1250 1251 static int 1252 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1253 struct tegra_clk *tclk, u_int rate) 1254 { 1255 struct tegra_div_clk *tdiv = &tclk->u.div; 1256 bus_space_tag_t bst = sc->sc_bst; 1257 bus_space_handle_t bsh = sc->sc_bsh; 1258 struct clk *clk_parent; 1259 u_int raw_div; 1260 uint32_t v; 1261 1262 KASSERT(tclk->type == TEGRA_CLK_DIV); 1263 1264 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1265 if (clk_parent == NULL) 1266 return EINVAL; 1267 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1268 1269 v = bus_space_read_4(bst, bsh, tdiv->reg); 1270 1271 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1272 1273 switch (tdiv->reg) { 1274 case CAR_CLKSRC_UARTA_REG: 1275 case CAR_CLKSRC_UARTB_REG: 1276 case CAR_CLKSRC_UARTC_REG: 1277 case CAR_CLKSRC_UARTD_REG: 1278 if (rate == parent_rate) { 1279 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1280 } else { 1281 v |= CAR_CLKSRC_UART_DIV_ENB; 1282 raw_div = (parent_rate * 2) / rate - 2; 1283 } 1284 break; 1285 case CAR_CLKSRC_SATA_REG: 1286 if (rate) { 1287 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1288 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1289 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1290 raw_div = (parent_rate * 2) / rate - 2; 1291 } else { 1292 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1293 } 1294 break; 1295 case CAR_CLKSRC_I2C1_REG: 1296 case CAR_CLKSRC_I2C2_REG: 1297 case CAR_CLKSRC_I2C3_REG: 1298 case CAR_CLKSRC_I2C4_REG: 1299 case CAR_CLKSRC_I2C5_REG: 1300 case CAR_CLKSRC_I2C6_REG: 1301 if (rate) 1302 raw_div = parent_rate / rate - 1; 1303 break; 1304 default: 1305 if (rate) 1306 raw_div = (parent_rate * 2) / rate - 2; 1307 break; 1308 } 1309 1310 v &= ~tdiv->bits; 1311 v |= __SHIFTIN(raw_div, tdiv->bits); 1312 1313 bus_space_write_4(bst, bsh, tdiv->reg, v); 1314 1315 return 0; 1316 } 1317 1318 static int 1319 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1320 struct tegra_clk *tclk, bool enable) 1321 { 1322 struct tegra_gate_clk *tgate = &tclk->u.gate; 1323 bus_space_tag_t bst = sc->sc_bst; 1324 bus_space_handle_t bsh = sc->sc_bsh; 1325 bus_size_t reg; 1326 1327 KASSERT(tclk->type == TEGRA_CLK_GATE); 1328 1329 if (tgate->set_reg == tgate->clr_reg) { 1330 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1331 if (enable) { 1332 v |= tgate->bits; 1333 } else { 1334 v &= ~tgate->bits; 1335 } 1336 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1337 } else { 1338 if (enable) { 1339 reg = tgate->set_reg; 1340 } else { 1341 reg = tgate->clr_reg; 1342 } 1343 1344 if (reg == CAR_CLK_ENB_V_SET_REG && 1345 tgate->bits == CAR_DEV_V_SATA) { 1346 /* De-assert reset to SATA PADPLL */ 1347 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1348 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1349 delay(15); 1350 } 1351 bus_space_write_4(bst, bsh, reg, tgate->bits); 1352 } 1353 1354 return 0; 1355 } 1356 1357 static u_int 1358 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1359 { 1360 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1361 struct clk *clk_parent; 1362 1363 switch (tclk->type) { 1364 case TEGRA_CLK_FIXED: 1365 return tclk->u.fixed.rate; 1366 case TEGRA_CLK_PLL: 1367 return tegra124_car_clock_get_rate_pll(priv, tclk); 1368 case TEGRA_CLK_MUX: 1369 case TEGRA_CLK_GATE: 1370 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1371 if (clk_parent == NULL) 1372 return EINVAL; 1373 return tegra124_car_clock_get_rate(priv, clk_parent); 1374 case TEGRA_CLK_FIXED_DIV: 1375 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1376 case TEGRA_CLK_DIV: 1377 return tegra124_car_clock_get_rate_div(priv, tclk); 1378 default: 1379 panic("tegra124: unknown tclk type %d", tclk->type); 1380 } 1381 } 1382 1383 static int 1384 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1385 { 1386 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1387 struct clk *clk_parent; 1388 1389 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1390 1391 switch (tclk->type) { 1392 case TEGRA_CLK_FIXED: 1393 case TEGRA_CLK_MUX: 1394 return EIO; 1395 case TEGRA_CLK_FIXED_DIV: 1396 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1397 if (clk_parent == NULL) 1398 return EIO; 1399 return tegra124_car_clock_set_rate(priv, clk_parent, 1400 rate * tclk->u.fixed_div.div); 1401 case TEGRA_CLK_GATE: 1402 return EINVAL; 1403 case TEGRA_CLK_PLL: 1404 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1405 case TEGRA_CLK_DIV: 1406 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1407 default: 1408 panic("tegra124: unknown tclk type %d", tclk->type); 1409 } 1410 } 1411 1412 static int 1413 tegra124_car_clock_enable(void *priv, struct clk *clk) 1414 { 1415 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1416 struct clk *clk_parent; 1417 1418 if (tclk->type != TEGRA_CLK_GATE) { 1419 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1420 if (clk_parent == NULL) 1421 return 0; 1422 return tegra124_car_clock_enable(priv, clk_parent); 1423 } 1424 1425 return tegra124_car_clock_enable_gate(priv, tclk, true); 1426 } 1427 1428 static int 1429 tegra124_car_clock_disable(void *priv, struct clk *clk) 1430 { 1431 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1432 1433 if (tclk->type != TEGRA_CLK_GATE) 1434 return EINVAL; 1435 1436 return tegra124_car_clock_enable_gate(priv, tclk, false); 1437 } 1438 1439 static int 1440 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1441 struct clk *clk_parent) 1442 { 1443 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1444 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1445 struct clk *nclk_parent; 1446 1447 if (tclk->type != TEGRA_CLK_MUX) { 1448 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1449 if (nclk_parent == clk_parent || nclk_parent == NULL) 1450 return EINVAL; 1451 return tegra124_car_clock_set_parent(priv, nclk_parent, 1452 clk_parent); 1453 } 1454 1455 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1456 } 1457 1458 static struct clk * 1459 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1460 { 1461 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1462 struct tegra_clk *tclk_parent = NULL; 1463 1464 switch (tclk->type) { 1465 case TEGRA_CLK_FIXED: 1466 case TEGRA_CLK_PLL: 1467 case TEGRA_CLK_FIXED_DIV: 1468 case TEGRA_CLK_DIV: 1469 case TEGRA_CLK_GATE: 1470 if (tclk->parent) { 1471 tclk_parent = tegra124_car_clock_find(tclk->parent); 1472 } 1473 break; 1474 case TEGRA_CLK_MUX: 1475 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1476 break; 1477 } 1478 1479 if (tclk_parent == NULL) 1480 return NULL; 1481 1482 return TEGRA_CLK_BASE(tclk_parent); 1483 } 1484 1485 static void * 1486 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1487 { 1488 struct tegra124_car_softc * const sc = device_private(dev); 1489 struct tegra124_car_rst *rst; 1490 1491 if (len != sc->sc_reset_cells * 4) 1492 return NULL; 1493 1494 const u_int reset_id = be32dec(data); 1495 1496 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32) 1497 return NULL; 1498 1499 const u_int reg = reset_id / 32; 1500 1501 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1502 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1503 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1504 rst->mask = __BIT(reset_id % 32); 1505 1506 return rst; 1507 } 1508 1509 static void 1510 tegra124_car_reset_release(device_t dev, void *priv) 1511 { 1512 struct tegra124_car_rst *rst = priv; 1513 1514 kmem_free(rst, sizeof(*rst)); 1515 } 1516 1517 static int 1518 tegra124_car_reset_assert(device_t dev, void *priv) 1519 { 1520 struct tegra124_car_softc * const sc = device_private(dev); 1521 struct tegra124_car_rst *rst = priv; 1522 1523 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1524 1525 return 0; 1526 } 1527 1528 static int 1529 tegra124_car_reset_deassert(device_t dev, void *priv) 1530 { 1531 struct tegra124_car_softc * const sc = device_private(dev); 1532 struct tegra124_car_rst *rst = priv; 1533 1534 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1535 1536 return 0; 1537 } 1538
Indexes created Tue Sep 30 20:09:53 GMT 2025