tegra124_car.c revision 1.12
1 /* $NetBSD: tegra124_car.c,v 1.12 2017/04/26 01:43:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.12 2017/04/26 01:43:00 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra124_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra124_car_match(device_t, cfdata_t, void *); 54 static void tegra124_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra124_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 59 .decode = tegra124_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra124_car_clock_id { 64 u_int id; 65 const char *name; 66 } tegra124_car_clock_ids[] = { 67 { 3, "ispb" }, 68 { 4, "rtc" }, 69 { 5, "timer" }, 70 { 6, "uarta" }, 71 { 9, "sdmmc2" }, 72 { 11, "i2s1" }, 73 { 12, "i2c1" }, 74 { 14, "sdmmc1" }, 75 { 15, "sdmmc4" }, 76 { 17, "pwm" }, 77 { 18, "i2s2" }, 78 { 22, "usbd" }, 79 { 23, "isp" }, 80 { 26, "disp2" }, 81 { 27, "disp1" }, 82 { 28, "host1x" }, 83 { 29, "vcp" }, 84 { 30, "i2s0" }, 85 { 32, "mc" }, 86 { 34, "apbdma" }, 87 { 36, "kbc" }, 88 { 40, "kfuse" }, 89 { 41, "spi1" }, 90 { 42, "nor" }, 91 { 44, "spi2" }, 92 { 46, "spi3" }, 93 { 47, "i2c5" }, 94 { 48, "dsia" }, 95 { 50, "mipi" }, 96 { 51, "hdmi" }, 97 { 52, "csi" }, 98 { 54, "i2c2" }, 99 { 55, "uartc" }, 100 { 56, "mipi_cal" }, 101 { 57, "emc" }, 102 { 58, "usb2" }, 103 { 59, "usb3" }, 104 { 61, "vde" }, 105 { 62, "bsea" }, 106 { 63, "bsev" }, 107 { 65, "uartd" }, 108 { 67, "i2c3" }, 109 { 68, "spi4" }, 110 { 69, "sdmmc3" }, 111 { 70, "pcie" }, 112 { 71, "owr" }, 113 { 72, "afi" }, 114 { 73, "csite" }, 115 { 76, "la" }, 116 { 77, "trace" }, 117 { 78, "soc_therm" }, 118 { 79, "dtv" }, 119 { 81, "i2cslow" }, 120 { 82, "dsib" }, 121 { 83, "tsec" }, 122 { 89, "xusb_host" }, 123 { 91, "msenc" }, 124 { 92, "csus" }, 125 { 99, "mselect" }, 126 { 100, "tsensor" }, 127 { 101, "i2s3" }, 128 { 102, "i2s4" }, 129 { 103, "i2c4" }, 130 { 104, "spi5" }, 131 { 105, "spi6" }, 132 { 106, "d_audio" }, 133 { 107, "apbif" }, 134 { 108, "dam0" }, 135 { 109, "dam1" }, 136 { 110, "dam2" }, 137 { 111, "hda2codec_2x" }, 138 { 113, "audio0_2x" }, 139 { 114, "audio1_2x" }, 140 { 115, "audio2_2x" }, 141 { 116, "audio3_2x" }, 142 { 117, "audio4_2x" }, 143 { 118, "spdif_2x" }, 144 { 119, "actmon" }, 145 { 120, "extern1" }, 146 { 121, "extern2" }, 147 { 122, "extern3" }, 148 { 123, "sata_oob" }, 149 { 124, "sata" }, 150 { 125, "hda" }, 151 { 127, "se" }, 152 { 128, "hda2hdmi" }, 153 { 129, "sata_cold" }, 154 { 144, "cilab" }, 155 { 145, "cilcd" }, 156 { 146, "cile" }, 157 { 147, "dsialp" }, 158 { 148, "dsiblp" }, 159 { 149, "entropy" }, 160 { 150, "dds" }, 161 { 152, "dp2" }, 162 { 153, "amx" }, 163 { 154, "adx" }, 164 { 156, "xusb_ss" }, 165 { 166, "i2c6" }, 166 { 171, "vim2_clk" }, 167 { 176, "hdmi_audio" }, 168 { 177, "clk72mhz" }, 169 { 178, "vic03" }, 170 { 180, "adx1" }, 171 { 181, "dpaux" }, 172 { 182, "sor0" }, 173 { 184, "gpu" }, 174 { 185, "amx1" }, 175 { 192, "uartb" }, 176 { 193, "vfir" }, 177 { 194, "spdif_in" }, 178 { 195, "spdif_out" }, 179 { 196, "vi" }, 180 { 197, "vi_sensor" }, 181 { 198, "fuse" }, 182 { 199, "fuse_burn" }, 183 { 200, "clk_32k" }, 184 { 201, "clk_m" }, 185 { 202, "clk_m_div2" }, 186 { 203, "clk_m_div4" }, 187 { 204, "pll_ref" }, 188 { 205, "pll_c" }, 189 { 206, "pll_c_out1" }, 190 { 207, "pll_c2" }, 191 { 208, "pll_c3" }, 192 { 209, "pll_m" }, 193 { 210, "pll_m_out1" }, 194 { 211, "pll_p_out0" }, 195 { 212, "pll_p_out1" }, 196 { 213, "pll_p_out2" }, 197 { 214, "pll_p_out3" }, 198 { 215, "pll_p_out4" }, 199 { 216, "pll_a" }, 200 { 217, "pll_a_out0" }, 201 { 218, "pll_d" }, 202 { 219, "pll_d_out0" }, 203 { 220, "pll_d2" }, 204 { 221, "pll_d2_out0" }, 205 { 222, "pll_u" }, 206 { 223, "pll_u_480m" }, 207 { 224, "pll_u_60m" }, 208 { 225, "pll_u_48m" }, 209 { 226, "pll_u_12m" }, 210 { 229, "pll_re_vco" }, 211 { 230, "pll_re_out" }, 212 { 231, "pll_e" }, 213 { 232, "spdif_in_sync" }, 214 { 233, "i2s0_sync" }, 215 { 234, "i2s1_sync" }, 216 { 235, "i2s2_sync" }, 217 { 236, "i2s3_sync" }, 218 { 237, "i2s4_sync" }, 219 { 238, "vimclk_sync" }, 220 { 239, "audio0" }, 221 { 240, "audio1" }, 222 { 241, "audio2" }, 223 { 242, "audio3" }, 224 { 243, "audio4" }, 225 { 244, "spdif" }, 226 { 245, "clk_out_1" }, 227 { 246, "clk_out_2" }, 228 { 247, "clk_out_3" }, 229 { 248, "blink" }, 230 { 252, "xusb_host_src" }, 231 { 253, "xusb_falcon_src" }, 232 { 254, "xusb_fs_src" }, 233 { 255, "xusb_ss_src" }, 234 { 256, "xusb_dev_src" }, 235 { 257, "xusb_dev" }, 236 { 258, "xusb_hs_src" }, 237 { 259, "sclk" }, 238 { 260, "hclk" }, 239 { 261, "pclk" }, 240 { 264, "dfll_ref" }, 241 { 265, "dfll_soc" }, 242 { 266, "vi_sensor2" }, 243 { 267, "pll_p_out5" }, 244 { 268, "cml0" }, 245 { 269, "cml1" }, 246 { 270, "pll_c4" }, 247 { 271, "pll_dp" }, 248 { 272, "pll_e_mux" }, 249 { 273, "pll_d_dsi_out" }, 250 { 300, "audio0_mux" }, 251 { 301, "audio1_mux" }, 252 { 302, "audio2_mux" }, 253 { 303, "audio3_mux" }, 254 { 304, "audio4_mux" }, 255 { 305, "spdif_mux" }, 256 { 306, "clk_out_1_mux" }, 257 { 307, "clk_out_2_mux" }, 258 { 308, "clk_out_3_mux" }, 259 { 311, "sor0_lvds" }, 260 { 312, "xusb_ss_div2" }, 261 { 313, "pll_m_ud" }, 262 { 314, "pll_c_ud" }, 263 { 227, "pll_x" }, 264 { 228, "pll_x_out0" }, 265 { 262, "cclk_g" }, 266 { 263, "cclk_lp" }, 267 { 315, "clk_max" }, 268 }; 269 270 static struct clk *tegra124_car_clock_get(void *, const char *); 271 static void tegra124_car_clock_put(void *, struct clk *); 272 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 273 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 274 static int tegra124_car_clock_enable(void *, struct clk *); 275 static int tegra124_car_clock_disable(void *, struct clk *); 276 static int tegra124_car_clock_set_parent(void *, struct clk *, 277 struct clk *); 278 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 279 280 static const struct clk_funcs tegra124_car_clock_funcs = { 281 .get = tegra124_car_clock_get, 282 .put = tegra124_car_clock_put, 283 .get_rate = tegra124_car_clock_get_rate, 284 .set_rate = tegra124_car_clock_set_rate, 285 .enable = tegra124_car_clock_enable, 286 .disable = tegra124_car_clock_disable, 287 .set_parent = tegra124_car_clock_set_parent, 288 .get_parent = tegra124_car_clock_get_parent, 289 }; 290 291 #define CLK_FIXED(_name, _rate) { \ 292 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 293 .u = { .fixed = { .rate = (_rate) } } \ 294 } 295 296 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 297 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 298 .parent = (_parent), \ 299 .u = { \ 300 .pll = { \ 301 .base_reg = (_base), \ 302 .divm_mask = (_divm), \ 303 .divn_mask = (_divn), \ 304 .divp_mask = (_divp), \ 305 } \ 306 } \ 307 } 308 309 #define CLK_MUX(_name, _reg, _bits, _p) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 311 .u = { \ 312 .mux = { \ 313 .nparents = __arraycount(_p), \ 314 .parents = (_p), \ 315 .reg = (_reg), \ 316 .bits = (_bits) \ 317 } \ 318 } \ 319 } 320 321 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 322 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 323 .parent = (_parent), \ 324 .u = { \ 325 .fixed_div = { \ 326 .div = (_div) \ 327 } \ 328 } \ 329 } 330 331 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 332 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 333 .parent = (_parent), \ 334 .u = { \ 335 .div = { \ 336 .reg = (_reg), \ 337 .bits = (_bits) \ 338 } \ 339 } \ 340 } 341 342 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 343 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 344 .type = TEGRA_CLK_GATE, \ 345 .parent = (_parent), \ 346 .u = { \ 347 .gate = { \ 348 .set_reg = (_set), \ 349 .clr_reg = (_clr), \ 350 .bits = (_bits), \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE_L(_name, _parent, _bits) \ 356 CLK_GATE(_name, _parent, \ 357 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 358 _bits) 359 360 #define CLK_GATE_H(_name, _parent, _bits) \ 361 CLK_GATE(_name, _parent, \ 362 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 363 _bits) 364 365 #define CLK_GATE_U(_name, _parent, _bits) \ 366 CLK_GATE(_name, _parent, \ 367 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 368 _bits) 369 370 #define CLK_GATE_V(_name, _parent, _bits) \ 371 CLK_GATE(_name, _parent, \ 372 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 373 _bits) 374 375 #define CLK_GATE_W(_name, _parent, _bits) \ 376 CLK_GATE(_name, _parent, \ 377 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 378 _bits) 379 380 #define CLK_GATE_X(_name, _parent, _bits) \ 381 CLK_GATE(_name, _parent, \ 382 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 383 _bits) 384 385 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 386 CLK_GATE(_name, _parent, _reg, _reg, _bits) 387 388 static const char *mux_uart_p[] = 389 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 390 "pll_m_out0", NULL, "clk_m" }; 391 static const char *mux_sdmmc_p[] = 392 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 393 "pll_m_out0", "pll_e_out0", "clk_m" }; 394 static const char *mux_i2c_p[] = 395 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 396 "pll_m_out0", NULL, "clk_m" }; 397 static const char *mux_spi_p[] = 398 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 399 "pll_m_out0", NULL, "clk_m" }; 400 static const char *mux_sata_p[] = 401 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 402 static const char *mux_hda_p[] = 403 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 404 "pll_m_out0", NULL, "clk_m" }; 405 static const char *mux_tsensor_p[] = 406 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 407 NULL, "clk_s" }; 408 static const char *mux_soc_therm_p[] = 409 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 410 "pll_c3_out0" }; 411 static const char *mux_host1x_p[] = 412 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 413 "pll_p_out0", NULL, "pll_a_out0" }; 414 static const char *mux_disp_p[] = 415 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 416 "pll_d2_out0", "clk_m" }; 417 static const char *mux_hdmi_p[] = 418 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 419 "pll_d2_out0", "clk_m" }; 420 static const char *mux_xusb_host_p[] = 421 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 422 "pll_re_out" }; 423 static const char *mux_xusb_ss_p[] = 424 { "clk_m", "pll_re_out", "clk_s", "pll_u_480", 425 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL }; 426 static const char *mux_xusb_fs_p[] = 427 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" }; 428 429 static struct tegra_clk tegra124_car_clocks[] = { 430 CLK_FIXED("clk_m", TEGRA_REF_FREQ), 431 432 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 433 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 434 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 435 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 436 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 437 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 438 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 439 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 440 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 441 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 442 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 443 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 444 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 445 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 446 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG, 447 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 448 449 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 450 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 451 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 452 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 453 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 454 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 455 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 456 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 457 CLK_FIXED_DIV("pll_re_out", "pll_re", 1), 458 459 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 460 mux_uart_p), 461 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 462 mux_uart_p), 463 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 464 mux_uart_p), 465 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 466 mux_uart_p), 467 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 468 mux_sdmmc_p), 469 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 470 mux_sdmmc_p), 471 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc_p), 473 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc_p), 475 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 476 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 477 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 478 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 479 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 480 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 482 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 483 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 484 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 485 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 486 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 487 CLK_MUX("mux_sata_oob", 488 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 489 CLK_MUX("mux_sata", 490 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 491 CLK_MUX("mux_hda2codec_2x", 492 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 493 mux_hda_p), 494 CLK_MUX("mux_hda", 495 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 496 CLK_MUX("mux_soc_therm", 497 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 498 mux_soc_therm_p), 499 CLK_MUX("mux_tsensor", 500 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 501 mux_tsensor_p), 502 CLK_MUX("mux_host1x", 503 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 504 mux_host1x_p), 505 CLK_MUX("mux_disp1", 506 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 507 mux_disp_p), 508 CLK_MUX("mux_disp2", 509 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 510 mux_disp_p), 511 CLK_MUX("mux_hdmi", 512 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 513 mux_hdmi_p), 514 CLK_MUX("mux_xusb_host", 515 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 516 mux_xusb_host_p), 517 CLK_MUX("mux_xusb_falcon", 518 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 519 mux_xusb_host_p), 520 CLK_MUX("mux_xusb_ss", 521 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 522 mux_xusb_ss_p), 523 CLK_MUX("mux_xusb_fs", 524 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 525 mux_xusb_fs_p), 526 527 CLK_DIV("div_uarta", "mux_uarta", 528 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 529 CLK_DIV("div_uartb", "mux_uartb", 530 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 531 CLK_DIV("div_uartc", "mux_uartc", 532 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 533 CLK_DIV("div_uartd", "mux_uartd", 534 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 535 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 536 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 537 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 538 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 539 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 540 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 541 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 542 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 543 CLK_DIV("div_i2c1", "mux_i2c1", 544 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 545 CLK_DIV("div_i2c2", "mux_i2c2", 546 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 547 CLK_DIV("div_i2c3", "mux_i2c3", 548 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 549 CLK_DIV("div_i2c4", "mux_i2c4", 550 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 551 CLK_DIV("div_i2c5", "mux_i2c5", 552 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 553 CLK_DIV("div_i2c6", "mux_i2c6", 554 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 555 CLK_DIV("div_spi1", "mux_spi1", 556 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV), 557 CLK_DIV("div_spi2", "mux_spi2", 558 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV), 559 CLK_DIV("div_spi3", "mux_spi3", 560 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV), 561 CLK_DIV("div_spi4", "mux_spi4", 562 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV), 563 CLK_DIV("div_spi5", "mux_spi5", 564 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV), 565 CLK_DIV("div_spi6", "mux_spi6", 566 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV), 567 CLK_DIV("div_sata_oob", "mux_sata_oob", 568 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 569 CLK_DIV("div_sata", "mux_sata", 570 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 571 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 572 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 573 CLK_DIV("div_hda", "mux_hda", 574 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 575 CLK_DIV("div_soc_therm", "mux_soc_therm", 576 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 577 CLK_DIV("div_tsensor", "mux_tsensor", 578 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 579 CLK_DIV("div_host1x", "mux_host1x", 580 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 581 CLK_DIV("div_hdmi", "mux_hdmi", 582 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 583 CLK_DIV("div_pll_p_out5", "pll_p", 584 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 585 CLK_DIV("xusb_host_src", "mux_xusb_host", 586 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 587 CLK_DIV("xusb_ss_src", "mux_xusb_ss", 588 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 589 CLK_DIV("xusb_fs_src", "mux_xusb_fs", 590 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 591 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon", 592 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 593 594 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 595 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 596 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 597 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 598 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 599 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 600 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 601 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 602 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 603 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 604 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 605 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 606 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 607 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 608 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1), 609 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2), 610 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3), 611 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4), 612 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5), 613 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6), 614 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 615 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 616 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 617 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 618 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 619 CLK_GATE_SIMPLE("cml0", "pll_e", 620 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 621 CLK_GATE_SIMPLE("cml1", "pll_e", 622 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 623 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 624 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 625 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 626 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 627 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 628 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 629 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 630 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 631 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 632 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 633 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5", 634 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 635 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST), 636 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS), 637 CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU), 638 }; 639 640 struct tegra124_init_parent { 641 const char *clock; 642 const char *parent; 643 } tegra124_init_parents[] = { 644 { "sata_oob", "pll_p_out0" }, 645 { "sata", "pll_p_out0" }, 646 { "hda", "pll_p_out0" }, 647 { "hda2codec_2x", "pll_p_out0" }, 648 { "soc_therm", "pll_p_out0" }, 649 { "tsensor", "clk_m" }, 650 { "xusb_host_src", "pll_p_out0" }, 651 { "xusb_falcon_src", "pll_p_out0" }, 652 { "xusb_ss_src", "pll_u_480" }, 653 { "xusb_fs_src", "pll_u_48" }, 654 { "host1x", "pll_p_out0" }, 655 }; 656 657 struct tegra124_car_rst { 658 u_int set_reg; 659 u_int clr_reg; 660 u_int mask; 661 }; 662 663 static struct tegra124_car_reset_reg { 664 u_int set_reg; 665 u_int clr_reg; 666 } tegra124_car_reset_regs[] = { 667 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 668 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 669 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 670 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 671 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 672 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 673 }; 674 675 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 676 static void tegra124_car_reset_release(device_t, void *); 677 static int tegra124_car_reset_assert(device_t, void *); 678 static int tegra124_car_reset_deassert(device_t, void *); 679 680 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 681 .acquire = tegra124_car_reset_acquire, 682 .release = tegra124_car_reset_release, 683 .reset_assert = tegra124_car_reset_assert, 684 .reset_deassert = tegra124_car_reset_deassert, 685 }; 686 687 struct tegra124_car_softc { 688 device_t sc_dev; 689 bus_space_tag_t sc_bst; 690 bus_space_handle_t sc_bsh; 691 692 struct clk_domain sc_clkdom; 693 694 u_int sc_clock_cells; 695 u_int sc_reset_cells; 696 697 kmutex_t sc_rndlock; 698 krndsource_t sc_rndsource; 699 }; 700 701 static void tegra124_car_init(struct tegra124_car_softc *); 702 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 703 static void tegra124_car_xusb_init(struct tegra124_car_softc *); 704 static void tegra124_car_watchdog_init(struct tegra124_car_softc *); 705 static void tegra124_car_parent_init(struct tegra124_car_softc *); 706 707 static void tegra124_car_rnd_attach(device_t); 708 static void tegra124_car_rnd_callback(size_t, void *); 709 710 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 711 tegra124_car_match, tegra124_car_attach, NULL, NULL); 712 713 static int 714 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 715 { 716 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 717 struct fdt_attach_args * const faa = aux; 718 719 #if 0 720 return of_match_compatible(faa->faa_phandle, compatible); 721 #else 722 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 723 return 0; 724 725 return 999; 726 #endif 727 } 728 729 static void 730 tegra124_car_attach(device_t parent, device_t self, void *aux) 731 { 732 struct tegra124_car_softc * const sc = device_private(self); 733 struct fdt_attach_args * const faa = aux; 734 const int phandle = faa->faa_phandle; 735 bus_addr_t addr; 736 bus_size_t size; 737 int error, n; 738 739 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 740 aprint_error(": couldn't get registers\n"); 741 return; 742 } 743 744 sc->sc_dev = self; 745 sc->sc_bst = faa->faa_bst; 746 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 747 if (error) { 748 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 749 return; 750 } 751 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 752 sc->sc_clock_cells = 1; 753 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 754 sc->sc_reset_cells = 1; 755 756 aprint_naive("\n"); 757 aprint_normal(": CAR\n"); 758 759 sc->sc_clkdom.funcs = &tegra124_car_clock_funcs; 760 sc->sc_clkdom.priv = sc; 761 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) 762 tegra124_car_clocks[n].base.domain = &sc->sc_clkdom; 763 764 fdtbus_register_clock_controller(self, phandle, 765 &tegra124_car_fdtclock_funcs); 766 fdtbus_register_reset_controller(self, phandle, 767 &tegra124_car_fdtreset_funcs); 768 769 tegra124_car_init(sc); 770 771 config_interrupts(self, tegra124_car_rnd_attach); 772 } 773 774 static void 775 tegra124_car_init(struct tegra124_car_softc *sc) 776 { 777 tegra124_car_parent_init(sc); 778 tegra124_car_utmip_init(sc); 779 tegra124_car_xusb_init(sc); 780 tegra124_car_watchdog_init(sc); 781 } 782 783 static void 784 tegra124_car_parent_init(struct tegra124_car_softc *sc) 785 { 786 struct clk *clk, *clk_parent; 787 int error; 788 u_int n; 789 790 for (n = 0; n < __arraycount(tegra124_init_parents); n++) { 791 clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock); 792 KASSERT(clk != NULL); 793 clk_parent = clk_get(&sc->sc_clkdom, 794 tegra124_init_parents[n].parent); 795 KASSERT(clk_parent != NULL); 796 797 error = clk_set_parent(clk, clk_parent); 798 if (error) { 799 aprint_error_dev(sc->sc_dev, 800 "couldn't set '%s' parent to '%s': %d\n", 801 clk->name, clk_parent->name, error); 802 } 803 clk_put(clk_parent); 804 clk_put(clk); 805 } 806 } 807 808 static void 809 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 810 { 811 bus_space_tag_t bst = sc->sc_bst; 812 bus_space_handle_t bsh = sc->sc_bsh; 813 814 const u_int enable_dly_count = 0x02; 815 const u_int stable_count = 0x2f; 816 const u_int active_dly_count = 0x04; 817 const u_int xtal_freq_count = 0x76; 818 819 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 820 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 821 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 822 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 823 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 824 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 825 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 826 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 827 828 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 829 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 830 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 831 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 832 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 833 834 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 835 0, 836 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 837 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 838 839 } 840 841 static void 842 tegra124_car_xusb_init(struct tegra124_car_softc *sc) 843 { 844 const bus_space_tag_t bst = sc->sc_bst; 845 const bus_space_handle_t bsh = sc->sc_bsh; 846 uint32_t val; 847 848 /* XXX do this all better */ 849 850 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 851 852 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 853 0, CAR_PLLREFE_MISC_IDDQ); 854 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 855 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 856 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 857 858 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 859 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 860 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 861 CAR_PLLREFE_BASE_ENABLE, 0); 862 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 863 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 864 865 do { 866 delay(2); 867 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 868 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 869 870 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 871 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 872 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 873 CAR_PLLE_BASE_ENABLE, 0); 874 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 875 CAR_PLLE_MISC_LOCK_ENABLE, 0); 876 877 do { 878 delay(2); 879 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 880 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 881 882 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 883 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 884 } 885 886 static void 887 tegra124_car_watchdog_init(struct tegra124_car_softc *sc) 888 { 889 const bus_space_tag_t bst = sc->sc_bst; 890 const bus_space_handle_t bsh = sc->sc_bsh; 891 892 /* Enable watchdog timer reset for system */ 893 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 894 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 895 } 896 897 static void 898 tegra124_car_rnd_attach(device_t self) 899 { 900 struct tegra124_car_softc * const sc = device_private(self); 901 902 mutex_init(&sc->sc_rndlock, MUTEX_DEFAULT, IPL_VM); 903 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 904 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 905 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 906 tegra124_car_rnd_callback(RND_POOLBITS / NBBY, sc); 907 } 908 909 static void 910 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 911 { 912 struct tegra124_car_softc * const sc = priv; 913 uint16_t buf[512]; 914 uint32_t cnt; 915 916 mutex_enter(&sc->sc_rndlock); 917 while (bytes_wanted) { 918 const u_int nbytes = MIN(bytes_wanted, 1024); 919 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) { 920 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 921 CAR_PLL_LFSR_REG) & 0xffff; 922 } 923 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes, 924 nbytes * NBBY); 925 bytes_wanted -= MIN(bytes_wanted, nbytes); 926 } 927 explicit_memset(buf, 0, sizeof(buf)); 928 mutex_exit(&sc->sc_rndlock); 929 } 930 931 static struct tegra_clk * 932 tegra124_car_clock_find(const char *name) 933 { 934 u_int n; 935 936 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 937 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 938 return &tegra124_car_clocks[n]; 939 } 940 } 941 942 return NULL; 943 } 944 945 static struct tegra_clk * 946 tegra124_car_clock_find_by_id(u_int clock_id) 947 { 948 u_int n; 949 950 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 951 if (tegra124_car_clock_ids[n].id == clock_id) { 952 const char *name = tegra124_car_clock_ids[n].name; 953 return tegra124_car_clock_find(name); 954 } 955 } 956 957 return NULL; 958 } 959 960 static struct clk * 961 tegra124_car_clock_decode(device_t dev, const void *data, size_t len) 962 { 963 struct tegra124_car_softc * const sc = device_private(dev); 964 struct tegra_clk *tclk; 965 966 if (len != sc->sc_clock_cells * 4) { 967 return NULL; 968 } 969 970 const u_int clock_id = be32dec(data); 971 972 tclk = tegra124_car_clock_find_by_id(clock_id); 973 if (tclk) 974 return TEGRA_CLK_BASE(tclk); 975 976 return NULL; 977 } 978 979 static struct clk * 980 tegra124_car_clock_get(void *priv, const char *name) 981 { 982 struct tegra_clk *tclk; 983 984 tclk = tegra124_car_clock_find(name); 985 if (tclk == NULL) 986 return NULL; 987 988 atomic_inc_uint(&tclk->refcnt); 989 990 return TEGRA_CLK_BASE(tclk); 991 } 992 993 static void 994 tegra124_car_clock_put(void *priv, struct clk *clk) 995 { 996 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 997 998 KASSERT(tclk->refcnt > 0); 999 1000 atomic_dec_uint(&tclk->refcnt); 1001 } 1002 1003 static u_int 1004 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 1005 struct tegra_clk *tclk) 1006 { 1007 struct tegra_pll_clk *tpll = &tclk->u.pll; 1008 struct tegra_clk *tclk_parent; 1009 bus_space_tag_t bst = sc->sc_bst; 1010 bus_space_handle_t bsh = sc->sc_bsh; 1011 u_int divm, divn, divp; 1012 uint64_t rate; 1013 1014 KASSERT(tclk->type == TEGRA_CLK_PLL); 1015 1016 tclk_parent = tegra124_car_clock_find(tclk->parent); 1017 KASSERT(tclk_parent != NULL); 1018 1019 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 1020 TEGRA_CLK_BASE(tclk_parent)); 1021 1022 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1023 divm = __SHIFTOUT(base, tpll->divm_mask); 1024 divn = __SHIFTOUT(base, tpll->divn_mask); 1025 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1026 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1027 } else { 1028 divp = __SHIFTOUT(base, tpll->divp_mask); 1029 } 1030 1031 rate = (uint64_t)rate_parent * divn; 1032 return rate / (divm << divp); 1033 } 1034 1035 static int 1036 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 1037 struct tegra_clk *tclk, u_int rate) 1038 { 1039 struct tegra_pll_clk *tpll = &tclk->u.pll; 1040 bus_space_tag_t bst = sc->sc_bst; 1041 bus_space_handle_t bsh = sc->sc_bsh; 1042 struct clk *clk_parent; 1043 uint32_t bp, base; 1044 1045 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1046 if (clk_parent == NULL) 1047 return EIO; 1048 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 1049 if (rate_parent == 0) 1050 return EIO; 1051 1052 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1053 const u_int divm = 1; 1054 const u_int divn = rate / rate_parent; 1055 const u_int divp = 0; 1056 1057 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1058 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1059 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1060 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1061 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1062 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1063 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1064 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1065 1066 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1067 base &= ~CAR_PLLX_BASE_DIVM; 1068 base &= ~CAR_PLLX_BASE_DIVN; 1069 base &= ~CAR_PLLX_BASE_DIVP; 1070 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1071 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1072 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1073 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1074 1075 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1076 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1077 do { 1078 delay(2); 1079 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1080 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1081 delay(100); 1082 1083 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1084 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1085 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1086 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1087 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1088 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1089 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1090 1091 return 0; 1092 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1093 const u_int divm = 1; 1094 const u_int pldiv = 1; 1095 const u_int divn = (rate << pldiv) / rate_parent; 1096 1097 /* Set frequency */ 1098 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1099 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1100 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1101 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1102 CAR_PLLD2_BASE_REF_SRC_SEL | 1103 CAR_PLLD2_BASE_DIVM | 1104 CAR_PLLD2_BASE_DIVN | 1105 CAR_PLLD2_BASE_DIVP); 1106 1107 return 0; 1108 } else { 1109 /* TODO */ 1110 return EOPNOTSUPP; 1111 } 1112 } 1113 1114 static int 1115 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 1116 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1117 { 1118 struct tegra_mux_clk *tmux = &tclk->u.mux; 1119 bus_space_tag_t bst = sc->sc_bst; 1120 bus_space_handle_t bsh = sc->sc_bsh; 1121 uint32_t v; 1122 u_int src; 1123 1124 KASSERT(tclk->type == TEGRA_CLK_MUX); 1125 1126 for (src = 0; src < tmux->nparents; src++) { 1127 if (tmux->parents[src] == NULL) { 1128 continue; 1129 } 1130 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1131 break; 1132 } 1133 } 1134 if (src == tmux->nparents) { 1135 return EINVAL; 1136 } 1137 1138 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1139 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1140 /* Change IDDQ from 1 to 0 */ 1141 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1142 0, CAR_PLLD2_BASE_IDDQ); 1143 delay(2); 1144 1145 /* Enable lock */ 1146 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1147 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1148 1149 /* Enable PLLD2 */ 1150 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1151 CAR_PLLD2_BASE_ENABLE, 0); 1152 1153 /* Wait for lock */ 1154 do { 1155 delay(2); 1156 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1157 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1158 1159 delay(200); 1160 } 1161 1162 v = bus_space_read_4(bst, bsh, tmux->reg); 1163 v &= ~tmux->bits; 1164 v |= __SHIFTIN(src, tmux->bits); 1165 bus_space_write_4(bst, bsh, tmux->reg, v); 1166 1167 return 0; 1168 } 1169 1170 static struct tegra_clk * 1171 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1172 struct tegra_clk *tclk) 1173 { 1174 struct tegra_mux_clk *tmux = &tclk->u.mux; 1175 bus_space_tag_t bst = sc->sc_bst; 1176 bus_space_handle_t bsh = sc->sc_bsh; 1177 1178 KASSERT(tclk->type == TEGRA_CLK_MUX); 1179 1180 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1181 const u_int src = __SHIFTOUT(v, tmux->bits); 1182 1183 KASSERT(src < tmux->nparents); 1184 1185 if (tmux->parents[src] == NULL) { 1186 return NULL; 1187 } 1188 1189 return tegra124_car_clock_find(tmux->parents[src]); 1190 } 1191 1192 static u_int 1193 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1194 struct tegra_clk *tclk) 1195 { 1196 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1197 struct clk *clk_parent; 1198 1199 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1200 if (clk_parent == NULL) 1201 return 0; 1202 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1203 1204 return parent_rate / tfixed_div->div; 1205 } 1206 1207 static u_int 1208 tegra124_car_clock_calc_rate_frac_div(u_int rate, u_int raw_div) 1209 { 1210 raw_div += 2; 1211 rate *= 2; 1212 rate += raw_div - 1; 1213 rate /= raw_div; 1214 return rate; 1215 } 1216 1217 static u_int 1218 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1219 struct tegra_clk *tclk) 1220 { 1221 struct tegra_div_clk *tdiv = &tclk->u.div; 1222 bus_space_tag_t bst = sc->sc_bst; 1223 bus_space_handle_t bsh = sc->sc_bsh; 1224 struct clk *clk_parent; 1225 u_int rate; 1226 1227 KASSERT(tclk->type == TEGRA_CLK_DIV); 1228 1229 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1230 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1231 1232 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1233 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1234 1235 switch (tdiv->reg) { 1236 case CAR_CLKSRC_I2C1_REG: 1237 case CAR_CLKSRC_I2C2_REG: 1238 case CAR_CLKSRC_I2C3_REG: 1239 case CAR_CLKSRC_I2C4_REG: 1240 case CAR_CLKSRC_I2C5_REG: 1241 case CAR_CLKSRC_I2C6_REG: 1242 rate = parent_rate * 1 / (raw_div + 1); 1243 break; 1244 case CAR_CLKSRC_UARTA_REG: 1245 case CAR_CLKSRC_UARTB_REG: 1246 case CAR_CLKSRC_UARTC_REG: 1247 case CAR_CLKSRC_UARTD_REG: 1248 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1249 rate = tegra124_car_clock_calc_rate_frac_div( 1250 parent_rate, raw_div); 1251 } else { 1252 rate = parent_rate; 1253 } 1254 break; 1255 default: 1256 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate, 1257 raw_div); 1258 break; 1259 } 1260 1261 return rate; 1262 } 1263 1264 static int 1265 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1266 struct tegra_clk *tclk, u_int rate) 1267 { 1268 struct tegra_div_clk *tdiv = &tclk->u.div; 1269 bus_space_tag_t bst = sc->sc_bst; 1270 bus_space_handle_t bsh = sc->sc_bsh; 1271 struct clk *clk_parent; 1272 u_int raw_div; 1273 uint32_t v; 1274 1275 KASSERT(tclk->type == TEGRA_CLK_DIV); 1276 1277 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1278 if (clk_parent == NULL) 1279 return EINVAL; 1280 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1281 1282 v = bus_space_read_4(bst, bsh, tdiv->reg); 1283 1284 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1285 1286 switch (tdiv->reg) { 1287 case CAR_CLKSRC_UARTA_REG: 1288 case CAR_CLKSRC_UARTB_REG: 1289 case CAR_CLKSRC_UARTC_REG: 1290 case CAR_CLKSRC_UARTD_REG: 1291 if (rate == parent_rate) { 1292 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1293 } else { 1294 v |= CAR_CLKSRC_UART_DIV_ENB; 1295 raw_div = (parent_rate * 2) / rate - 2; 1296 } 1297 break; 1298 case CAR_CLKSRC_SATA_REG: 1299 if (rate) { 1300 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1301 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1302 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1303 raw_div = (parent_rate * 2) / rate - 2; 1304 } else { 1305 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1306 } 1307 break; 1308 case CAR_CLKSRC_I2C1_REG: 1309 case CAR_CLKSRC_I2C2_REG: 1310 case CAR_CLKSRC_I2C3_REG: 1311 case CAR_CLKSRC_I2C4_REG: 1312 case CAR_CLKSRC_I2C5_REG: 1313 case CAR_CLKSRC_I2C6_REG: 1314 if (rate) 1315 raw_div = parent_rate / rate - 1; 1316 break; 1317 case CAR_CLKSRC_SDMMC1_REG: 1318 case CAR_CLKSRC_SDMMC2_REG: 1319 case CAR_CLKSRC_SDMMC3_REG: 1320 case CAR_CLKSRC_SDMMC4_REG: 1321 if (rate) { 1322 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1323 u_int calc_rate = 1324 tegra124_car_clock_calc_rate_frac_div( 1325 parent_rate, raw_div); 1326 if (calc_rate <= rate) 1327 break; 1328 } 1329 if (raw_div == 0x100) 1330 return EINVAL; 1331 } 1332 break; 1333 default: 1334 if (rate) 1335 raw_div = (parent_rate * 2) / rate - 2; 1336 break; 1337 } 1338 1339 v &= ~tdiv->bits; 1340 v |= __SHIFTIN(raw_div, tdiv->bits); 1341 1342 bus_space_write_4(bst, bsh, tdiv->reg, v); 1343 1344 return 0; 1345 } 1346 1347 static int 1348 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1349 struct tegra_clk *tclk, bool enable) 1350 { 1351 struct tegra_gate_clk *tgate = &tclk->u.gate; 1352 bus_space_tag_t bst = sc->sc_bst; 1353 bus_space_handle_t bsh = sc->sc_bsh; 1354 bus_size_t reg; 1355 1356 KASSERT(tclk->type == TEGRA_CLK_GATE); 1357 1358 if (tgate->set_reg == tgate->clr_reg) { 1359 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1360 if (enable) { 1361 v |= tgate->bits; 1362 } else { 1363 v &= ~tgate->bits; 1364 } 1365 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1366 } else { 1367 if (enable) { 1368 reg = tgate->set_reg; 1369 } else { 1370 reg = tgate->clr_reg; 1371 } 1372 1373 if (reg == CAR_CLK_ENB_V_SET_REG && 1374 tgate->bits == CAR_DEV_V_SATA) { 1375 /* De-assert reset to SATA PADPLL */ 1376 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1377 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1378 delay(15); 1379 } 1380 bus_space_write_4(bst, bsh, reg, tgate->bits); 1381 } 1382 1383 return 0; 1384 } 1385 1386 static u_int 1387 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1388 { 1389 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1390 struct clk *clk_parent; 1391 1392 switch (tclk->type) { 1393 case TEGRA_CLK_FIXED: 1394 return tclk->u.fixed.rate; 1395 case TEGRA_CLK_PLL: 1396 return tegra124_car_clock_get_rate_pll(priv, tclk); 1397 case TEGRA_CLK_MUX: 1398 case TEGRA_CLK_GATE: 1399 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1400 if (clk_parent == NULL) 1401 return EINVAL; 1402 return tegra124_car_clock_get_rate(priv, clk_parent); 1403 case TEGRA_CLK_FIXED_DIV: 1404 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1405 case TEGRA_CLK_DIV: 1406 return tegra124_car_clock_get_rate_div(priv, tclk); 1407 default: 1408 panic("tegra124: unknown tclk type %d", tclk->type); 1409 } 1410 } 1411 1412 static int 1413 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1414 { 1415 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1416 struct clk *clk_parent; 1417 1418 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1419 1420 switch (tclk->type) { 1421 case TEGRA_CLK_FIXED: 1422 case TEGRA_CLK_MUX: 1423 return EIO; 1424 case TEGRA_CLK_FIXED_DIV: 1425 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1426 if (clk_parent == NULL) 1427 return EIO; 1428 return tegra124_car_clock_set_rate(priv, clk_parent, 1429 rate * tclk->u.fixed_div.div); 1430 case TEGRA_CLK_GATE: 1431 return EINVAL; 1432 case TEGRA_CLK_PLL: 1433 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1434 case TEGRA_CLK_DIV: 1435 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1436 default: 1437 panic("tegra124: unknown tclk type %d", tclk->type); 1438 } 1439 } 1440 1441 static int 1442 tegra124_car_clock_enable(void *priv, struct clk *clk) 1443 { 1444 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1445 struct clk *clk_parent; 1446 1447 if (tclk->type != TEGRA_CLK_GATE) { 1448 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1449 if (clk_parent == NULL) 1450 return 0; 1451 return tegra124_car_clock_enable(priv, clk_parent); 1452 } 1453 1454 return tegra124_car_clock_enable_gate(priv, tclk, true); 1455 } 1456 1457 static int 1458 tegra124_car_clock_disable(void *priv, struct clk *clk) 1459 { 1460 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1461 1462 if (tclk->type != TEGRA_CLK_GATE) 1463 return EINVAL; 1464 1465 return tegra124_car_clock_enable_gate(priv, tclk, false); 1466 } 1467 1468 static int 1469 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1470 struct clk *clk_parent) 1471 { 1472 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1473 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1474 struct clk *nclk_parent; 1475 1476 if (tclk->type != TEGRA_CLK_MUX) { 1477 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1478 if (nclk_parent == clk_parent || nclk_parent == NULL) 1479 return EINVAL; 1480 return tegra124_car_clock_set_parent(priv, nclk_parent, 1481 clk_parent); 1482 } 1483 1484 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1485 } 1486 1487 static struct clk * 1488 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1489 { 1490 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1491 struct tegra_clk *tclk_parent = NULL; 1492 1493 switch (tclk->type) { 1494 case TEGRA_CLK_FIXED: 1495 case TEGRA_CLK_PLL: 1496 case TEGRA_CLK_FIXED_DIV: 1497 case TEGRA_CLK_DIV: 1498 case TEGRA_CLK_GATE: 1499 if (tclk->parent) { 1500 tclk_parent = tegra124_car_clock_find(tclk->parent); 1501 } 1502 break; 1503 case TEGRA_CLK_MUX: 1504 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1505 break; 1506 } 1507 1508 if (tclk_parent == NULL) 1509 return NULL; 1510 1511 return TEGRA_CLK_BASE(tclk_parent); 1512 } 1513 1514 static void * 1515 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1516 { 1517 struct tegra124_car_softc * const sc = device_private(dev); 1518 struct tegra124_car_rst *rst; 1519 1520 if (len != sc->sc_reset_cells * 4) 1521 return NULL; 1522 1523 const u_int reset_id = be32dec(data); 1524 1525 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32) 1526 return NULL; 1527 1528 const u_int reg = reset_id / 32; 1529 1530 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1531 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1532 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1533 rst->mask = __BIT(reset_id % 32); 1534 1535 return rst; 1536 } 1537 1538 static void 1539 tegra124_car_reset_release(device_t dev, void *priv) 1540 { 1541 struct tegra124_car_rst *rst = priv; 1542 1543 kmem_free(rst, sizeof(*rst)); 1544 } 1545 1546 static int 1547 tegra124_car_reset_assert(device_t dev, void *priv) 1548 { 1549 struct tegra124_car_softc * const sc = device_private(dev); 1550 struct tegra124_car_rst *rst = priv; 1551 1552 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1553 1554 return 0; 1555 } 1556 1557 static int 1558 tegra124_car_reset_deassert(device_t dev, void *priv) 1559 { 1560 struct tegra124_car_softc * const sc = device_private(dev); 1561 struct tegra124_car_rst *rst = priv; 1562 1563 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1564 1565 return 0; 1566 } 1567
Indexes created Thu Oct 02 01:09:59 GMT 2025