tegra124_car.c revision 1.16
1 /* $NetBSD: tegra124_car.c,v 1.16 2018/09/26 22:32:46 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.16 2018/09/26 22:32:46 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra124_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra124_car_match(device_t, cfdata_t, void *); 54 static void tegra124_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra124_car_clock_decode(device_t, int, const void *, 57 size_t); 58 59 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 60 .decode = tegra124_car_clock_decode 61 }; 62 63 /* DT clock ID to clock name mappings */ 64 static struct tegra124_car_clock_id { 65 u_int id; 66 const char *name; 67 } tegra124_car_clock_ids[] = { 68 { 3, "ispb" }, 69 { 4, "rtc" }, 70 { 5, "timer" }, 71 { 6, "uarta" }, 72 { 9, "sdmmc2" }, 73 { 11, "i2s1" }, 74 { 12, "i2c1" }, 75 { 14, "sdmmc1" }, 76 { 15, "sdmmc4" }, 77 { 17, "pwm" }, 78 { 18, "i2s2" }, 79 { 22, "usbd" }, 80 { 23, "isp" }, 81 { 26, "disp2" }, 82 { 27, "disp1" }, 83 { 28, "host1x" }, 84 { 29, "vcp" }, 85 { 30, "i2s0" }, 86 { 32, "mc" }, 87 { 34, "apbdma" }, 88 { 36, "kbc" }, 89 { 40, "kfuse" }, 90 { 41, "spi1" }, 91 { 42, "nor" }, 92 { 44, "spi2" }, 93 { 46, "spi3" }, 94 { 47, "i2c5" }, 95 { 48, "dsia" }, 96 { 50, "mipi" }, 97 { 51, "hdmi" }, 98 { 52, "csi" }, 99 { 54, "i2c2" }, 100 { 55, "uartc" }, 101 { 56, "mipi_cal" }, 102 { 57, "emc" }, 103 { 58, "usb2" }, 104 { 59, "usb3" }, 105 { 61, "vde" }, 106 { 62, "bsea" }, 107 { 63, "bsev" }, 108 { 65, "uartd" }, 109 { 67, "i2c3" }, 110 { 68, "spi4" }, 111 { 69, "sdmmc3" }, 112 { 70, "pcie" }, 113 { 71, "owr" }, 114 { 72, "afi" }, 115 { 73, "csite" }, 116 { 76, "la" }, 117 { 77, "trace" }, 118 { 78, "soc_therm" }, 119 { 79, "dtv" }, 120 { 81, "i2cslow" }, 121 { 82, "dsib" }, 122 { 83, "tsec" }, 123 { 89, "xusb_host" }, 124 { 91, "msenc" }, 125 { 92, "csus" }, 126 { 99, "mselect" }, 127 { 100, "tsensor" }, 128 { 101, "i2s3" }, 129 { 102, "i2s4" }, 130 { 103, "i2c4" }, 131 { 104, "spi5" }, 132 { 105, "spi6" }, 133 { 106, "d_audio" }, 134 { 107, "apbif" }, 135 { 108, "dam0" }, 136 { 109, "dam1" }, 137 { 110, "dam2" }, 138 { 111, "hda2codec_2x" }, 139 { 113, "audio0_2x" }, 140 { 114, "audio1_2x" }, 141 { 115, "audio2_2x" }, 142 { 116, "audio3_2x" }, 143 { 117, "audio4_2x" }, 144 { 118, "spdif_2x" }, 145 { 119, "actmon" }, 146 { 120, "extern1" }, 147 { 121, "extern2" }, 148 { 122, "extern3" }, 149 { 123, "sata_oob" }, 150 { 124, "sata" }, 151 { 125, "hda" }, 152 { 127, "se" }, 153 { 128, "hda2hdmi" }, 154 { 129, "sata_cold" }, 155 { 144, "cilab" }, 156 { 145, "cilcd" }, 157 { 146, "cile" }, 158 { 147, "dsialp" }, 159 { 148, "dsiblp" }, 160 { 149, "entropy" }, 161 { 150, "dds" }, 162 { 152, "dp2" }, 163 { 153, "amx" }, 164 { 154, "adx" }, 165 { 156, "xusb_ss" }, 166 { 166, "i2c6" }, 167 { 171, "vim2_clk" }, 168 { 176, "hdmi_audio" }, 169 { 177, "clk72mhz" }, 170 { 178, "vic03" }, 171 { 180, "adx1" }, 172 { 181, "dpaux" }, 173 { 182, "sor0" }, 174 { 184, "gpu" }, 175 { 185, "amx1" }, 176 { 192, "uartb" }, 177 { 193, "vfir" }, 178 { 194, "spdif_in" }, 179 { 195, "spdif_out" }, 180 { 196, "vi" }, 181 { 197, "vi_sensor" }, 182 { 198, "fuse" }, 183 { 199, "fuse_burn" }, 184 { 200, "clk_32k" }, 185 { 201, "clk_m" }, 186 { 202, "clk_m_div2" }, 187 { 203, "clk_m_div4" }, 188 { 204, "pll_ref" }, 189 { 205, "pll_c" }, 190 { 206, "pll_c_out1" }, 191 { 207, "pll_c2" }, 192 { 208, "pll_c3" }, 193 { 209, "pll_m" }, 194 { 210, "pll_m_out1" }, 195 { 211, "pll_p_out0" }, 196 { 212, "pll_p_out1" }, 197 { 213, "pll_p_out2" }, 198 { 214, "pll_p_out3" }, 199 { 215, "pll_p_out4" }, 200 { 216, "pll_a" }, 201 { 217, "pll_a_out0" }, 202 { 218, "pll_d" }, 203 { 219, "pll_d_out0" }, 204 { 220, "pll_d2" }, 205 { 221, "pll_d2_out0" }, 206 { 222, "pll_u" }, 207 { 223, "pll_u_480m" }, 208 { 224, "pll_u_60m" }, 209 { 225, "pll_u_48m" }, 210 { 226, "pll_u_12m" }, 211 { 229, "pll_re_vco" }, 212 { 230, "pll_re_out" }, 213 { 231, "pll_e" }, 214 { 232, "spdif_in_sync" }, 215 { 233, "i2s0_sync" }, 216 { 234, "i2s1_sync" }, 217 { 235, "i2s2_sync" }, 218 { 236, "i2s3_sync" }, 219 { 237, "i2s4_sync" }, 220 { 238, "vimclk_sync" }, 221 { 239, "audio0" }, 222 { 240, "audio1" }, 223 { 241, "audio2" }, 224 { 242, "audio3" }, 225 { 243, "audio4" }, 226 { 244, "spdif" }, 227 { 245, "clk_out_1" }, 228 { 246, "clk_out_2" }, 229 { 247, "clk_out_3" }, 230 { 248, "blink" }, 231 { 252, "xusb_host_src" }, 232 { 253, "xusb_falcon_src" }, 233 { 254, "xusb_fs_src" }, 234 { 255, "xusb_ss_src" }, 235 { 256, "xusb_dev_src" }, 236 { 257, "xusb_dev" }, 237 { 258, "xusb_hs_src" }, 238 { 259, "sclk" }, 239 { 260, "hclk" }, 240 { 261, "pclk" }, 241 { 264, "dfll_ref" }, 242 { 265, "dfll_soc" }, 243 { 266, "vi_sensor2" }, 244 { 267, "pll_p_out5" }, 245 { 268, "cml0" }, 246 { 269, "cml1" }, 247 { 270, "pll_c4" }, 248 { 271, "pll_dp" }, 249 { 272, "pll_e_mux" }, 250 { 273, "pll_d_dsi_out" }, 251 { 300, "audio0_mux" }, 252 { 301, "audio1_mux" }, 253 { 302, "audio2_mux" }, 254 { 303, "audio3_mux" }, 255 { 304, "audio4_mux" }, 256 { 305, "spdif_mux" }, 257 { 306, "clk_out_1_mux" }, 258 { 307, "clk_out_2_mux" }, 259 { 308, "clk_out_3_mux" }, 260 { 311, "sor0_lvds" }, 261 { 312, "xusb_ss_div2" }, 262 { 313, "pll_m_ud" }, 263 { 314, "pll_c_ud" }, 264 { 227, "pll_x" }, 265 { 228, "pll_x_out0" }, 266 { 262, "cclk_g" }, 267 { 263, "cclk_lp" }, 268 { 315, "clk_max" }, 269 }; 270 271 static struct clk *tegra124_car_clock_get(void *, const char *); 272 static void tegra124_car_clock_put(void *, struct clk *); 273 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 274 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 275 static int tegra124_car_clock_enable(void *, struct clk *); 276 static int tegra124_car_clock_disable(void *, struct clk *); 277 static int tegra124_car_clock_set_parent(void *, struct clk *, 278 struct clk *); 279 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 280 281 static const struct clk_funcs tegra124_car_clock_funcs = { 282 .get = tegra124_car_clock_get, 283 .put = tegra124_car_clock_put, 284 .get_rate = tegra124_car_clock_get_rate, 285 .set_rate = tegra124_car_clock_set_rate, 286 .enable = tegra124_car_clock_enable, 287 .disable = tegra124_car_clock_disable, 288 .set_parent = tegra124_car_clock_set_parent, 289 .get_parent = tegra124_car_clock_get_parent, 290 }; 291 292 #define CLK_FIXED(_name, _rate) { \ 293 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 294 .u = { .fixed = { .rate = (_rate) } } \ 295 } 296 297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 298 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 299 .parent = (_parent), \ 300 .u = { \ 301 .pll = { \ 302 .base_reg = (_base), \ 303 .divm_mask = (_divm), \ 304 .divn_mask = (_divn), \ 305 .divp_mask = (_divp), \ 306 } \ 307 } \ 308 } 309 310 #define CLK_MUX(_name, _reg, _bits, _p) { \ 311 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 312 .u = { \ 313 .mux = { \ 314 .nparents = __arraycount(_p), \ 315 .parents = (_p), \ 316 .reg = (_reg), \ 317 .bits = (_bits) \ 318 } \ 319 } \ 320 } 321 322 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 324 .parent = (_parent), \ 325 .u = { \ 326 .fixed_div = { \ 327 .div = (_div) \ 328 } \ 329 } \ 330 } 331 332 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 333 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 334 .parent = (_parent), \ 335 .u = { \ 336 .div = { \ 337 .reg = (_reg), \ 338 .bits = (_bits) \ 339 } \ 340 } \ 341 } 342 343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 344 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 345 .type = TEGRA_CLK_GATE, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .gate = { \ 349 .set_reg = (_set), \ 350 .clr_reg = (_clr), \ 351 .bits = (_bits), \ 352 } \ 353 } \ 354 } 355 356 #define CLK_GATE_L(_name, _parent, _bits) \ 357 CLK_GATE(_name, _parent, \ 358 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 359 _bits) 360 361 #define CLK_GATE_H(_name, _parent, _bits) \ 362 CLK_GATE(_name, _parent, \ 363 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 364 _bits) 365 366 #define CLK_GATE_U(_name, _parent, _bits) \ 367 CLK_GATE(_name, _parent, \ 368 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 369 _bits) 370 371 #define CLK_GATE_V(_name, _parent, _bits) \ 372 CLK_GATE(_name, _parent, \ 373 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 374 _bits) 375 376 #define CLK_GATE_W(_name, _parent, _bits) \ 377 CLK_GATE(_name, _parent, \ 378 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 379 _bits) 380 381 #define CLK_GATE_X(_name, _parent, _bits) \ 382 CLK_GATE(_name, _parent, \ 383 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 384 _bits) 385 386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 387 CLK_GATE(_name, _parent, _reg, _reg, _bits) 388 389 static const char *mux_uart_p[] = 390 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 391 "pll_m_out0", NULL, "clk_m" }; 392 static const char *mux_sdmmc_p[] = 393 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 394 "pll_m_out0", "pll_e_out0", "clk_m" }; 395 static const char *mux_i2c_p[] = 396 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 397 "pll_m_out0", NULL, "clk_m" }; 398 static const char *mux_spi_p[] = 399 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 400 "pll_m_out0", NULL, "clk_m" }; 401 static const char *mux_sata_p[] = 402 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 403 static const char *mux_hda_p[] = 404 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 405 "pll_m_out0", NULL, "clk_m" }; 406 static const char *mux_tsensor_p[] = 407 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 408 NULL, "clk_s" }; 409 static const char *mux_soc_therm_p[] = 410 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 411 "pll_c3_out0" }; 412 static const char *mux_host1x_p[] = 413 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 414 "pll_p_out0", NULL, "pll_a_out0" }; 415 static const char *mux_disp_p[] = 416 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 417 "pll_d2_out0", "clk_m" }; 418 static const char *mux_hdmi_p[] = 419 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 420 "pll_d2_out0", "clk_m" }; 421 static const char *mux_xusb_host_p[] = 422 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 423 "pll_re_out" }; 424 static const char *mux_xusb_ss_p[] = 425 { "clk_m", "pll_re_out", "clk_s", "pll_u_480", 426 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL }; 427 static const char *mux_xusb_fs_p[] = 428 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" }; 429 430 static struct tegra_clk tegra124_car_clocks[] = { 431 CLK_FIXED("clk_m", TEGRA124_REF_FREQ), 432 433 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 434 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 435 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 436 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 437 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 438 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 439 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 440 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 441 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 442 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 443 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 444 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 445 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 446 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 447 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG, 448 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 449 450 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 451 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 452 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 453 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 454 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 455 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 456 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 457 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 458 CLK_FIXED_DIV("pll_re_out", "pll_re", 1), 459 460 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 461 mux_uart_p), 462 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 463 mux_uart_p), 464 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 465 mux_uart_p), 466 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 469 mux_sdmmc_p), 470 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 471 mux_sdmmc_p), 472 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 473 mux_sdmmc_p), 474 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 475 mux_sdmmc_p), 476 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 477 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 478 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 479 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 480 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 483 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 484 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 485 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 486 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 487 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 488 CLK_MUX("mux_sata_oob", 489 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 490 CLK_MUX("mux_sata", 491 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 492 CLK_MUX("mux_hda2codec_2x", 493 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 494 mux_hda_p), 495 CLK_MUX("mux_hda", 496 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 497 CLK_MUX("mux_soc_therm", 498 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 499 mux_soc_therm_p), 500 CLK_MUX("mux_tsensor", 501 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 502 mux_tsensor_p), 503 CLK_MUX("mux_host1x", 504 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 505 mux_host1x_p), 506 CLK_MUX("mux_disp1", 507 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 508 mux_disp_p), 509 CLK_MUX("mux_disp2", 510 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 511 mux_disp_p), 512 CLK_MUX("mux_hdmi", 513 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 514 mux_hdmi_p), 515 CLK_MUX("mux_xusb_host", 516 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 517 mux_xusb_host_p), 518 CLK_MUX("mux_xusb_falcon", 519 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 520 mux_xusb_host_p), 521 CLK_MUX("mux_xusb_ss", 522 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 523 mux_xusb_ss_p), 524 CLK_MUX("mux_xusb_fs", 525 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 526 mux_xusb_fs_p), 527 528 CLK_DIV("div_uarta", "mux_uarta", 529 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 530 CLK_DIV("div_uartb", "mux_uartb", 531 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 532 CLK_DIV("div_uartc", "mux_uartc", 533 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 534 CLK_DIV("div_uartd", "mux_uartd", 535 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 536 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 537 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 538 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 539 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 540 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 541 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 542 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 543 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 544 CLK_DIV("div_i2c1", "mux_i2c1", 545 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 546 CLK_DIV("div_i2c2", "mux_i2c2", 547 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 548 CLK_DIV("div_i2c3", "mux_i2c3", 549 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 550 CLK_DIV("div_i2c4", "mux_i2c4", 551 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 552 CLK_DIV("div_i2c5", "mux_i2c5", 553 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 554 CLK_DIV("div_i2c6", "mux_i2c6", 555 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 556 CLK_DIV("div_spi1", "mux_spi1", 557 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV), 558 CLK_DIV("div_spi2", "mux_spi2", 559 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV), 560 CLK_DIV("div_spi3", "mux_spi3", 561 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV), 562 CLK_DIV("div_spi4", "mux_spi4", 563 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV), 564 CLK_DIV("div_spi5", "mux_spi5", 565 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV), 566 CLK_DIV("div_spi6", "mux_spi6", 567 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV), 568 CLK_DIV("div_sata_oob", "mux_sata_oob", 569 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 570 CLK_DIV("div_sata", "mux_sata", 571 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 572 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 573 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 574 CLK_DIV("div_hda", "mux_hda", 575 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 576 CLK_DIV("div_soc_therm", "mux_soc_therm", 577 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 578 CLK_DIV("div_tsensor", "mux_tsensor", 579 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 580 CLK_DIV("div_host1x", "mux_host1x", 581 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 582 CLK_DIV("div_hdmi", "mux_hdmi", 583 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 584 CLK_DIV("div_pll_p_out5", "pll_p", 585 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 586 CLK_DIV("xusb_host_src", "mux_xusb_host", 587 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 588 CLK_DIV("xusb_ss_src", "mux_xusb_ss", 589 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 590 CLK_DIV("xusb_fs_src", "mux_xusb_fs", 591 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 592 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon", 593 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 594 595 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 596 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 597 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 598 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 599 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 600 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 601 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 602 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 603 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 604 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 605 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 606 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 607 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 608 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 609 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1), 610 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2), 611 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3), 612 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4), 613 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5), 614 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6), 615 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 616 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 617 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 618 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 619 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 620 CLK_GATE_SIMPLE("cml0", "pll_e", 621 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 622 CLK_GATE_SIMPLE("cml1", "pll_e", 623 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 624 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 625 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 626 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 627 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 628 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 629 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 630 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 631 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 632 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 633 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 634 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5", 635 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 636 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST), 637 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS), 638 CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU), 639 CLK_GATE_H("apbdma", "clk_m", CAR_DEV_H_APBDMA), 640 }; 641 642 struct tegra124_init_parent { 643 const char *clock; 644 const char *parent; 645 } tegra124_init_parents[] = { 646 { "sata_oob", "pll_p_out0" }, 647 { "sata", "pll_p_out0" }, 648 { "hda", "pll_p_out0" }, 649 { "hda2codec_2x", "pll_p_out0" }, 650 { "soc_therm", "pll_p_out0" }, 651 { "tsensor", "clk_m" }, 652 { "xusb_host_src", "pll_p_out0" }, 653 { "xusb_falcon_src", "pll_p_out0" }, 654 { "xusb_ss_src", "pll_u_480" }, 655 { "xusb_fs_src", "pll_u_48" }, 656 { "host1x", "pll_p_out0" }, 657 }; 658 659 struct tegra124_car_rst { 660 u_int set_reg; 661 u_int clr_reg; 662 u_int mask; 663 }; 664 665 static struct tegra124_car_reset_reg { 666 u_int set_reg; 667 u_int clr_reg; 668 } tegra124_car_reset_regs[] = { 669 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 670 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 671 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 672 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 673 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 674 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 675 }; 676 677 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 678 static void tegra124_car_reset_release(device_t, void *); 679 static int tegra124_car_reset_assert(device_t, void *); 680 static int tegra124_car_reset_deassert(device_t, void *); 681 682 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 683 .acquire = tegra124_car_reset_acquire, 684 .release = tegra124_car_reset_release, 685 .reset_assert = tegra124_car_reset_assert, 686 .reset_deassert = tegra124_car_reset_deassert, 687 }; 688 689 struct tegra124_car_softc { 690 device_t sc_dev; 691 bus_space_tag_t sc_bst; 692 bus_space_handle_t sc_bsh; 693 694 struct clk_domain sc_clkdom; 695 696 u_int sc_clock_cells; 697 u_int sc_reset_cells; 698 699 kmutex_t sc_rndlock; 700 krndsource_t sc_rndsource; 701 }; 702 703 static void tegra124_car_init(struct tegra124_car_softc *); 704 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 705 static void tegra124_car_xusb_init(struct tegra124_car_softc *); 706 static void tegra124_car_watchdog_init(struct tegra124_car_softc *); 707 static void tegra124_car_parent_init(struct tegra124_car_softc *); 708 709 static void tegra124_car_rnd_attach(device_t); 710 static void tegra124_car_rnd_callback(size_t, void *); 711 712 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 713 tegra124_car_match, tegra124_car_attach, NULL, NULL); 714 715 static int 716 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 717 { 718 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 719 struct fdt_attach_args * const faa = aux; 720 721 #if 0 722 return of_match_compatible(faa->faa_phandle, compatible); 723 #else 724 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 725 return 0; 726 727 return 999; 728 #endif 729 } 730 731 static void 732 tegra124_car_attach(device_t parent, device_t self, void *aux) 733 { 734 struct tegra124_car_softc * const sc = device_private(self); 735 struct fdt_attach_args * const faa = aux; 736 const int phandle = faa->faa_phandle; 737 bus_addr_t addr; 738 bus_size_t size; 739 int error, n; 740 741 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 742 aprint_error(": couldn't get registers\n"); 743 return; 744 } 745 746 sc->sc_dev = self; 747 sc->sc_bst = faa->faa_bst; 748 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 749 if (error) { 750 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 751 return; 752 } 753 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 754 sc->sc_clock_cells = 1; 755 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 756 sc->sc_reset_cells = 1; 757 758 aprint_naive("\n"); 759 aprint_normal(": CAR\n"); 760 761 sc->sc_clkdom.name = device_xname(self); 762 sc->sc_clkdom.funcs = &tegra124_car_clock_funcs; 763 sc->sc_clkdom.priv = sc; 764 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 765 tegra124_car_clocks[n].base.domain = &sc->sc_clkdom; 766 clk_attach(&tegra124_car_clocks[n].base); 767 } 768 769 fdtbus_register_clock_controller(self, phandle, 770 &tegra124_car_fdtclock_funcs); 771 fdtbus_register_reset_controller(self, phandle, 772 &tegra124_car_fdtreset_funcs); 773 774 tegra124_car_init(sc); 775 776 config_interrupts(self, tegra124_car_rnd_attach); 777 } 778 779 static void 780 tegra124_car_init(struct tegra124_car_softc *sc) 781 { 782 tegra124_car_parent_init(sc); 783 tegra124_car_utmip_init(sc); 784 tegra124_car_xusb_init(sc); 785 tegra124_car_watchdog_init(sc); 786 } 787 788 static void 789 tegra124_car_parent_init(struct tegra124_car_softc *sc) 790 { 791 struct clk *clk, *clk_parent; 792 int error; 793 u_int n; 794 795 for (n = 0; n < __arraycount(tegra124_init_parents); n++) { 796 clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock); 797 KASSERT(clk != NULL); 798 clk_parent = clk_get(&sc->sc_clkdom, 799 tegra124_init_parents[n].parent); 800 KASSERT(clk_parent != NULL); 801 802 error = clk_set_parent(clk, clk_parent); 803 if (error) { 804 aprint_error_dev(sc->sc_dev, 805 "couldn't set '%s' parent to '%s': %d\n", 806 clk->name, clk_parent->name, error); 807 } 808 clk_put(clk_parent); 809 clk_put(clk); 810 } 811 } 812 813 static void 814 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 815 { 816 bus_space_tag_t bst = sc->sc_bst; 817 bus_space_handle_t bsh = sc->sc_bsh; 818 819 const u_int enable_dly_count = 0x02; 820 const u_int stable_count = 0x2f; 821 const u_int active_dly_count = 0x04; 822 const u_int xtal_freq_count = 0x76; 823 824 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 825 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 826 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 827 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 828 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 829 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 830 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 831 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 832 833 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 834 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 835 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 836 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 837 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 838 839 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 840 0, 841 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 842 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 843 844 } 845 846 static void 847 tegra124_car_xusb_init(struct tegra124_car_softc *sc) 848 { 849 const bus_space_tag_t bst = sc->sc_bst; 850 const bus_space_handle_t bsh = sc->sc_bsh; 851 uint32_t val; 852 853 /* XXX do this all better */ 854 855 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 856 857 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 858 0, CAR_PLLREFE_MISC_IDDQ); 859 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 860 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 861 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 862 863 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 864 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 865 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 866 CAR_PLLREFE_BASE_ENABLE, 0); 867 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 868 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 869 870 do { 871 delay(2); 872 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 873 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 874 875 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 876 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 877 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 878 CAR_PLLE_BASE_ENABLE, 0); 879 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 880 CAR_PLLE_MISC_LOCK_ENABLE, 0); 881 882 do { 883 delay(2); 884 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 885 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 886 887 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 888 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 889 } 890 891 static void 892 tegra124_car_watchdog_init(struct tegra124_car_softc *sc) 893 { 894 const bus_space_tag_t bst = sc->sc_bst; 895 const bus_space_handle_t bsh = sc->sc_bsh; 896 897 /* Enable watchdog timer reset for system */ 898 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 899 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 900 } 901 902 static void 903 tegra124_car_rnd_attach(device_t self) 904 { 905 struct tegra124_car_softc * const sc = device_private(self); 906 907 mutex_init(&sc->sc_rndlock, MUTEX_DEFAULT, IPL_VM); 908 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 909 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 910 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 911 tegra124_car_rnd_callback(RND_POOLBITS / NBBY, sc); 912 } 913 914 static void 915 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 916 { 917 struct tegra124_car_softc * const sc = priv; 918 uint16_t buf[512]; 919 uint32_t cnt; 920 921 mutex_enter(&sc->sc_rndlock); 922 while (bytes_wanted) { 923 const u_int nbytes = MIN(bytes_wanted, 1024); 924 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) { 925 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 926 CAR_PLL_LFSR_REG) & 0xffff; 927 } 928 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes, 929 nbytes * NBBY); 930 bytes_wanted -= MIN(bytes_wanted, nbytes); 931 } 932 explicit_memset(buf, 0, sizeof(buf)); 933 mutex_exit(&sc->sc_rndlock); 934 } 935 936 static struct tegra_clk * 937 tegra124_car_clock_find(const char *name) 938 { 939 u_int n; 940 941 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 942 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 943 return &tegra124_car_clocks[n]; 944 } 945 } 946 947 return NULL; 948 } 949 950 static struct tegra_clk * 951 tegra124_car_clock_find_by_id(u_int clock_id) 952 { 953 u_int n; 954 955 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 956 if (tegra124_car_clock_ids[n].id == clock_id) { 957 const char *name = tegra124_car_clock_ids[n].name; 958 return tegra124_car_clock_find(name); 959 } 960 } 961 962 return NULL; 963 } 964 965 static struct clk * 966 tegra124_car_clock_decode(device_t dev, int cc_phandle, const void *data, 967 size_t len) 968 { 969 struct tegra124_car_softc * const sc = device_private(dev); 970 struct tegra_clk *tclk; 971 972 if (len != sc->sc_clock_cells * 4) { 973 return NULL; 974 } 975 976 const u_int clock_id = be32dec(data); 977 978 tclk = tegra124_car_clock_find_by_id(clock_id); 979 if (tclk) 980 return TEGRA_CLK_BASE(tclk); 981 982 return NULL; 983 } 984 985 static struct clk * 986 tegra124_car_clock_get(void *priv, const char *name) 987 { 988 struct tegra_clk *tclk; 989 990 tclk = tegra124_car_clock_find(name); 991 if (tclk == NULL) 992 return NULL; 993 994 atomic_inc_uint(&tclk->refcnt); 995 996 return TEGRA_CLK_BASE(tclk); 997 } 998 999 static void 1000 tegra124_car_clock_put(void *priv, struct clk *clk) 1001 { 1002 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1003 1004 KASSERT(tclk->refcnt > 0); 1005 1006 atomic_dec_uint(&tclk->refcnt); 1007 } 1008 1009 static u_int 1010 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 1011 struct tegra_clk *tclk) 1012 { 1013 struct tegra_pll_clk *tpll = &tclk->u.pll; 1014 struct tegra_clk *tclk_parent; 1015 bus_space_tag_t bst = sc->sc_bst; 1016 bus_space_handle_t bsh = sc->sc_bsh; 1017 u_int divm, divn, divp; 1018 uint64_t rate; 1019 1020 KASSERT(tclk->type == TEGRA_CLK_PLL); 1021 1022 tclk_parent = tegra124_car_clock_find(tclk->parent); 1023 KASSERT(tclk_parent != NULL); 1024 1025 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 1026 TEGRA_CLK_BASE(tclk_parent)); 1027 1028 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1029 divm = __SHIFTOUT(base, tpll->divm_mask); 1030 divn = __SHIFTOUT(base, tpll->divn_mask); 1031 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1032 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1033 } else { 1034 divp = __SHIFTOUT(base, tpll->divp_mask); 1035 } 1036 1037 rate = (uint64_t)rate_parent * divn; 1038 return rate / (divm << divp); 1039 } 1040 1041 static int 1042 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 1043 struct tegra_clk *tclk, u_int rate) 1044 { 1045 struct tegra_pll_clk *tpll = &tclk->u.pll; 1046 bus_space_tag_t bst = sc->sc_bst; 1047 bus_space_handle_t bsh = sc->sc_bsh; 1048 struct clk *clk_parent; 1049 uint32_t bp, base; 1050 1051 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1052 if (clk_parent == NULL) 1053 return EIO; 1054 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 1055 if (rate_parent == 0) 1056 return EIO; 1057 1058 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1059 const u_int divm = 1; 1060 const u_int divn = rate / rate_parent; 1061 const u_int divp = 0; 1062 1063 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1064 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1065 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1066 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1067 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1068 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1069 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1070 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1071 1072 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1073 base &= ~CAR_PLLX_BASE_DIVM; 1074 base &= ~CAR_PLLX_BASE_DIVN; 1075 base &= ~CAR_PLLX_BASE_DIVP; 1076 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1077 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1078 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1079 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1080 1081 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1082 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1083 do { 1084 delay(2); 1085 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1086 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1087 delay(100); 1088 1089 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1090 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1091 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1092 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1093 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1094 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1095 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1096 1097 return 0; 1098 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1099 const u_int divm = 1; 1100 const u_int pldiv = 1; 1101 const u_int divn = (rate << pldiv) / rate_parent; 1102 1103 /* Set frequency */ 1104 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1105 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1106 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1107 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1108 CAR_PLLD2_BASE_REF_SRC_SEL | 1109 CAR_PLLD2_BASE_DIVM | 1110 CAR_PLLD2_BASE_DIVN | 1111 CAR_PLLD2_BASE_DIVP); 1112 1113 return 0; 1114 } else { 1115 /* TODO */ 1116 return EOPNOTSUPP; 1117 } 1118 } 1119 1120 static int 1121 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 1122 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1123 { 1124 struct tegra_mux_clk *tmux = &tclk->u.mux; 1125 bus_space_tag_t bst = sc->sc_bst; 1126 bus_space_handle_t bsh = sc->sc_bsh; 1127 uint32_t v; 1128 u_int src; 1129 1130 KASSERT(tclk->type == TEGRA_CLK_MUX); 1131 1132 for (src = 0; src < tmux->nparents; src++) { 1133 if (tmux->parents[src] == NULL) { 1134 continue; 1135 } 1136 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1137 break; 1138 } 1139 } 1140 if (src == tmux->nparents) { 1141 return EINVAL; 1142 } 1143 1144 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1145 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1146 /* Change IDDQ from 1 to 0 */ 1147 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1148 0, CAR_PLLD2_BASE_IDDQ); 1149 delay(2); 1150 1151 /* Enable lock */ 1152 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1153 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1154 1155 /* Enable PLLD2 */ 1156 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1157 CAR_PLLD2_BASE_ENABLE, 0); 1158 1159 /* Wait for lock */ 1160 do { 1161 delay(2); 1162 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1163 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1164 1165 delay(200); 1166 } 1167 1168 v = bus_space_read_4(bst, bsh, tmux->reg); 1169 v &= ~tmux->bits; 1170 v |= __SHIFTIN(src, tmux->bits); 1171 bus_space_write_4(bst, bsh, tmux->reg, v); 1172 1173 return 0; 1174 } 1175 1176 static struct tegra_clk * 1177 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1178 struct tegra_clk *tclk) 1179 { 1180 struct tegra_mux_clk *tmux = &tclk->u.mux; 1181 bus_space_tag_t bst = sc->sc_bst; 1182 bus_space_handle_t bsh = sc->sc_bsh; 1183 1184 KASSERT(tclk->type == TEGRA_CLK_MUX); 1185 1186 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1187 const u_int src = __SHIFTOUT(v, tmux->bits); 1188 1189 KASSERT(src < tmux->nparents); 1190 1191 if (tmux->parents[src] == NULL) { 1192 return NULL; 1193 } 1194 1195 return tegra124_car_clock_find(tmux->parents[src]); 1196 } 1197 1198 static u_int 1199 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1200 struct tegra_clk *tclk) 1201 { 1202 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1203 struct clk *clk_parent; 1204 1205 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1206 if (clk_parent == NULL) 1207 return 0; 1208 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1209 1210 return parent_rate / tfixed_div->div; 1211 } 1212 1213 static u_int 1214 tegra124_car_clock_calc_rate_frac_div(u_int rate, u_int raw_div) 1215 { 1216 raw_div += 2; 1217 rate *= 2; 1218 rate += raw_div - 1; 1219 rate /= raw_div; 1220 return rate; 1221 } 1222 1223 static u_int 1224 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1225 struct tegra_clk *tclk) 1226 { 1227 struct tegra_div_clk *tdiv = &tclk->u.div; 1228 bus_space_tag_t bst = sc->sc_bst; 1229 bus_space_handle_t bsh = sc->sc_bsh; 1230 struct clk *clk_parent; 1231 u_int rate; 1232 1233 KASSERT(tclk->type == TEGRA_CLK_DIV); 1234 1235 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1236 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1237 1238 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1239 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1240 1241 switch (tdiv->reg) { 1242 case CAR_CLKSRC_I2C1_REG: 1243 case CAR_CLKSRC_I2C2_REG: 1244 case CAR_CLKSRC_I2C3_REG: 1245 case CAR_CLKSRC_I2C4_REG: 1246 case CAR_CLKSRC_I2C5_REG: 1247 case CAR_CLKSRC_I2C6_REG: 1248 rate = parent_rate * 1 / (raw_div + 1); 1249 break; 1250 case CAR_CLKSRC_UARTA_REG: 1251 case CAR_CLKSRC_UARTB_REG: 1252 case CAR_CLKSRC_UARTC_REG: 1253 case CAR_CLKSRC_UARTD_REG: 1254 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1255 rate = tegra124_car_clock_calc_rate_frac_div( 1256 parent_rate, raw_div); 1257 } else { 1258 rate = parent_rate; 1259 } 1260 break; 1261 default: 1262 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate, 1263 raw_div); 1264 break; 1265 } 1266 1267 return rate; 1268 } 1269 1270 static int 1271 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1272 struct tegra_clk *tclk, u_int rate) 1273 { 1274 struct tegra_div_clk *tdiv = &tclk->u.div; 1275 bus_space_tag_t bst = sc->sc_bst; 1276 bus_space_handle_t bsh = sc->sc_bsh; 1277 struct clk *clk_parent; 1278 u_int raw_div; 1279 uint32_t v; 1280 1281 KASSERT(tclk->type == TEGRA_CLK_DIV); 1282 1283 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1284 if (clk_parent == NULL) 1285 return EINVAL; 1286 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1287 1288 v = bus_space_read_4(bst, bsh, tdiv->reg); 1289 1290 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1291 1292 switch (tdiv->reg) { 1293 case CAR_CLKSRC_UARTA_REG: 1294 case CAR_CLKSRC_UARTB_REG: 1295 case CAR_CLKSRC_UARTC_REG: 1296 case CAR_CLKSRC_UARTD_REG: 1297 if (rate == parent_rate) { 1298 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1299 } else { 1300 v |= CAR_CLKSRC_UART_DIV_ENB; 1301 raw_div = (parent_rate * 2) / rate - 2; 1302 } 1303 break; 1304 case CAR_CLKSRC_SATA_REG: 1305 if (rate) { 1306 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1307 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1308 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1309 raw_div = (parent_rate * 2) / rate - 2; 1310 } else { 1311 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1312 } 1313 break; 1314 case CAR_CLKSRC_I2C1_REG: 1315 case CAR_CLKSRC_I2C2_REG: 1316 case CAR_CLKSRC_I2C3_REG: 1317 case CAR_CLKSRC_I2C4_REG: 1318 case CAR_CLKSRC_I2C5_REG: 1319 case CAR_CLKSRC_I2C6_REG: 1320 if (rate) 1321 raw_div = parent_rate / rate - 1; 1322 break; 1323 case CAR_CLKSRC_SDMMC1_REG: 1324 case CAR_CLKSRC_SDMMC2_REG: 1325 case CAR_CLKSRC_SDMMC3_REG: 1326 case CAR_CLKSRC_SDMMC4_REG: 1327 if (rate) { 1328 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1329 u_int calc_rate = 1330 tegra124_car_clock_calc_rate_frac_div( 1331 parent_rate, raw_div); 1332 if (calc_rate <= rate) 1333 break; 1334 } 1335 if (raw_div == 0x100) 1336 return EINVAL; 1337 } 1338 break; 1339 default: 1340 if (rate) 1341 raw_div = (parent_rate * 2) / rate - 2; 1342 break; 1343 } 1344 1345 v &= ~tdiv->bits; 1346 v |= __SHIFTIN(raw_div, tdiv->bits); 1347 1348 bus_space_write_4(bst, bsh, tdiv->reg, v); 1349 1350 return 0; 1351 } 1352 1353 static int 1354 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1355 struct tegra_clk *tclk, bool enable) 1356 { 1357 struct tegra_gate_clk *tgate = &tclk->u.gate; 1358 bus_space_tag_t bst = sc->sc_bst; 1359 bus_space_handle_t bsh = sc->sc_bsh; 1360 bus_size_t reg; 1361 1362 KASSERT(tclk->type == TEGRA_CLK_GATE); 1363 1364 if (tgate->set_reg == tgate->clr_reg) { 1365 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1366 if (enable) { 1367 v |= tgate->bits; 1368 } else { 1369 v &= ~tgate->bits; 1370 } 1371 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1372 } else { 1373 if (enable) { 1374 reg = tgate->set_reg; 1375 } else { 1376 reg = tgate->clr_reg; 1377 } 1378 1379 if (reg == CAR_CLK_ENB_V_SET_REG && 1380 tgate->bits == CAR_DEV_V_SATA) { 1381 /* De-assert reset to SATA PADPLL */ 1382 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1383 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1384 delay(15); 1385 } 1386 bus_space_write_4(bst, bsh, reg, tgate->bits); 1387 } 1388 1389 return 0; 1390 } 1391 1392 static u_int 1393 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1394 { 1395 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1396 struct clk *clk_parent; 1397 1398 switch (tclk->type) { 1399 case TEGRA_CLK_FIXED: 1400 return tclk->u.fixed.rate; 1401 case TEGRA_CLK_PLL: 1402 return tegra124_car_clock_get_rate_pll(priv, tclk); 1403 case TEGRA_CLK_MUX: 1404 case TEGRA_CLK_GATE: 1405 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1406 if (clk_parent == NULL) 1407 return EINVAL; 1408 return tegra124_car_clock_get_rate(priv, clk_parent); 1409 case TEGRA_CLK_FIXED_DIV: 1410 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1411 case TEGRA_CLK_DIV: 1412 return tegra124_car_clock_get_rate_div(priv, tclk); 1413 default: 1414 panic("tegra124: unknown tclk type %d", tclk->type); 1415 } 1416 } 1417 1418 static int 1419 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1420 { 1421 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1422 struct clk *clk_parent; 1423 1424 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1425 1426 switch (tclk->type) { 1427 case TEGRA_CLK_FIXED: 1428 case TEGRA_CLK_MUX: 1429 return EIO; 1430 case TEGRA_CLK_FIXED_DIV: 1431 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1432 if (clk_parent == NULL) 1433 return EIO; 1434 return tegra124_car_clock_set_rate(priv, clk_parent, 1435 rate * tclk->u.fixed_div.div); 1436 case TEGRA_CLK_GATE: 1437 return EINVAL; 1438 case TEGRA_CLK_PLL: 1439 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1440 case TEGRA_CLK_DIV: 1441 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1442 default: 1443 panic("tegra124: unknown tclk type %d", tclk->type); 1444 } 1445 } 1446 1447 static int 1448 tegra124_car_clock_enable(void *priv, struct clk *clk) 1449 { 1450 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1451 struct clk *clk_parent; 1452 1453 if (tclk->type != TEGRA_CLK_GATE) { 1454 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1455 if (clk_parent == NULL) 1456 return 0; 1457 return tegra124_car_clock_enable(priv, clk_parent); 1458 } 1459 1460 return tegra124_car_clock_enable_gate(priv, tclk, true); 1461 } 1462 1463 static int 1464 tegra124_car_clock_disable(void *priv, struct clk *clk) 1465 { 1466 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1467 1468 if (tclk->type != TEGRA_CLK_GATE) 1469 return EINVAL; 1470 1471 return tegra124_car_clock_enable_gate(priv, tclk, false); 1472 } 1473 1474 static int 1475 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1476 struct clk *clk_parent) 1477 { 1478 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1479 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1480 struct clk *nclk_parent; 1481 1482 if (tclk->type != TEGRA_CLK_MUX) { 1483 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1484 if (nclk_parent == clk_parent || nclk_parent == NULL) 1485 return EINVAL; 1486 return tegra124_car_clock_set_parent(priv, nclk_parent, 1487 clk_parent); 1488 } 1489 1490 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1491 } 1492 1493 static struct clk * 1494 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1495 { 1496 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1497 struct tegra_clk *tclk_parent = NULL; 1498 1499 switch (tclk->type) { 1500 case TEGRA_CLK_FIXED: 1501 case TEGRA_CLK_PLL: 1502 case TEGRA_CLK_FIXED_DIV: 1503 case TEGRA_CLK_DIV: 1504 case TEGRA_CLK_GATE: 1505 if (tclk->parent) { 1506 tclk_parent = tegra124_car_clock_find(tclk->parent); 1507 } 1508 break; 1509 case TEGRA_CLK_MUX: 1510 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1511 break; 1512 } 1513 1514 if (tclk_parent == NULL) 1515 return NULL; 1516 1517 return TEGRA_CLK_BASE(tclk_parent); 1518 } 1519 1520 static void * 1521 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1522 { 1523 struct tegra124_car_softc * const sc = device_private(dev); 1524 struct tegra124_car_rst *rst; 1525 1526 if (len != sc->sc_reset_cells * 4) 1527 return NULL; 1528 1529 const u_int reset_id = be32dec(data); 1530 1531 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32) 1532 return NULL; 1533 1534 const u_int reg = reset_id / 32; 1535 1536 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1537 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1538 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1539 rst->mask = __BIT(reset_id % 32); 1540 1541 return rst; 1542 } 1543 1544 static void 1545 tegra124_car_reset_release(device_t dev, void *priv) 1546 { 1547 struct tegra124_car_rst *rst = priv; 1548 1549 kmem_free(rst, sizeof(*rst)); 1550 } 1551 1552 static int 1553 tegra124_car_reset_assert(device_t dev, void *priv) 1554 { 1555 struct tegra124_car_softc * const sc = device_private(dev); 1556 struct tegra124_car_rst *rst = priv; 1557 1558 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1559 1560 return 0; 1561 } 1562 1563 static int 1564 tegra124_car_reset_deassert(device_t dev, void *priv) 1565 { 1566 struct tegra124_car_softc * const sc = device_private(dev); 1567 struct tegra124_car_rst *rst = priv; 1568 1569 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1570 1571 return 0; 1572 } 1573
Indexes created Tue Sep 30 20:09:53 GMT 2025