tegra124_car.c revision 1.20
1 /* $NetBSD: tegra124_car.c,v 1.20 2020/04/30 03:40:52 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.20 2020/04/30 03:40:52 riastradh Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndsource.h> 39 #include <sys/atomic.h> 40 #include <sys/kmem.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/nvidia/tegra_reg.h> 45 #include <arm/nvidia/tegra124_carreg.h> 46 #include <arm/nvidia/tegra_clock.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra124_car_match(device_t, cfdata_t, void *); 53 static void tegra124_car_attach(device_t, device_t, void *); 54 55 static struct clk *tegra124_car_clock_decode(device_t, int, const void *, 56 size_t); 57 58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 59 .decode = tegra124_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra124_car_clock_id { 64 u_int id; 65 const char *name; 66 } tegra124_car_clock_ids[] = { 67 { 3, "ispb" }, 68 { 4, "rtc" }, 69 { 5, "timer" }, 70 { 6, "uarta" }, 71 { 9, "sdmmc2" }, 72 { 11, "i2s1" }, 73 { 12, "i2c1" }, 74 { 14, "sdmmc1" }, 75 { 15, "sdmmc4" }, 76 { 17, "pwm" }, 77 { 18, "i2s2" }, 78 { 22, "usbd" }, 79 { 23, "isp" }, 80 { 26, "disp2" }, 81 { 27, "disp1" }, 82 { 28, "host1x" }, 83 { 29, "vcp" }, 84 { 30, "i2s0" }, 85 { 32, "mc" }, 86 { 34, "apbdma" }, 87 { 36, "kbc" }, 88 { 40, "kfuse" }, 89 { 41, "spi1" }, 90 { 42, "nor" }, 91 { 44, "spi2" }, 92 { 46, "spi3" }, 93 { 47, "i2c5" }, 94 { 48, "dsia" }, 95 { 50, "mipi" }, 96 { 51, "hdmi" }, 97 { 52, "csi" }, 98 { 54, "i2c2" }, 99 { 55, "uartc" }, 100 { 56, "mipi_cal" }, 101 { 57, "emc" }, 102 { 58, "usb2" }, 103 { 59, "usb3" }, 104 { 61, "vde" }, 105 { 62, "bsea" }, 106 { 63, "bsev" }, 107 { 65, "uartd" }, 108 { 67, "i2c3" }, 109 { 68, "spi4" }, 110 { 69, "sdmmc3" }, 111 { 70, "pcie" }, 112 { 71, "owr" }, 113 { 72, "afi" }, 114 { 73, "csite" }, 115 { 76, "la" }, 116 { 77, "trace" }, 117 { 78, "soc_therm" }, 118 { 79, "dtv" }, 119 { 81, "i2cslow" }, 120 { 82, "dsib" }, 121 { 83, "tsec" }, 122 { 89, "xusb_host" }, 123 { 91, "msenc" }, 124 { 92, "csus" }, 125 { 99, "mselect" }, 126 { 100, "tsensor" }, 127 { 101, "i2s3" }, 128 { 102, "i2s4" }, 129 { 103, "i2c4" }, 130 { 104, "spi5" }, 131 { 105, "spi6" }, 132 { 106, "d_audio" }, 133 { 107, "apbif" }, 134 { 108, "dam0" }, 135 { 109, "dam1" }, 136 { 110, "dam2" }, 137 { 111, "hda2codec_2x" }, 138 { 113, "audio0_2x" }, 139 { 114, "audio1_2x" }, 140 { 115, "audio2_2x" }, 141 { 116, "audio3_2x" }, 142 { 117, "audio4_2x" }, 143 { 118, "spdif_2x" }, 144 { 119, "actmon" }, 145 { 120, "extern1" }, 146 { 121, "extern2" }, 147 { 122, "extern3" }, 148 { 123, "sata_oob" }, 149 { 124, "sata" }, 150 { 125, "hda" }, 151 { 127, "se" }, 152 { 128, "hda2hdmi" }, 153 { 129, "sata_cold" }, 154 { 144, "cilab" }, 155 { 145, "cilcd" }, 156 { 146, "cile" }, 157 { 147, "dsialp" }, 158 { 148, "dsiblp" }, 159 { 149, "entropy" }, 160 { 150, "dds" }, 161 { 152, "dp2" }, 162 { 153, "amx" }, 163 { 154, "adx" }, 164 { 156, "xusb_ss" }, 165 { 166, "i2c6" }, 166 { 171, "vim2_clk" }, 167 { 176, "hdmi_audio" }, 168 { 177, "clk72mhz" }, 169 { 178, "vic03" }, 170 { 180, "adx1" }, 171 { 181, "dpaux" }, 172 { 182, "sor0" }, 173 { 184, "gpu" }, 174 { 185, "amx1" }, 175 { 192, "uartb" }, 176 { 193, "vfir" }, 177 { 194, "spdif_in" }, 178 { 195, "spdif_out" }, 179 { 196, "vi" }, 180 { 197, "vi_sensor" }, 181 { 198, "fuse" }, 182 { 199, "fuse_burn" }, 183 { 200, "clk_32k" }, 184 { 201, "clk_m" }, 185 { 202, "clk_m_div2" }, 186 { 203, "clk_m_div4" }, 187 { 204, "pll_ref" }, 188 { 205, "pll_c" }, 189 { 206, "pll_c_out1" }, 190 { 207, "pll_c2" }, 191 { 208, "pll_c3" }, 192 { 209, "pll_m" }, 193 { 210, "pll_m_out1" }, 194 { 211, "pll_p_out0" }, 195 { 212, "pll_p_out1" }, 196 { 213, "pll_p_out2" }, 197 { 214, "pll_p_out3" }, 198 { 215, "pll_p_out4" }, 199 { 216, "pll_a" }, 200 { 217, "pll_a_out0" }, 201 { 218, "pll_d" }, 202 { 219, "pll_d_out0" }, 203 { 220, "pll_d2" }, 204 { 221, "pll_d2_out0" }, 205 { 222, "pll_u" }, 206 { 223, "pll_u_480m" }, 207 { 224, "pll_u_60m" }, 208 { 225, "pll_u_48m" }, 209 { 226, "pll_u_12m" }, 210 { 229, "pll_re_vco" }, 211 { 230, "pll_re_out" }, 212 { 231, "pll_e" }, 213 { 232, "spdif_in_sync" }, 214 { 233, "i2s0_sync" }, 215 { 234, "i2s1_sync" }, 216 { 235, "i2s2_sync" }, 217 { 236, "i2s3_sync" }, 218 { 237, "i2s4_sync" }, 219 { 238, "vimclk_sync" }, 220 { 239, "audio0" }, 221 { 240, "audio1" }, 222 { 241, "audio2" }, 223 { 242, "audio3" }, 224 { 243, "audio4" }, 225 { 244, "spdif" }, 226 { 245, "clk_out_1" }, 227 { 246, "clk_out_2" }, 228 { 247, "clk_out_3" }, 229 { 248, "blink" }, 230 { 252, "xusb_host_src" }, 231 { 253, "xusb_falcon_src" }, 232 { 254, "xusb_fs_src" }, 233 { 255, "xusb_ss_src" }, 234 { 256, "xusb_dev_src" }, 235 { 257, "xusb_dev" }, 236 { 258, "xusb_hs_src" }, 237 { 259, "sclk" }, 238 { 260, "hclk" }, 239 { 261, "pclk" }, 240 { 264, "dfll_ref" }, 241 { 265, "dfll_soc" }, 242 { 266, "vi_sensor2" }, 243 { 267, "pll_p_out5" }, 244 { 268, "cml0" }, 245 { 269, "cml1" }, 246 { 270, "pll_c4" }, 247 { 271, "pll_dp" }, 248 { 272, "pll_e_mux" }, 249 { 273, "pll_d_dsi_out" }, 250 { 300, "audio0_mux" }, 251 { 301, "audio1_mux" }, 252 { 302, "audio2_mux" }, 253 { 303, "audio3_mux" }, 254 { 304, "audio4_mux" }, 255 { 305, "spdif_mux" }, 256 { 306, "clk_out_1_mux" }, 257 { 307, "clk_out_2_mux" }, 258 { 308, "clk_out_3_mux" }, 259 { 311, "sor0_lvds" }, 260 { 312, "xusb_ss_div2" }, 261 { 313, "pll_m_ud" }, 262 { 314, "pll_c_ud" }, 263 { 227, "pll_x" }, 264 { 228, "pll_x_out0" }, 265 { 262, "cclk_g" }, 266 { 263, "cclk_lp" }, 267 { 315, "clk_max" }, 268 }; 269 270 static struct clk *tegra124_car_clock_get(void *, const char *); 271 static void tegra124_car_clock_put(void *, struct clk *); 272 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 273 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 274 static int tegra124_car_clock_enable(void *, struct clk *); 275 static int tegra124_car_clock_disable(void *, struct clk *); 276 static int tegra124_car_clock_set_parent(void *, struct clk *, 277 struct clk *); 278 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 279 280 static const struct clk_funcs tegra124_car_clock_funcs = { 281 .get = tegra124_car_clock_get, 282 .put = tegra124_car_clock_put, 283 .get_rate = tegra124_car_clock_get_rate, 284 .set_rate = tegra124_car_clock_set_rate, 285 .enable = tegra124_car_clock_enable, 286 .disable = tegra124_car_clock_disable, 287 .set_parent = tegra124_car_clock_set_parent, 288 .get_parent = tegra124_car_clock_get_parent, 289 }; 290 291 #define CLK_FIXED(_name, _rate) { \ 292 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 293 .u = { .fixed = { .rate = (_rate) } } \ 294 } 295 296 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 297 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 298 .parent = (_parent), \ 299 .u = { \ 300 .pll = { \ 301 .base_reg = (_base), \ 302 .divm_mask = (_divm), \ 303 .divn_mask = (_divn), \ 304 .divp_mask = (_divp), \ 305 } \ 306 } \ 307 } 308 309 #define CLK_MUX(_name, _reg, _bits, _p) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 311 .u = { \ 312 .mux = { \ 313 .nparents = __arraycount(_p), \ 314 .parents = (_p), \ 315 .reg = (_reg), \ 316 .bits = (_bits) \ 317 } \ 318 } \ 319 } 320 321 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 322 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 323 .parent = (_parent), \ 324 .u = { \ 325 .fixed_div = { \ 326 .div = (_div) \ 327 } \ 328 } \ 329 } 330 331 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 332 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 333 .parent = (_parent), \ 334 .u = { \ 335 .div = { \ 336 .reg = (_reg), \ 337 .bits = (_bits) \ 338 } \ 339 } \ 340 } 341 342 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 343 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 344 .type = TEGRA_CLK_GATE, \ 345 .parent = (_parent), \ 346 .u = { \ 347 .gate = { \ 348 .set_reg = (_set), \ 349 .clr_reg = (_clr), \ 350 .bits = (_bits), \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE_L(_name, _parent, _bits) \ 356 CLK_GATE(_name, _parent, \ 357 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 358 _bits) 359 360 #define CLK_GATE_H(_name, _parent, _bits) \ 361 CLK_GATE(_name, _parent, \ 362 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 363 _bits) 364 365 #define CLK_GATE_U(_name, _parent, _bits) \ 366 CLK_GATE(_name, _parent, \ 367 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 368 _bits) 369 370 #define CLK_GATE_V(_name, _parent, _bits) \ 371 CLK_GATE(_name, _parent, \ 372 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 373 _bits) 374 375 #define CLK_GATE_W(_name, _parent, _bits) \ 376 CLK_GATE(_name, _parent, \ 377 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 378 _bits) 379 380 #define CLK_GATE_X(_name, _parent, _bits) \ 381 CLK_GATE(_name, _parent, \ 382 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 383 _bits) 384 385 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 386 CLK_GATE(_name, _parent, _reg, _reg, _bits) 387 388 static const char *mux_uart_p[] = 389 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 390 "pll_m_out0", NULL, "clk_m" }; 391 static const char *mux_sdmmc_p[] = 392 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 393 "pll_m_out0", "pll_e_out0", "clk_m" }; 394 static const char *mux_i2c_p[] = 395 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 396 "pll_m_out0", NULL, "clk_m" }; 397 static const char *mux_spi_p[] = 398 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 399 "pll_m_out0", NULL, "clk_m" }; 400 static const char *mux_sata_p[] = 401 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 402 static const char *mux_hda_p[] = 403 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 404 "pll_m_out0", NULL, "clk_m" }; 405 static const char *mux_mselect_p[] = 406 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 407 "pll_m_out0", "clk_s", "clk_m" }; 408 static const char *mux_tsensor_p[] = 409 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 410 NULL, "clk_s" }; 411 static const char *mux_soc_therm_p[] = 412 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 413 "pll_c3_out0" }; 414 static const char *mux_host1x_p[] = 415 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 416 "pll_p_out0", NULL, "pll_a_out0" }; 417 static const char *mux_disp_p[] = 418 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 419 "pll_d2_out0", "clk_m" }; 420 static const char *mux_hdmi_p[] = 421 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 422 "pll_d2_out0", "clk_m" }; 423 static const char *mux_xusb_host_p[] = 424 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 425 "pll_re_out" }; 426 static const char *mux_xusb_ss_p[] = 427 { "clk_m", "pll_re_out", "clk_s", "pll_u_480", 428 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL }; 429 static const char *mux_xusb_fs_p[] = 430 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" }; 431 432 static struct tegra_clk tegra124_car_clocks[] = { 433 CLK_FIXED("clk_m", TEGRA124_REF_FREQ), 434 435 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 436 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 437 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 438 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 439 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 440 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 441 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 442 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 443 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 444 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 445 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 446 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 447 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 448 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 449 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG, 450 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 451 452 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 453 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 454 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 455 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 456 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 457 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 458 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 459 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 460 CLK_FIXED_DIV("pll_re_out", "pll_re", 1), 461 462 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 463 mux_uart_p), 464 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 465 mux_uart_p), 466 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 469 mux_uart_p), 470 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 471 mux_sdmmc_p), 472 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 473 mux_sdmmc_p), 474 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 475 mux_sdmmc_p), 476 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 477 mux_sdmmc_p), 478 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 479 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 480 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 485 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 486 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 487 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 488 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 489 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 490 CLK_MUX("mux_sata_oob", 491 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 492 CLK_MUX("mux_sata", 493 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 494 CLK_MUX("mux_hda2codec_2x", 495 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 496 mux_hda_p), 497 CLK_MUX("mux_hda", 498 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 499 CLK_MUX("mux_soc_therm", 500 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 501 mux_soc_therm_p), 502 CLK_MUX("mux_mselect", 503 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 504 mux_mselect_p), 505 CLK_MUX("mux_tsensor", 506 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 507 mux_tsensor_p), 508 CLK_MUX("mux_host1x", 509 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 510 mux_host1x_p), 511 CLK_MUX("mux_disp1", 512 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 513 mux_disp_p), 514 CLK_MUX("mux_disp2", 515 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 516 mux_disp_p), 517 CLK_MUX("mux_hdmi", 518 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 519 mux_hdmi_p), 520 CLK_MUX("mux_xusb_host", 521 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 522 mux_xusb_host_p), 523 CLK_MUX("mux_xusb_falcon", 524 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 525 mux_xusb_host_p), 526 CLK_MUX("mux_xusb_ss", 527 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 528 mux_xusb_ss_p), 529 CLK_MUX("mux_xusb_fs", 530 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 531 mux_xusb_fs_p), 532 533 CLK_DIV("div_uarta", "mux_uarta", 534 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 535 CLK_DIV("div_uartb", "mux_uartb", 536 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 537 CLK_DIV("div_uartc", "mux_uartc", 538 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 539 CLK_DIV("div_uartd", "mux_uartd", 540 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 541 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 542 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 543 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 544 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 545 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 546 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 547 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 548 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 549 CLK_DIV("div_i2c1", "mux_i2c1", 550 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 551 CLK_DIV("div_i2c2", "mux_i2c2", 552 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 553 CLK_DIV("div_i2c3", "mux_i2c3", 554 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 555 CLK_DIV("div_i2c4", "mux_i2c4", 556 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 557 CLK_DIV("div_i2c5", "mux_i2c5", 558 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 559 CLK_DIV("div_i2c6", "mux_i2c6", 560 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 561 CLK_DIV("div_spi1", "mux_spi1", 562 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV), 563 CLK_DIV("div_spi2", "mux_spi2", 564 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV), 565 CLK_DIV("div_spi3", "mux_spi3", 566 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV), 567 CLK_DIV("div_spi4", "mux_spi4", 568 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV), 569 CLK_DIV("div_spi5", "mux_spi5", 570 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV), 571 CLK_DIV("div_spi6", "mux_spi6", 572 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV), 573 CLK_DIV("div_sata_oob", "mux_sata_oob", 574 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 575 CLK_DIV("div_sata", "mux_sata", 576 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 577 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 578 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 579 CLK_DIV("div_hda", "mux_hda", 580 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 581 CLK_DIV("div_soc_therm", "mux_soc_therm", 582 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 583 CLK_DIV("div_mselect", "mux_mselect", 584 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 585 CLK_DIV("div_tsensor", "mux_tsensor", 586 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 587 CLK_DIV("div_host1x", "mux_host1x", 588 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 589 CLK_DIV("div_hdmi", "mux_hdmi", 590 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 591 CLK_DIV("div_pll_p_out5", "pll_p", 592 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 593 CLK_DIV("xusb_host_src", "mux_xusb_host", 594 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 595 CLK_DIV("xusb_ss_src", "mux_xusb_ss", 596 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 597 CLK_DIV("xusb_fs_src", "mux_xusb_fs", 598 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 599 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon", 600 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 601 602 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 603 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 604 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 605 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 606 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 607 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 608 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 609 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 610 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 611 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 612 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 613 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 614 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 615 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 616 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1), 617 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2), 618 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3), 619 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4), 620 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5), 621 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6), 622 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 623 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 624 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 625 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 626 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 627 CLK_GATE_SIMPLE("cml0", "pll_e", 628 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 629 CLK_GATE_SIMPLE("cml1", "pll_e", 630 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 631 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 632 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 633 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 634 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 635 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 636 CLK_GATE_V("mselect", "div_mselect", CAR_DEV_V_MSELECT), 637 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 638 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 639 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 640 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 641 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 642 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5", 643 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 644 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST), 645 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS), 646 CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU), 647 CLK_GATE_H("apbdma", "clk_m", CAR_DEV_H_APBDMA), 648 CLK_GATE_U("pcie", "mselect", CAR_DEV_U_PCIE), 649 CLK_GATE_U("afi", "mselect", CAR_DEV_U_AFI), 650 }; 651 652 struct tegra124_init_parent { 653 const char *clock; 654 const char *parent; 655 } tegra124_init_parents[] = { 656 { "sata_oob", "pll_p_out0" }, 657 { "sata", "pll_p_out0" }, 658 { "hda", "pll_p_out0" }, 659 { "hda2codec_2x", "pll_p_out0" }, 660 { "soc_therm", "pll_p_out0" }, 661 { "tsensor", "clk_m" }, 662 { "xusb_host_src", "pll_p_out0" }, 663 { "xusb_falcon_src", "pll_p_out0" }, 664 { "xusb_ss_src", "pll_u_480" }, 665 { "xusb_fs_src", "pll_u_48" }, 666 { "host1x", "pll_p_out0" }, 667 }; 668 669 struct tegra124_car_rst { 670 u_int set_reg; 671 u_int clr_reg; 672 u_int mask; 673 }; 674 675 static struct tegra124_car_reset_reg { 676 u_int set_reg; 677 u_int clr_reg; 678 } tegra124_car_reset_regs[] = { 679 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 680 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 681 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 682 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 683 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 684 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 685 }; 686 687 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 688 static void tegra124_car_reset_release(device_t, void *); 689 static int tegra124_car_reset_assert(device_t, void *); 690 static int tegra124_car_reset_deassert(device_t, void *); 691 692 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 693 .acquire = tegra124_car_reset_acquire, 694 .release = tegra124_car_reset_release, 695 .reset_assert = tegra124_car_reset_assert, 696 .reset_deassert = tegra124_car_reset_deassert, 697 }; 698 699 struct tegra124_car_softc { 700 device_t sc_dev; 701 bus_space_tag_t sc_bst; 702 bus_space_handle_t sc_bsh; 703 704 struct clk_domain sc_clkdom; 705 706 u_int sc_clock_cells; 707 u_int sc_reset_cells; 708 709 kmutex_t sc_rndlock; 710 krndsource_t sc_rndsource; 711 }; 712 713 static void tegra124_car_init(struct tegra124_car_softc *); 714 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 715 static void tegra124_car_xusb_init(struct tegra124_car_softc *); 716 static void tegra124_car_watchdog_init(struct tegra124_car_softc *); 717 static void tegra124_car_parent_init(struct tegra124_car_softc *); 718 719 static void tegra124_car_rnd_attach(device_t); 720 static void tegra124_car_rnd_callback(size_t, void *); 721 722 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 723 tegra124_car_match, tegra124_car_attach, NULL, NULL); 724 725 static int 726 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 727 { 728 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 729 struct fdt_attach_args * const faa = aux; 730 731 #if 0 732 return of_match_compatible(faa->faa_phandle, compatible); 733 #else 734 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 735 return 0; 736 737 return 999; 738 #endif 739 } 740 741 static void 742 tegra124_car_attach(device_t parent, device_t self, void *aux) 743 { 744 struct tegra124_car_softc * const sc = device_private(self); 745 struct fdt_attach_args * const faa = aux; 746 const int phandle = faa->faa_phandle; 747 bus_addr_t addr; 748 bus_size_t size; 749 int error, n; 750 751 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 752 aprint_error(": couldn't get registers\n"); 753 return; 754 } 755 756 sc->sc_dev = self; 757 sc->sc_bst = faa->faa_bst; 758 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 759 if (error) { 760 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 761 return; 762 } 763 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 764 sc->sc_clock_cells = 1; 765 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 766 sc->sc_reset_cells = 1; 767 768 aprint_naive("\n"); 769 aprint_normal(": CAR\n"); 770 771 sc->sc_clkdom.name = device_xname(self); 772 sc->sc_clkdom.funcs = &tegra124_car_clock_funcs; 773 sc->sc_clkdom.priv = sc; 774 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 775 tegra124_car_clocks[n].base.domain = &sc->sc_clkdom; 776 clk_attach(&tegra124_car_clocks[n].base); 777 } 778 779 fdtbus_register_clock_controller(self, phandle, 780 &tegra124_car_fdtclock_funcs); 781 fdtbus_register_reset_controller(self, phandle, 782 &tegra124_car_fdtreset_funcs); 783 784 tegra124_car_init(sc); 785 786 config_interrupts(self, tegra124_car_rnd_attach); 787 } 788 789 static void 790 tegra124_car_init(struct tegra124_car_softc *sc) 791 { 792 tegra124_car_parent_init(sc); 793 tegra124_car_utmip_init(sc); 794 tegra124_car_xusb_init(sc); 795 tegra124_car_watchdog_init(sc); 796 } 797 798 static void 799 tegra124_car_parent_init(struct tegra124_car_softc *sc) 800 { 801 struct clk *clk, *clk_parent; 802 int error; 803 u_int n; 804 805 for (n = 0; n < __arraycount(tegra124_init_parents); n++) { 806 clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock); 807 KASSERT(clk != NULL); 808 clk_parent = clk_get(&sc->sc_clkdom, 809 tegra124_init_parents[n].parent); 810 KASSERT(clk_parent != NULL); 811 812 error = clk_set_parent(clk, clk_parent); 813 if (error) { 814 aprint_error_dev(sc->sc_dev, 815 "couldn't set '%s' parent to '%s': %d\n", 816 clk->name, clk_parent->name, error); 817 } 818 clk_put(clk_parent); 819 clk_put(clk); 820 } 821 } 822 823 static void 824 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 825 { 826 bus_space_tag_t bst = sc->sc_bst; 827 bus_space_handle_t bsh = sc->sc_bsh; 828 829 const u_int enable_dly_count = 0x02; 830 const u_int stable_count = 0x2f; 831 const u_int active_dly_count = 0x04; 832 const u_int xtal_freq_count = 0x76; 833 834 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 835 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 836 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 837 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 838 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 839 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 840 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 841 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 842 843 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 844 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 845 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 846 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 847 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 848 849 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 850 0, 851 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 852 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 853 854 } 855 856 static void 857 tegra124_car_xusb_init(struct tegra124_car_softc *sc) 858 { 859 const bus_space_tag_t bst = sc->sc_bst; 860 const bus_space_handle_t bsh = sc->sc_bsh; 861 uint32_t val; 862 863 /* XXX do this all better */ 864 865 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 866 867 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 868 0, CAR_PLLREFE_MISC_IDDQ); 869 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 870 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 871 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 872 873 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 874 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 875 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 876 CAR_PLLREFE_BASE_ENABLE, 0); 877 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 878 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 879 880 do { 881 delay(2); 882 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 883 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 884 885 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 886 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 887 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 888 CAR_PLLE_BASE_ENABLE, 0); 889 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 890 CAR_PLLE_MISC_LOCK_ENABLE, 0); 891 892 do { 893 delay(2); 894 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 895 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 896 897 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 898 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 899 } 900 901 static void 902 tegra124_car_watchdog_init(struct tegra124_car_softc *sc) 903 { 904 const bus_space_tag_t bst = sc->sc_bst; 905 const bus_space_handle_t bsh = sc->sc_bsh; 906 907 /* Enable watchdog timer reset for system */ 908 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 909 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 910 } 911 912 static void 913 tegra124_car_rnd_attach(device_t self) 914 { 915 struct tegra124_car_softc * const sc = device_private(self); 916 917 mutex_init(&sc->sc_rndlock, MUTEX_DEFAULT, IPL_VM); 918 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 919 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 920 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 921 } 922 923 static void 924 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 925 { 926 struct tegra124_car_softc * const sc = priv; 927 uint16_t buf[512]; 928 uint32_t cnt; 929 930 mutex_enter(&sc->sc_rndlock); 931 while (bytes_wanted) { 932 const u_int nbytes = MIN(bytes_wanted, 1024); 933 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) { 934 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 935 CAR_PLL_LFSR_REG) & 0xffff; 936 } 937 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes, 938 nbytes * NBBY); 939 bytes_wanted -= MIN(bytes_wanted, nbytes); 940 } 941 explicit_memset(buf, 0, sizeof(buf)); 942 mutex_exit(&sc->sc_rndlock); 943 } 944 945 static struct tegra_clk * 946 tegra124_car_clock_find(const char *name) 947 { 948 u_int n; 949 950 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 951 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 952 return &tegra124_car_clocks[n]; 953 } 954 } 955 956 return NULL; 957 } 958 959 static struct tegra_clk * 960 tegra124_car_clock_find_by_id(u_int clock_id) 961 { 962 u_int n; 963 964 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 965 if (tegra124_car_clock_ids[n].id == clock_id) { 966 const char *name = tegra124_car_clock_ids[n].name; 967 return tegra124_car_clock_find(name); 968 } 969 } 970 971 return NULL; 972 } 973 974 static struct clk * 975 tegra124_car_clock_decode(device_t dev, int cc_phandle, const void *data, 976 size_t len) 977 { 978 struct tegra124_car_softc * const sc = device_private(dev); 979 struct tegra_clk *tclk; 980 981 if (len != sc->sc_clock_cells * 4) { 982 return NULL; 983 } 984 985 const u_int clock_id = be32dec(data); 986 987 tclk = tegra124_car_clock_find_by_id(clock_id); 988 if (tclk) 989 return TEGRA_CLK_BASE(tclk); 990 991 return NULL; 992 } 993 994 static struct clk * 995 tegra124_car_clock_get(void *priv, const char *name) 996 { 997 struct tegra_clk *tclk; 998 999 tclk = tegra124_car_clock_find(name); 1000 if (tclk == NULL) 1001 return NULL; 1002 1003 atomic_inc_uint(&tclk->refcnt); 1004 1005 return TEGRA_CLK_BASE(tclk); 1006 } 1007 1008 static void 1009 tegra124_car_clock_put(void *priv, struct clk *clk) 1010 { 1011 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1012 1013 KASSERT(tclk->refcnt > 0); 1014 1015 atomic_dec_uint(&tclk->refcnt); 1016 } 1017 1018 static u_int 1019 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 1020 struct tegra_clk *tclk) 1021 { 1022 struct tegra_pll_clk *tpll = &tclk->u.pll; 1023 struct tegra_clk *tclk_parent; 1024 bus_space_tag_t bst = sc->sc_bst; 1025 bus_space_handle_t bsh = sc->sc_bsh; 1026 u_int divm, divn, divp; 1027 uint64_t rate; 1028 1029 KASSERT(tclk->type == TEGRA_CLK_PLL); 1030 1031 tclk_parent = tegra124_car_clock_find(tclk->parent); 1032 KASSERT(tclk_parent != NULL); 1033 1034 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 1035 TEGRA_CLK_BASE(tclk_parent)); 1036 1037 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1038 divm = __SHIFTOUT(base, tpll->divm_mask); 1039 divn = __SHIFTOUT(base, tpll->divn_mask); 1040 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1041 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1042 } else { 1043 divp = __SHIFTOUT(base, tpll->divp_mask); 1044 } 1045 1046 rate = (uint64_t)rate_parent * divn; 1047 return rate / (divm << divp); 1048 } 1049 1050 static int 1051 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 1052 struct tegra_clk *tclk, u_int rate) 1053 { 1054 struct tegra_pll_clk *tpll = &tclk->u.pll; 1055 bus_space_tag_t bst = sc->sc_bst; 1056 bus_space_handle_t bsh = sc->sc_bsh; 1057 struct clk *clk_parent; 1058 uint32_t bp, base; 1059 1060 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1061 if (clk_parent == NULL) 1062 return EIO; 1063 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 1064 if (rate_parent == 0) 1065 return EIO; 1066 1067 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1068 const u_int divm = 1; 1069 const u_int divn = rate / rate_parent; 1070 const u_int divp = 0; 1071 1072 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1073 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1074 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1075 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1076 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1077 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1078 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1079 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1080 1081 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1082 base &= ~CAR_PLLX_BASE_DIVM; 1083 base &= ~CAR_PLLX_BASE_DIVN; 1084 base &= ~CAR_PLLX_BASE_DIVP; 1085 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1086 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1087 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1088 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1089 1090 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1091 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1092 do { 1093 delay(2); 1094 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1095 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1096 delay(100); 1097 1098 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1099 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1100 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1101 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1102 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1103 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1104 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1105 1106 return 0; 1107 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1108 const u_int divm = 1; 1109 const u_int pldiv = 1; 1110 const u_int divn = (rate << pldiv) / rate_parent; 1111 1112 /* Set frequency */ 1113 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1114 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1115 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1116 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1117 CAR_PLLD2_BASE_REF_SRC_SEL | 1118 CAR_PLLD2_BASE_DIVM | 1119 CAR_PLLD2_BASE_DIVN | 1120 CAR_PLLD2_BASE_DIVP); 1121 1122 return 0; 1123 } else { 1124 /* TODO */ 1125 return EOPNOTSUPP; 1126 } 1127 } 1128 1129 static int 1130 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 1131 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1132 { 1133 struct tegra_mux_clk *tmux = &tclk->u.mux; 1134 bus_space_tag_t bst = sc->sc_bst; 1135 bus_space_handle_t bsh = sc->sc_bsh; 1136 uint32_t v; 1137 u_int src; 1138 1139 KASSERT(tclk->type == TEGRA_CLK_MUX); 1140 1141 for (src = 0; src < tmux->nparents; src++) { 1142 if (tmux->parents[src] == NULL) { 1143 continue; 1144 } 1145 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1146 break; 1147 } 1148 } 1149 if (src == tmux->nparents) { 1150 return EINVAL; 1151 } 1152 1153 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1154 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1155 /* Change IDDQ from 1 to 0 */ 1156 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1157 0, CAR_PLLD2_BASE_IDDQ); 1158 delay(2); 1159 1160 /* Enable lock */ 1161 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1162 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1163 1164 /* Enable PLLD2 */ 1165 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1166 CAR_PLLD2_BASE_ENABLE, 0); 1167 1168 /* Wait for lock */ 1169 do { 1170 delay(2); 1171 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1172 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1173 1174 delay(200); 1175 } 1176 1177 v = bus_space_read_4(bst, bsh, tmux->reg); 1178 v &= ~tmux->bits; 1179 v |= __SHIFTIN(src, tmux->bits); 1180 bus_space_write_4(bst, bsh, tmux->reg, v); 1181 1182 return 0; 1183 } 1184 1185 static struct tegra_clk * 1186 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1187 struct tegra_clk *tclk) 1188 { 1189 struct tegra_mux_clk *tmux = &tclk->u.mux; 1190 bus_space_tag_t bst = sc->sc_bst; 1191 bus_space_handle_t bsh = sc->sc_bsh; 1192 1193 KASSERT(tclk->type == TEGRA_CLK_MUX); 1194 1195 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1196 const u_int src = __SHIFTOUT(v, tmux->bits); 1197 1198 KASSERT(src < tmux->nparents); 1199 1200 if (tmux->parents[src] == NULL) { 1201 return NULL; 1202 } 1203 1204 return tegra124_car_clock_find(tmux->parents[src]); 1205 } 1206 1207 static u_int 1208 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1209 struct tegra_clk *tclk) 1210 { 1211 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1212 struct clk *clk_parent; 1213 1214 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1215 if (clk_parent == NULL) 1216 return 0; 1217 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1218 1219 return parent_rate / tfixed_div->div; 1220 } 1221 1222 static u_int 1223 tegra124_car_clock_calc_rate_frac_div(u_int rate, u_int raw_div) 1224 { 1225 raw_div += 2; 1226 rate *= 2; 1227 rate += raw_div - 1; 1228 rate /= raw_div; 1229 return rate; 1230 } 1231 1232 static u_int 1233 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1234 struct tegra_clk *tclk) 1235 { 1236 struct tegra_div_clk *tdiv = &tclk->u.div; 1237 bus_space_tag_t bst = sc->sc_bst; 1238 bus_space_handle_t bsh = sc->sc_bsh; 1239 struct clk *clk_parent; 1240 u_int rate; 1241 1242 KASSERT(tclk->type == TEGRA_CLK_DIV); 1243 1244 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1245 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1246 1247 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1248 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1249 1250 switch (tdiv->reg) { 1251 case CAR_CLKSRC_I2C1_REG: 1252 case CAR_CLKSRC_I2C2_REG: 1253 case CAR_CLKSRC_I2C3_REG: 1254 case CAR_CLKSRC_I2C4_REG: 1255 case CAR_CLKSRC_I2C5_REG: 1256 case CAR_CLKSRC_I2C6_REG: 1257 rate = parent_rate * 1 / (raw_div + 1); 1258 break; 1259 case CAR_CLKSRC_UARTA_REG: 1260 case CAR_CLKSRC_UARTB_REG: 1261 case CAR_CLKSRC_UARTC_REG: 1262 case CAR_CLKSRC_UARTD_REG: 1263 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1264 rate = tegra124_car_clock_calc_rate_frac_div( 1265 parent_rate, raw_div); 1266 } else { 1267 rate = parent_rate; 1268 } 1269 break; 1270 default: 1271 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate, 1272 raw_div); 1273 break; 1274 } 1275 1276 return rate; 1277 } 1278 1279 static int 1280 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1281 struct tegra_clk *tclk, u_int rate) 1282 { 1283 struct tegra_div_clk *tdiv = &tclk->u.div; 1284 bus_space_tag_t bst = sc->sc_bst; 1285 bus_space_handle_t bsh = sc->sc_bsh; 1286 struct clk *clk_parent; 1287 u_int raw_div; 1288 uint32_t v; 1289 1290 KASSERT(tclk->type == TEGRA_CLK_DIV); 1291 1292 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1293 if (clk_parent == NULL) 1294 return EINVAL; 1295 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1296 1297 v = bus_space_read_4(bst, bsh, tdiv->reg); 1298 1299 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1300 1301 switch (tdiv->reg) { 1302 case CAR_CLKSRC_UARTA_REG: 1303 case CAR_CLKSRC_UARTB_REG: 1304 case CAR_CLKSRC_UARTC_REG: 1305 case CAR_CLKSRC_UARTD_REG: 1306 if (rate == parent_rate) { 1307 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1308 } else { 1309 v |= CAR_CLKSRC_UART_DIV_ENB; 1310 raw_div = (parent_rate * 2) / rate - 2; 1311 } 1312 break; 1313 case CAR_CLKSRC_SATA_REG: 1314 if (rate) { 1315 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1316 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1317 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1318 raw_div = (parent_rate * 2) / rate - 2; 1319 } else { 1320 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1321 } 1322 break; 1323 case CAR_CLKSRC_I2C1_REG: 1324 case CAR_CLKSRC_I2C2_REG: 1325 case CAR_CLKSRC_I2C3_REG: 1326 case CAR_CLKSRC_I2C4_REG: 1327 case CAR_CLKSRC_I2C5_REG: 1328 case CAR_CLKSRC_I2C6_REG: 1329 if (rate) 1330 raw_div = parent_rate / rate - 1; 1331 break; 1332 case CAR_CLKSRC_SDMMC1_REG: 1333 case CAR_CLKSRC_SDMMC2_REG: 1334 case CAR_CLKSRC_SDMMC3_REG: 1335 case CAR_CLKSRC_SDMMC4_REG: 1336 if (rate) { 1337 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1338 u_int calc_rate = 1339 tegra124_car_clock_calc_rate_frac_div( 1340 parent_rate, raw_div); 1341 if (calc_rate <= rate) 1342 break; 1343 } 1344 if (raw_div == 0x100) 1345 return EINVAL; 1346 } 1347 break; 1348 default: 1349 if (rate) 1350 raw_div = (parent_rate * 2) / rate - 2; 1351 break; 1352 } 1353 1354 v &= ~tdiv->bits; 1355 v |= __SHIFTIN(raw_div, tdiv->bits); 1356 1357 bus_space_write_4(bst, bsh, tdiv->reg, v); 1358 1359 return 0; 1360 } 1361 1362 static int 1363 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1364 struct tegra_clk *tclk, bool enable) 1365 { 1366 struct tegra_gate_clk *tgate = &tclk->u.gate; 1367 bus_space_tag_t bst = sc->sc_bst; 1368 bus_space_handle_t bsh = sc->sc_bsh; 1369 bus_size_t reg; 1370 1371 KASSERT(tclk->type == TEGRA_CLK_GATE); 1372 1373 if (tgate->set_reg == tgate->clr_reg) { 1374 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1375 if (enable) { 1376 v |= tgate->bits; 1377 } else { 1378 v &= ~tgate->bits; 1379 } 1380 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1381 } else { 1382 if (enable) { 1383 reg = tgate->set_reg; 1384 } else { 1385 reg = tgate->clr_reg; 1386 } 1387 1388 if (reg == CAR_CLK_ENB_V_SET_REG && 1389 tgate->bits == CAR_DEV_V_SATA) { 1390 /* De-assert reset to SATA PADPLL */ 1391 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1392 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1393 delay(15); 1394 } 1395 bus_space_write_4(bst, bsh, reg, tgate->bits); 1396 } 1397 1398 return 0; 1399 } 1400 1401 static u_int 1402 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1403 { 1404 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1405 struct clk *clk_parent; 1406 1407 switch (tclk->type) { 1408 case TEGRA_CLK_FIXED: 1409 return tclk->u.fixed.rate; 1410 case TEGRA_CLK_PLL: 1411 return tegra124_car_clock_get_rate_pll(priv, tclk); 1412 case TEGRA_CLK_MUX: 1413 case TEGRA_CLK_GATE: 1414 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1415 if (clk_parent == NULL) 1416 return EINVAL; 1417 return tegra124_car_clock_get_rate(priv, clk_parent); 1418 case TEGRA_CLK_FIXED_DIV: 1419 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1420 case TEGRA_CLK_DIV: 1421 return tegra124_car_clock_get_rate_div(priv, tclk); 1422 default: 1423 panic("tegra124: unknown tclk type %d", tclk->type); 1424 } 1425 } 1426 1427 static int 1428 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1429 { 1430 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1431 struct clk *clk_parent; 1432 1433 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1434 1435 switch (tclk->type) { 1436 case TEGRA_CLK_FIXED: 1437 case TEGRA_CLK_MUX: 1438 return EIO; 1439 case TEGRA_CLK_FIXED_DIV: 1440 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1441 if (clk_parent == NULL) 1442 return EIO; 1443 return tegra124_car_clock_set_rate(priv, clk_parent, 1444 rate * tclk->u.fixed_div.div); 1445 case TEGRA_CLK_GATE: 1446 return EINVAL; 1447 case TEGRA_CLK_PLL: 1448 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1449 case TEGRA_CLK_DIV: 1450 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1451 default: 1452 panic("tegra124: unknown tclk type %d", tclk->type); 1453 } 1454 } 1455 1456 static int 1457 tegra124_car_clock_enable(void *priv, struct clk *clk) 1458 { 1459 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1460 struct clk *clk_parent; 1461 1462 if (tclk->type != TEGRA_CLK_GATE) { 1463 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1464 if (clk_parent == NULL) 1465 return 0; 1466 return tegra124_car_clock_enable(priv, clk_parent); 1467 } 1468 1469 return tegra124_car_clock_enable_gate(priv, tclk, true); 1470 } 1471 1472 static int 1473 tegra124_car_clock_disable(void *priv, struct clk *clk) 1474 { 1475 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1476 1477 if (tclk->type != TEGRA_CLK_GATE) 1478 return EINVAL; 1479 1480 return tegra124_car_clock_enable_gate(priv, tclk, false); 1481 } 1482 1483 static int 1484 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1485 struct clk *clk_parent) 1486 { 1487 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1488 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1489 struct clk *nclk_parent; 1490 1491 if (tclk->type != TEGRA_CLK_MUX) { 1492 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1493 if (nclk_parent == clk_parent || nclk_parent == NULL) 1494 return EINVAL; 1495 return tegra124_car_clock_set_parent(priv, nclk_parent, 1496 clk_parent); 1497 } 1498 1499 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1500 } 1501 1502 static struct clk * 1503 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1504 { 1505 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1506 struct tegra_clk *tclk_parent = NULL; 1507 1508 switch (tclk->type) { 1509 case TEGRA_CLK_FIXED: 1510 case TEGRA_CLK_PLL: 1511 case TEGRA_CLK_FIXED_DIV: 1512 case TEGRA_CLK_DIV: 1513 case TEGRA_CLK_GATE: 1514 if (tclk->parent) { 1515 tclk_parent = tegra124_car_clock_find(tclk->parent); 1516 } 1517 break; 1518 case TEGRA_CLK_MUX: 1519 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1520 break; 1521 } 1522 1523 if (tclk_parent == NULL) 1524 return NULL; 1525 1526 return TEGRA_CLK_BASE(tclk_parent); 1527 } 1528 1529 static void * 1530 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1531 { 1532 struct tegra124_car_softc * const sc = device_private(dev); 1533 struct tegra124_car_rst *rst; 1534 1535 if (len != sc->sc_reset_cells * 4) 1536 return NULL; 1537 1538 const u_int reset_id = be32dec(data); 1539 1540 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32) 1541 return NULL; 1542 1543 const u_int reg = reset_id / 32; 1544 1545 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1546 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1547 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1548 rst->mask = __BIT(reset_id % 32); 1549 1550 return rst; 1551 } 1552 1553 static void 1554 tegra124_car_reset_release(device_t dev, void *priv) 1555 { 1556 struct tegra124_car_rst *rst = priv; 1557 1558 kmem_free(rst, sizeof(*rst)); 1559 } 1560 1561 static int 1562 tegra124_car_reset_assert(device_t dev, void *priv) 1563 { 1564 struct tegra124_car_softc * const sc = device_private(dev); 1565 struct tegra124_car_rst *rst = priv; 1566 1567 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1568 1569 return 0; 1570 } 1571 1572 static int 1573 tegra124_car_reset_deassert(device_t dev, void *priv) 1574 { 1575 struct tegra124_car_softc * const sc = device_private(dev); 1576 struct tegra124_car_rst *rst = priv; 1577 1578 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1579 1580 return 0; 1581 } 1582
Indexes created Wed Oct 22 13:09:56 GMT 2025