tegra124_car.c revision 1.8
1 /* $NetBSD: tegra124_car.c,v 1.8 2017/01/12 01:12:08 maya Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.8 2017/01/12 01:12:08 maya Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra124_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra124_car_match(device_t, cfdata_t, void *); 54 static void tegra124_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra124_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = { 59 .decode = tegra124_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra124_car_clock_id { 64 u_int id; 65 const char *name; 66 } tegra124_car_clock_ids[] = { 67 { 3, "ispb" }, 68 { 4, "rtc" }, 69 { 5, "timer" }, 70 { 6, "uarta" }, 71 { 9, "sdmmc2" }, 72 { 11, "i2s1" }, 73 { 12, "i2c1" }, 74 { 14, "sdmmc1" }, 75 { 15, "sdmmc4" }, 76 { 17, "pwm" }, 77 { 18, "i2s2" }, 78 { 22, "usbd" }, 79 { 23, "isp" }, 80 { 26, "disp2" }, 81 { 27, "disp1" }, 82 { 28, "host1x" }, 83 { 29, "vcp" }, 84 { 30, "i2s0" }, 85 { 32, "mc" }, 86 { 34, "apbdma" }, 87 { 36, "kbc" }, 88 { 40, "kfuse" }, 89 { 41, "spi1" }, 90 { 42, "nor" }, 91 { 44, "spi2" }, 92 { 46, "spi3" }, 93 { 47, "i2c5" }, 94 { 48, "dsia" }, 95 { 50, "mipi" }, 96 { 51, "hdmi" }, 97 { 52, "csi" }, 98 { 54, "i2c2" }, 99 { 55, "uartc" }, 100 { 56, "mipi_cal" }, 101 { 57, "emc" }, 102 { 58, "usb2" }, 103 { 59, "usb3" }, 104 { 61, "vde" }, 105 { 62, "bsea" }, 106 { 63, "bsev" }, 107 { 65, "uartd" }, 108 { 67, "i2c3" }, 109 { 68, "spi4" }, 110 { 69, "sdmmc3" }, 111 { 70, "pcie" }, 112 { 71, "owr" }, 113 { 72, "afi" }, 114 { 73, "csite" }, 115 { 76, "la" }, 116 { 77, "trace" }, 117 { 78, "soc_therm" }, 118 { 79, "dtv" }, 119 { 81, "i2cslow" }, 120 { 82, "dsib" }, 121 { 83, "tsec" }, 122 { 89, "xusb_host" }, 123 { 91, "msenc" }, 124 { 92, "csus" }, 125 { 99, "mselect" }, 126 { 100, "tsensor" }, 127 { 101, "i2s3" }, 128 { 102, "i2s4" }, 129 { 103, "i2c4" }, 130 { 104, "spi5" }, 131 { 105, "spi6" }, 132 { 106, "d_audio" }, 133 { 107, "apbif" }, 134 { 108, "dam0" }, 135 { 109, "dam1" }, 136 { 110, "dam2" }, 137 { 111, "hda2codec_2x" }, 138 { 113, "audio0_2x" }, 139 { 114, "audio1_2x" }, 140 { 115, "audio2_2x" }, 141 { 116, "audio3_2x" }, 142 { 117, "audio4_2x" }, 143 { 118, "spdif_2x" }, 144 { 119, "actmon" }, 145 { 120, "extern1" }, 146 { 121, "extern2" }, 147 { 122, "extern3" }, 148 { 123, "sata_oob" }, 149 { 124, "sata" }, 150 { 125, "hda" }, 151 { 127, "se" }, 152 { 128, "hda2hdmi" }, 153 { 129, "sata_cold" }, 154 { 144, "cilab" }, 155 { 145, "cilcd" }, 156 { 146, "cile" }, 157 { 147, "dsialp" }, 158 { 148, "dsiblp" }, 159 { 149, "entropy" }, 160 { 150, "dds" }, 161 { 152, "dp2" }, 162 { 153, "amx" }, 163 { 154, "adx" }, 164 { 156, "xusb_ss" }, 165 { 166, "i2c6" }, 166 { 171, "vim2_clk" }, 167 { 176, "hdmi_audio" }, 168 { 177, "clk72mhz" }, 169 { 178, "vic03" }, 170 { 180, "adx1" }, 171 { 181, "dpaux" }, 172 { 182, "sor0" }, 173 { 184, "gpu" }, 174 { 185, "amx1" }, 175 { 192, "uartb" }, 176 { 193, "vfir" }, 177 { 194, "spdif_in" }, 178 { 195, "spdif_out" }, 179 { 196, "vi" }, 180 { 197, "vi_sensor" }, 181 { 198, "fuse" }, 182 { 199, "fuse_burn" }, 183 { 200, "clk_32k" }, 184 { 201, "clk_m" }, 185 { 202, "clk_m_div2" }, 186 { 203, "clk_m_div4" }, 187 { 204, "pll_ref" }, 188 { 205, "pll_c" }, 189 { 206, "pll_c_out1" }, 190 { 207, "pll_c2" }, 191 { 208, "pll_c3" }, 192 { 209, "pll_m" }, 193 { 210, "pll_m_out1" }, 194 { 211, "pll_p_out0" }, 195 { 212, "pll_p_out1" }, 196 { 213, "pll_p_out2" }, 197 { 214, "pll_p_out3" }, 198 { 215, "pll_p_out4" }, 199 { 216, "pll_a" }, 200 { 217, "pll_a_out0" }, 201 { 218, "pll_d" }, 202 { 219, "pll_d_out0" }, 203 { 220, "pll_d2" }, 204 { 221, "pll_d2_out0" }, 205 { 222, "pll_u" }, 206 { 223, "pll_u_480m" }, 207 { 224, "pll_u_60m" }, 208 { 225, "pll_u_48m" }, 209 { 226, "pll_u_12m" }, 210 { 229, "pll_re_vco" }, 211 { 230, "pll_re_out" }, 212 { 231, "pll_e" }, 213 { 232, "spdif_in_sync" }, 214 { 233, "i2s0_sync" }, 215 { 234, "i2s1_sync" }, 216 { 235, "i2s2_sync" }, 217 { 236, "i2s3_sync" }, 218 { 237, "i2s4_sync" }, 219 { 238, "vimclk_sync" }, 220 { 239, "audio0" }, 221 { 240, "audio1" }, 222 { 241, "audio2" }, 223 { 242, "audio3" }, 224 { 243, "audio4" }, 225 { 244, "spdif" }, 226 { 245, "clk_out_1" }, 227 { 246, "clk_out_2" }, 228 { 247, "clk_out_3" }, 229 { 248, "blink" }, 230 { 252, "xusb_host_src" }, 231 { 253, "xusb_falcon_src" }, 232 { 254, "xusb_fs_src" }, 233 { 255, "xusb_ss_src" }, 234 { 256, "xusb_dev_src" }, 235 { 257, "xusb_dev" }, 236 { 258, "xusb_hs_src" }, 237 { 259, "sclk" }, 238 { 260, "hclk" }, 239 { 261, "pclk" }, 240 { 264, "dfll_ref" }, 241 { 265, "dfll_soc" }, 242 { 266, "vi_sensor2" }, 243 { 267, "pll_p_out5" }, 244 { 268, "cml0" }, 245 { 269, "cml1" }, 246 { 270, "pll_c4" }, 247 { 271, "pll_dp" }, 248 { 272, "pll_e_mux" }, 249 { 273, "pll_d_dsi_out" }, 250 { 300, "audio0_mux" }, 251 { 301, "audio1_mux" }, 252 { 302, "audio2_mux" }, 253 { 303, "audio3_mux" }, 254 { 304, "audio4_mux" }, 255 { 305, "spdif_mux" }, 256 { 306, "clk_out_1_mux" }, 257 { 307, "clk_out_2_mux" }, 258 { 308, "clk_out_3_mux" }, 259 { 311, "sor0_lvds" }, 260 { 312, "xusb_ss_div2" }, 261 { 313, "pll_m_ud" }, 262 { 314, "pll_c_ud" }, 263 { 227, "pll_x" }, 264 { 228, "pll_x_out0" }, 265 { 262, "cclk_g" }, 266 { 263, "cclk_lp" }, 267 { 315, "clk_max" }, 268 }; 269 270 static struct clk *tegra124_car_clock_get(void *, const char *); 271 static void tegra124_car_clock_put(void *, struct clk *); 272 static u_int tegra124_car_clock_get_rate(void *, struct clk *); 273 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int); 274 static int tegra124_car_clock_enable(void *, struct clk *); 275 static int tegra124_car_clock_disable(void *, struct clk *); 276 static int tegra124_car_clock_set_parent(void *, struct clk *, 277 struct clk *); 278 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *); 279 280 static const struct clk_funcs tegra124_car_clock_funcs = { 281 .get = tegra124_car_clock_get, 282 .put = tegra124_car_clock_put, 283 .get_rate = tegra124_car_clock_get_rate, 284 .set_rate = tegra124_car_clock_set_rate, 285 .enable = tegra124_car_clock_enable, 286 .disable = tegra124_car_clock_disable, 287 .set_parent = tegra124_car_clock_set_parent, 288 .get_parent = tegra124_car_clock_get_parent, 289 }; 290 291 #define CLK_FIXED(_name, _rate) { \ 292 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 293 .u = { .fixed = { .rate = (_rate) } } \ 294 } 295 296 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 297 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 298 .parent = (_parent), \ 299 .u = { \ 300 .pll = { \ 301 .base_reg = (_base), \ 302 .divm_mask = (_divm), \ 303 .divn_mask = (_divn), \ 304 .divp_mask = (_divp), \ 305 } \ 306 } \ 307 } 308 309 #define CLK_MUX(_name, _reg, _bits, _p) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 311 .u = { \ 312 .mux = { \ 313 .nparents = __arraycount(_p), \ 314 .parents = (_p), \ 315 .reg = (_reg), \ 316 .bits = (_bits) \ 317 } \ 318 } \ 319 } 320 321 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 322 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 323 .parent = (_parent), \ 324 .u = { \ 325 .fixed_div = { \ 326 .div = (_div) \ 327 } \ 328 } \ 329 } 330 331 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 332 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 333 .parent = (_parent), \ 334 .u = { \ 335 .div = { \ 336 .reg = (_reg), \ 337 .bits = (_bits) \ 338 } \ 339 } \ 340 } 341 342 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 343 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 344 .type = TEGRA_CLK_GATE, \ 345 .parent = (_parent), \ 346 .u = { \ 347 .gate = { \ 348 .set_reg = (_set), \ 349 .clr_reg = (_clr), \ 350 .bits = (_bits), \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE_L(_name, _parent, _bits) \ 356 CLK_GATE(_name, _parent, \ 357 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 358 _bits) 359 360 #define CLK_GATE_H(_name, _parent, _bits) \ 361 CLK_GATE(_name, _parent, \ 362 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 363 _bits) 364 365 #define CLK_GATE_U(_name, _parent, _bits) \ 366 CLK_GATE(_name, _parent, \ 367 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 368 _bits) 369 370 #define CLK_GATE_V(_name, _parent, _bits) \ 371 CLK_GATE(_name, _parent, \ 372 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 373 _bits) 374 375 #define CLK_GATE_W(_name, _parent, _bits) \ 376 CLK_GATE(_name, _parent, \ 377 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 378 _bits) 379 380 #define CLK_GATE_X(_name, _parent, _bits) \ 381 CLK_GATE(_name, _parent, \ 382 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 383 _bits) 384 385 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 386 CLK_GATE(_name, _parent, _reg, _reg, _bits) 387 388 static const char *mux_uart_p[] = 389 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 390 "pll_m_out0", NULL, "clk_m" }; 391 static const char *mux_sdmmc_p[] = 392 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 393 "pll_m_out0", "pll_e_out0", "clk_m" }; 394 static const char *mux_i2c_p[] = 395 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 396 "pll_m_out0", NULL, "clk_m" }; 397 static const char *mux_spi_p[] = 398 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 399 "pll_m_out0", NULL, "clk_m" }; 400 static const char *mux_sata_p[] = 401 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" }; 402 static const char *mux_hda_p[] = 403 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 404 "pll_m_out0", NULL, "clk_m" }; 405 static const char *mux_tsensor_p[] = 406 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m", 407 NULL, "clk_s" }; 408 static const char *mux_soc_therm_p[] = 409 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0", 410 "pll_c3_out0" }; 411 static const char *mux_host1x_p[] = 412 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 413 "pll_p_out0", NULL, "pll_a_out0" }; 414 static const char *mux_disp_p[] = 415 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 416 "pll_d2_out0", "clk_m" }; 417 static const char *mux_hdmi_p[] = 418 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0", 419 "pll_d2_out0", "clk_m" }; 420 static const char *mux_xusb_host_p[] = 421 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", 422 "pll_re_out" }; 423 static const char *mux_xusb_ss_p[] = 424 { "clk_m", "pll_re_out", "clk_s", "pll_u_480", 425 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL }; 426 static const char *mux_xusb_fs_p[] = 427 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" }; 428 429 static struct tegra_clk tegra124_car_clocks[] = { 430 CLK_FIXED("clk_m", TEGRA_REF_FREQ), 431 432 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG, 433 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 434 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG, 435 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 436 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG, 437 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ), 438 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG, 439 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 440 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG, 441 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 442 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG, 443 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 444 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG, 445 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 446 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG, 447 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 448 449 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1), 450 CLK_FIXED_DIV("pll_u_480", "pll_u", 1), 451 CLK_FIXED_DIV("pll_u_60", "pll_u", 8), 452 CLK_FIXED_DIV("pll_u_48", "pll_u", 10), 453 CLK_FIXED_DIV("pll_u_12", "pll_u", 40), 454 CLK_FIXED_DIV("pll_d_out", "pll_d", 1), 455 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2), 456 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1), 457 CLK_FIXED_DIV("pll_re_out", "pll_re", 1), 458 459 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 460 mux_uart_p), 461 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 462 mux_uart_p), 463 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 464 mux_uart_p), 465 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 466 mux_uart_p), 467 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 468 mux_sdmmc_p), 469 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 470 mux_sdmmc_p), 471 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc_p), 473 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc_p), 475 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 476 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 477 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 478 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 479 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 480 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 482 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 483 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 484 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 485 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 486 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p), 487 CLK_MUX("mux_sata_oob", 488 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p), 489 CLK_MUX("mux_sata", 490 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p), 491 CLK_MUX("mux_hda2codec_2x", 492 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 493 mux_hda_p), 494 CLK_MUX("mux_hda", 495 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p), 496 CLK_MUX("mux_soc_therm", 497 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 498 mux_soc_therm_p), 499 CLK_MUX("mux_tsensor", 500 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 501 mux_tsensor_p), 502 CLK_MUX("mux_host1x", 503 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC, 504 mux_host1x_p), 505 CLK_MUX("mux_disp1", 506 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC, 507 mux_disp_p), 508 CLK_MUX("mux_disp2", 509 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC, 510 mux_disp_p), 511 CLK_MUX("mux_hdmi", 512 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC, 513 mux_hdmi_p), 514 CLK_MUX("mux_xusb_host", 515 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 516 mux_xusb_host_p), 517 CLK_MUX("mux_xusb_falcon", 518 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 519 mux_xusb_host_p), 520 CLK_MUX("mux_xusb_ss", 521 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 522 mux_xusb_ss_p), 523 CLK_MUX("mux_xusb_fs", 524 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 525 mux_xusb_fs_p), 526 527 CLK_DIV("div_uarta", "mux_uarta", 528 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 529 CLK_DIV("div_uartb", "mux_uartb", 530 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 531 CLK_DIV("div_uartc", "mux_uartc", 532 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 533 CLK_DIV("div_uartd", "mux_uartd", 534 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 535 CLK_DIV("div_sdmmc1", "mux_sdmmc1", 536 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 537 CLK_DIV("div_sdmmc2", "mux_sdmmc2", 538 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 539 CLK_DIV("div_sdmmc3", "mux_sdmmc3", 540 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 541 CLK_DIV("div_sdmmc4", "mux_sdmmc4", 542 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 543 CLK_DIV("div_i2c1", "mux_i2c1", 544 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 545 CLK_DIV("div_i2c2", "mux_i2c2", 546 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 547 CLK_DIV("div_i2c3", "mux_i2c3", 548 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 549 CLK_DIV("div_i2c4", "mux_i2c4", 550 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 551 CLK_DIV("div_i2c5", "mux_i2c5", 552 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 553 CLK_DIV("div_i2c6", "mux_i2c6", 554 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 555 CLK_DIV("div_spi1", "mux_spi1", 556 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV), 557 CLK_DIV("div_spi2", "mux_spi2", 558 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV), 559 CLK_DIV("div_spi3", "mux_spi3", 560 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV), 561 CLK_DIV("div_spi4", "mux_spi4", 562 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV), 563 CLK_DIV("div_spi5", "mux_spi5", 564 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV), 565 CLK_DIV("div_spi6", "mux_spi6", 566 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV), 567 CLK_DIV("div_sata_oob", "mux_sata_oob", 568 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV), 569 CLK_DIV("div_sata", "mux_sata", 570 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV), 571 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x", 572 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 573 CLK_DIV("div_hda", "mux_hda", 574 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 575 CLK_DIV("div_soc_therm", "mux_soc_therm", 576 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 577 CLK_DIV("div_tsensor", "mux_tsensor", 578 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 579 CLK_DIV("div_host1x", "mux_host1x", 580 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR), 581 CLK_DIV("div_hdmi", "mux_hdmi", 582 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV), 583 CLK_DIV("div_pll_p_out5", "pll_p", 584 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO), 585 CLK_DIV("xusb_host_src", "mux_xusb_host", 586 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 587 CLK_DIV("xusb_ss_src", "mux_xusb_ss", 588 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 589 CLK_DIV("xusb_fs_src", "mux_xusb_fs", 590 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 591 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon", 592 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 593 594 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA), 595 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB), 596 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC), 597 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD), 598 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1), 599 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2), 600 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3), 601 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4), 602 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1), 603 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2), 604 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3), 605 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4), 606 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5), 607 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6), 608 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1), 609 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2), 610 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3), 611 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4), 612 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5), 613 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6), 614 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD), 615 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2), 616 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3), 617 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB), 618 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA), 619 CLK_GATE_SIMPLE("cml0", "pll_e", 620 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 621 CLK_GATE_SIMPLE("cml1", "pll_e", 622 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 623 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X), 624 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA), 625 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC), 626 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE), 627 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM), 628 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR), 629 CLK_GATE_SIMPLE("watchdog", "clk_m", CAR_RST_SOURCE_REG, 630 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN), 631 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X), 632 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1), 633 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2), 634 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI), 635 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5", 636 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN), 637 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST), 638 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS), 639 }; 640 641 struct tegra124_car_rst { 642 u_int set_reg; 643 u_int clr_reg; 644 u_int mask; 645 }; 646 647 static struct tegra124_car_reset_reg { 648 u_int set_reg; 649 u_int clr_reg; 650 } tegra124_car_reset_regs[] = { 651 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 652 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 653 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 654 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 655 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 656 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 657 }; 658 659 static void * tegra124_car_reset_acquire(device_t, const void *, size_t); 660 static void tegra124_car_reset_release(device_t, void *); 661 static int tegra124_car_reset_assert(device_t, void *); 662 static int tegra124_car_reset_deassert(device_t, void *); 663 664 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = { 665 .acquire = tegra124_car_reset_acquire, 666 .release = tegra124_car_reset_release, 667 .reset_assert = tegra124_car_reset_assert, 668 .reset_deassert = tegra124_car_reset_deassert, 669 }; 670 671 struct tegra124_car_softc { 672 device_t sc_dev; 673 bus_space_tag_t sc_bst; 674 bus_space_handle_t sc_bsh; 675 676 u_int sc_clock_cells; 677 u_int sc_reset_cells; 678 679 kmutex_t sc_rndlock; 680 krndsource_t sc_rndsource; 681 }; 682 683 static void tegra124_car_init(struct tegra124_car_softc *); 684 static void tegra124_car_utmip_init(struct tegra124_car_softc *); 685 static void tegra124_car_xusb_init(struct tegra124_car_softc *); 686 687 static void tegra124_car_rnd_attach(device_t); 688 static void tegra124_car_rnd_callback(size_t, void *); 689 690 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc), 691 tegra124_car_match, tegra124_car_attach, NULL, NULL); 692 693 static int 694 tegra124_car_match(device_t parent, cfdata_t cf, void *aux) 695 { 696 const char * const compatible[] = { "nvidia,tegra124-car", NULL }; 697 struct fdt_attach_args * const faa = aux; 698 699 #if 0 700 return of_match_compatible(faa->faa_phandle, compatible); 701 #else 702 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 703 return 0; 704 705 return 999; 706 #endif 707 } 708 709 static void 710 tegra124_car_attach(device_t parent, device_t self, void *aux) 711 { 712 struct tegra124_car_softc * const sc = device_private(self); 713 struct fdt_attach_args * const faa = aux; 714 const int phandle = faa->faa_phandle; 715 bus_addr_t addr; 716 bus_size_t size; 717 int error; 718 719 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 720 aprint_error(": couldn't get registers\n"); 721 return; 722 } 723 724 sc->sc_dev = self; 725 sc->sc_bst = faa->faa_bst; 726 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 727 if (error) { 728 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 729 return; 730 } 731 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 732 sc->sc_clock_cells = 1; 733 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 734 sc->sc_reset_cells = 1; 735 736 aprint_naive("\n"); 737 aprint_normal(": CAR\n"); 738 739 clk_backend_register("tegra124", &tegra124_car_clock_funcs, sc); 740 741 fdtbus_register_clock_controller(self, phandle, 742 &tegra124_car_fdtclock_funcs); 743 fdtbus_register_reset_controller(self, phandle, 744 &tegra124_car_fdtreset_funcs); 745 746 tegra124_car_init(sc); 747 748 config_interrupts(self, tegra124_car_rnd_attach); 749 } 750 751 static void 752 tegra124_car_init(struct tegra124_car_softc *sc) 753 { 754 tegra124_car_utmip_init(sc); 755 tegra124_car_xusb_init(sc); 756 } 757 758 static void 759 tegra124_car_utmip_init(struct tegra124_car_softc *sc) 760 { 761 bus_space_tag_t bst = sc->sc_bst; 762 bus_space_handle_t bsh = sc->sc_bsh; 763 764 const u_int enable_dly_count = 0x02; 765 const u_int stable_count = 0x2f; 766 const u_int active_dly_count = 0x04; 767 const u_int xtal_freq_count = 0x76; 768 769 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 770 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 771 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 772 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 773 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 774 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 775 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 776 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 777 778 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 779 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 780 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 781 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 782 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 783 784 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 785 0, 786 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 787 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 788 789 } 790 791 static void 792 tegra124_car_xusb_init(struct tegra124_car_softc *sc) 793 { 794 const bus_space_tag_t bst = sc->sc_bst; 795 const bus_space_handle_t bsh = sc->sc_bsh; 796 uint32_t val; 797 798 /* XXX do this all better */ 799 800 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 801 802 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 803 0, CAR_PLLREFE_MISC_IDDQ); 804 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 805 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 806 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 807 808 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 809 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 810 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 811 CAR_PLLREFE_BASE_ENABLE, 0); 812 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 813 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 814 815 do { 816 delay(2); 817 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 818 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 819 820 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 821 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 822 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 823 CAR_PLLE_BASE_ENABLE, 0); 824 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 825 CAR_PLLE_MISC_LOCK_ENABLE, 0); 826 827 do { 828 delay(2); 829 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 830 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 831 832 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 833 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 834 } 835 836 static void 837 tegra124_car_rnd_attach(device_t self) 838 { 839 struct tegra124_car_softc * const sc = device_private(self); 840 841 mutex_init(&sc->sc_rndlock, MUTEX_DEFAULT, IPL_VM); 842 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc); 843 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 844 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 845 tegra124_car_rnd_callback(RND_POOLBITS / NBBY, sc); 846 } 847 848 static void 849 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv) 850 { 851 struct tegra124_car_softc * const sc = priv; 852 uint16_t buf[512]; 853 uint32_t cnt; 854 855 mutex_enter(&sc->sc_rndlock); 856 while (bytes_wanted) { 857 const u_int nbytes = MIN(bytes_wanted, 1024); 858 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) { 859 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 860 CAR_PLL_LFSR_REG) & 0xffff; 861 } 862 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes, 863 nbytes * NBBY); 864 bytes_wanted -= MIN(bytes_wanted, nbytes); 865 } 866 explicit_memset(buf, 0, sizeof(buf)); 867 mutex_exit(&sc->sc_rndlock); 868 } 869 870 static struct tegra_clk * 871 tegra124_car_clock_find(const char *name) 872 { 873 u_int n; 874 875 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) { 876 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) { 877 return &tegra124_car_clocks[n]; 878 } 879 } 880 881 return NULL; 882 } 883 884 static struct tegra_clk * 885 tegra124_car_clock_find_by_id(u_int clock_id) 886 { 887 u_int n; 888 889 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) { 890 if (tegra124_car_clock_ids[n].id == clock_id) { 891 const char *name = tegra124_car_clock_ids[n].name; 892 return tegra124_car_clock_find(name); 893 } 894 } 895 896 return NULL; 897 } 898 899 static struct clk * 900 tegra124_car_clock_decode(device_t dev, const void *data, size_t len) 901 { 902 struct tegra124_car_softc * const sc = device_private(dev); 903 struct tegra_clk *tclk; 904 905 if (len != sc->sc_clock_cells * 4) { 906 return NULL; 907 } 908 909 const u_int clock_id = be32dec(data); 910 911 tclk = tegra124_car_clock_find_by_id(clock_id); 912 if (tclk) 913 return TEGRA_CLK_BASE(tclk); 914 915 return NULL; 916 } 917 918 static struct clk * 919 tegra124_car_clock_get(void *priv, const char *name) 920 { 921 struct tegra_clk *tclk; 922 923 tclk = tegra124_car_clock_find(name); 924 if (tclk == NULL) 925 return NULL; 926 927 atomic_inc_uint(&tclk->refcnt); 928 929 return TEGRA_CLK_BASE(tclk); 930 } 931 932 static void 933 tegra124_car_clock_put(void *priv, struct clk *clk) 934 { 935 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 936 937 KASSERT(tclk->refcnt > 0); 938 939 atomic_dec_uint(&tclk->refcnt); 940 } 941 942 static u_int 943 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc, 944 struct tegra_clk *tclk) 945 { 946 struct tegra_pll_clk *tpll = &tclk->u.pll; 947 struct tegra_clk *tclk_parent; 948 bus_space_tag_t bst = sc->sc_bst; 949 bus_space_handle_t bsh = sc->sc_bsh; 950 u_int divm, divn, divp; 951 uint64_t rate; 952 953 KASSERT(tclk->type == TEGRA_CLK_PLL); 954 955 tclk_parent = tegra124_car_clock_find(tclk->parent); 956 KASSERT(tclk_parent != NULL); 957 958 const u_int rate_parent = tegra124_car_clock_get_rate(sc, 959 TEGRA_CLK_BASE(tclk_parent)); 960 961 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 962 divm = __SHIFTOUT(base, tpll->divm_mask); 963 divn = __SHIFTOUT(base, tpll->divn_mask); 964 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 965 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 966 } else { 967 divp = __SHIFTOUT(base, tpll->divp_mask); 968 } 969 970 rate = (uint64_t)rate_parent * divn; 971 return rate / (divm << divp); 972 } 973 974 static int 975 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc, 976 struct tegra_clk *tclk, u_int rate) 977 { 978 struct tegra_pll_clk *tpll = &tclk->u.pll; 979 bus_space_tag_t bst = sc->sc_bst; 980 bus_space_handle_t bsh = sc->sc_bsh; 981 struct clk *clk_parent; 982 uint32_t bp, base; 983 984 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 985 if (clk_parent == NULL) 986 return EIO; 987 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); 988 if (rate_parent == 0) 989 return EIO; 990 991 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 992 const u_int divm = 1; 993 const u_int divn = rate / rate_parent; 994 const u_int divp = 0; 995 996 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 997 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 998 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 999 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1000 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1001 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1002 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1003 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1004 1005 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1006 base &= ~CAR_PLLX_BASE_DIVM; 1007 base &= ~CAR_PLLX_BASE_DIVN; 1008 base &= ~CAR_PLLX_BASE_DIVP; 1009 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1010 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1011 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1012 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1013 1014 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1015 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1016 do { 1017 delay(2); 1018 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1019 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1020 delay(100); 1021 1022 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1023 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1024 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1025 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1026 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1027 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1028 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1029 1030 return 0; 1031 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1032 const u_int divm = 1; 1033 const u_int pldiv = 1; 1034 const u_int divn = (rate << pldiv) / rate_parent; 1035 1036 /* Set frequency */ 1037 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1038 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1039 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1040 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1041 CAR_PLLD2_BASE_REF_SRC_SEL | 1042 CAR_PLLD2_BASE_DIVM | 1043 CAR_PLLD2_BASE_DIVN | 1044 CAR_PLLD2_BASE_DIVP); 1045 1046 return 0; 1047 } else { 1048 /* TODO */ 1049 return EOPNOTSUPP; 1050 } 1051 } 1052 1053 static int 1054 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc, 1055 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1056 { 1057 struct tegra_mux_clk *tmux = &tclk->u.mux; 1058 bus_space_tag_t bst = sc->sc_bst; 1059 bus_space_handle_t bsh = sc->sc_bsh; 1060 uint32_t v; 1061 u_int src; 1062 1063 KASSERT(tclk->type == TEGRA_CLK_MUX); 1064 1065 for (src = 0; src < tmux->nparents; src++) { 1066 if (tmux->parents[src] == NULL) { 1067 continue; 1068 } 1069 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1070 break; 1071 } 1072 } 1073 if (src == tmux->nparents) { 1074 return EINVAL; 1075 } 1076 1077 if (tmux->reg == CAR_CLKSRC_HDMI_REG && 1078 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) { 1079 /* Change IDDQ from 1 to 0 */ 1080 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1081 0, CAR_PLLD2_BASE_IDDQ); 1082 delay(2); 1083 1084 /* Enable lock */ 1085 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 1086 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 1087 1088 /* Enable PLLD2 */ 1089 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 1090 CAR_PLLD2_BASE_ENABLE, 0); 1091 1092 /* Wait for lock */ 1093 do { 1094 delay(2); 1095 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 1096 } while ((v & CAR_PLLD2_BASE_LOCK) == 0); 1097 1098 delay(200); 1099 } 1100 1101 v = bus_space_read_4(bst, bsh, tmux->reg); 1102 v &= ~tmux->bits; 1103 v |= __SHIFTIN(src, tmux->bits); 1104 bus_space_write_4(bst, bsh, tmux->reg, v); 1105 1106 return 0; 1107 } 1108 1109 static struct tegra_clk * 1110 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc, 1111 struct tegra_clk *tclk) 1112 { 1113 struct tegra_mux_clk *tmux = &tclk->u.mux; 1114 bus_space_tag_t bst = sc->sc_bst; 1115 bus_space_handle_t bsh = sc->sc_bsh; 1116 1117 KASSERT(tclk->type == TEGRA_CLK_MUX); 1118 1119 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1120 const u_int src = __SHIFTOUT(v, tmux->bits); 1121 1122 KASSERT(src < tmux->nparents); 1123 1124 if (tmux->parents[src] == NULL) { 1125 return NULL; 1126 } 1127 1128 return tegra124_car_clock_find(tmux->parents[src]); 1129 } 1130 1131 static u_int 1132 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc, 1133 struct tegra_clk *tclk) 1134 { 1135 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1136 struct clk *clk_parent; 1137 1138 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1139 if (clk_parent == NULL) 1140 return 0; 1141 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1142 1143 return parent_rate / tfixed_div->div; 1144 } 1145 1146 static u_int 1147 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc, 1148 struct tegra_clk *tclk) 1149 { 1150 struct tegra_div_clk *tdiv = &tclk->u.div; 1151 bus_space_tag_t bst = sc->sc_bst; 1152 bus_space_handle_t bsh = sc->sc_bsh; 1153 struct clk *clk_parent; 1154 u_int rate; 1155 1156 KASSERT(tclk->type == TEGRA_CLK_DIV); 1157 1158 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1159 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1160 1161 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1162 const u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1163 1164 switch (tdiv->reg) { 1165 case CAR_CLKSRC_I2C1_REG: 1166 case CAR_CLKSRC_I2C2_REG: 1167 case CAR_CLKSRC_I2C3_REG: 1168 case CAR_CLKSRC_I2C4_REG: 1169 case CAR_CLKSRC_I2C5_REG: 1170 case CAR_CLKSRC_I2C6_REG: 1171 rate = parent_rate * 1 / (raw_div + 1); 1172 break; 1173 case CAR_CLKSRC_UARTA_REG: 1174 case CAR_CLKSRC_UARTB_REG: 1175 case CAR_CLKSRC_UARTC_REG: 1176 case CAR_CLKSRC_UARTD_REG: 1177 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1178 rate = parent_rate * 2 / (raw_div + 2); 1179 } else { 1180 rate = parent_rate; 1181 } 1182 break; 1183 default: 1184 rate = parent_rate * 2 / (raw_div + 2); 1185 break; 1186 } 1187 1188 return rate; 1189 } 1190 1191 static int 1192 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc, 1193 struct tegra_clk *tclk, u_int rate) 1194 { 1195 struct tegra_div_clk *tdiv = &tclk->u.div; 1196 bus_space_tag_t bst = sc->sc_bst; 1197 bus_space_handle_t bsh = sc->sc_bsh; 1198 struct clk *clk_parent; 1199 u_int raw_div; 1200 uint32_t v; 1201 1202 KASSERT(tclk->type == TEGRA_CLK_DIV); 1203 1204 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1205 if (clk_parent == NULL) 1206 return EINVAL; 1207 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); 1208 1209 v = bus_space_read_4(bst, bsh, tdiv->reg); 1210 1211 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1212 1213 switch (tdiv->reg) { 1214 case CAR_CLKSRC_UARTA_REG: 1215 case CAR_CLKSRC_UARTB_REG: 1216 case CAR_CLKSRC_UARTC_REG: 1217 case CAR_CLKSRC_UARTD_REG: 1218 if (rate == parent_rate) { 1219 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1220 } else { 1221 v |= CAR_CLKSRC_UART_DIV_ENB; 1222 raw_div = (parent_rate * 2) / rate - 2; 1223 } 1224 break; 1225 case CAR_CLKSRC_SATA_REG: 1226 if (rate) { 1227 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1228 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 1229 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB; 1230 raw_div = (parent_rate * 2) / rate - 2; 1231 } else { 1232 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB; 1233 } 1234 break; 1235 case CAR_CLKSRC_I2C1_REG: 1236 case CAR_CLKSRC_I2C2_REG: 1237 case CAR_CLKSRC_I2C3_REG: 1238 case CAR_CLKSRC_I2C4_REG: 1239 case CAR_CLKSRC_I2C5_REG: 1240 case CAR_CLKSRC_I2C6_REG: 1241 if (rate) 1242 raw_div = parent_rate / rate - 1; 1243 break; 1244 default: 1245 if (rate) 1246 raw_div = (parent_rate * 2) / rate - 2; 1247 break; 1248 } 1249 1250 v &= ~tdiv->bits; 1251 v |= __SHIFTIN(raw_div, tdiv->bits); 1252 1253 bus_space_write_4(bst, bsh, tdiv->reg, v); 1254 1255 return 0; 1256 } 1257 1258 static int 1259 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc, 1260 struct tegra_clk *tclk, bool enable) 1261 { 1262 struct tegra_gate_clk *tgate = &tclk->u.gate; 1263 bus_space_tag_t bst = sc->sc_bst; 1264 bus_space_handle_t bsh = sc->sc_bsh; 1265 bus_size_t reg; 1266 1267 KASSERT(tclk->type == TEGRA_CLK_GATE); 1268 1269 if (tgate->set_reg == tgate->clr_reg) { 1270 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1271 if (enable) { 1272 v |= tgate->bits; 1273 } else { 1274 v &= ~tgate->bits; 1275 } 1276 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1277 } else { 1278 if (enable) { 1279 reg = tgate->set_reg; 1280 } else { 1281 reg = tgate->clr_reg; 1282 } 1283 1284 if (reg == CAR_CLK_ENB_V_SET_REG && 1285 tgate->bits == CAR_DEV_V_SATA) { 1286 /* De-assert reset to SATA PADPLL */ 1287 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 1288 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 1289 delay(15); 1290 } 1291 bus_space_write_4(bst, bsh, reg, tgate->bits); 1292 } 1293 1294 return 0; 1295 } 1296 1297 static u_int 1298 tegra124_car_clock_get_rate(void *priv, struct clk *clk) 1299 { 1300 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1301 struct clk *clk_parent; 1302 1303 switch (tclk->type) { 1304 case TEGRA_CLK_FIXED: 1305 return tclk->u.fixed.rate; 1306 case TEGRA_CLK_PLL: 1307 return tegra124_car_clock_get_rate_pll(priv, tclk); 1308 case TEGRA_CLK_MUX: 1309 case TEGRA_CLK_GATE: 1310 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1311 if (clk_parent == NULL) 1312 return EINVAL; 1313 return tegra124_car_clock_get_rate(priv, clk_parent); 1314 case TEGRA_CLK_FIXED_DIV: 1315 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); 1316 case TEGRA_CLK_DIV: 1317 return tegra124_car_clock_get_rate_div(priv, tclk); 1318 default: 1319 panic("tegra124: unknown tclk type %d", tclk->type); 1320 } 1321 } 1322 1323 static int 1324 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1325 { 1326 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1327 struct clk *clk_parent; 1328 1329 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1330 1331 switch (tclk->type) { 1332 case TEGRA_CLK_FIXED: 1333 case TEGRA_CLK_MUX: 1334 return EIO; 1335 case TEGRA_CLK_FIXED_DIV: 1336 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1337 if (clk_parent == NULL) 1338 return EIO; 1339 return tegra124_car_clock_set_rate(priv, clk_parent, 1340 rate * tclk->u.fixed_div.div); 1341 case TEGRA_CLK_GATE: 1342 return EINVAL; 1343 case TEGRA_CLK_PLL: 1344 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); 1345 case TEGRA_CLK_DIV: 1346 return tegra124_car_clock_set_rate_div(priv, tclk, rate); 1347 default: 1348 panic("tegra124: unknown tclk type %d", tclk->type); 1349 } 1350 } 1351 1352 static int 1353 tegra124_car_clock_enable(void *priv, struct clk *clk) 1354 { 1355 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1356 struct clk *clk_parent; 1357 1358 if (tclk->type != TEGRA_CLK_GATE) { 1359 clk_parent = tegra124_car_clock_get_parent(priv, clk); 1360 if (clk_parent == NULL) 1361 return 0; 1362 return tegra124_car_clock_enable(priv, clk_parent); 1363 } 1364 1365 return tegra124_car_clock_enable_gate(priv, tclk, true); 1366 } 1367 1368 static int 1369 tegra124_car_clock_disable(void *priv, struct clk *clk) 1370 { 1371 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1372 1373 if (tclk->type != TEGRA_CLK_GATE) 1374 return EINVAL; 1375 1376 return tegra124_car_clock_enable_gate(priv, tclk, false); 1377 } 1378 1379 static int 1380 tegra124_car_clock_set_parent(void *priv, struct clk *clk, 1381 struct clk *clk_parent) 1382 { 1383 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1384 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1385 struct clk *nclk_parent; 1386 1387 if (tclk->type != TEGRA_CLK_MUX) { 1388 nclk_parent = tegra124_car_clock_get_parent(priv, clk); 1389 if (nclk_parent == clk_parent || nclk_parent == NULL) 1390 return EINVAL; 1391 return tegra124_car_clock_set_parent(priv, nclk_parent, 1392 clk_parent); 1393 } 1394 1395 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1396 } 1397 1398 static struct clk * 1399 tegra124_car_clock_get_parent(void *priv, struct clk *clk) 1400 { 1401 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1402 struct tegra_clk *tclk_parent = NULL; 1403 1404 switch (tclk->type) { 1405 case TEGRA_CLK_FIXED: 1406 case TEGRA_CLK_PLL: 1407 case TEGRA_CLK_FIXED_DIV: 1408 case TEGRA_CLK_DIV: 1409 case TEGRA_CLK_GATE: 1410 if (tclk->parent) { 1411 tclk_parent = tegra124_car_clock_find(tclk->parent); 1412 } 1413 break; 1414 case TEGRA_CLK_MUX: 1415 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); 1416 break; 1417 } 1418 1419 if (tclk_parent == NULL) 1420 return NULL; 1421 1422 return TEGRA_CLK_BASE(tclk_parent); 1423 } 1424 1425 static void * 1426 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len) 1427 { 1428 struct tegra124_car_softc * const sc = device_private(dev); 1429 struct tegra124_car_rst *rst; 1430 1431 if (len != sc->sc_reset_cells * 4) 1432 return NULL; 1433 1434 const u_int reset_id = be32dec(data); 1435 1436 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32) 1437 return NULL; 1438 1439 const u_int reg = reset_id / 32; 1440 1441 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1442 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; 1443 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1444 rst->mask = __BIT(reset_id % 32); 1445 1446 return rst; 1447 } 1448 1449 static void 1450 tegra124_car_reset_release(device_t dev, void *priv) 1451 { 1452 struct tegra124_car_rst *rst = priv; 1453 1454 kmem_free(rst, sizeof(*rst)); 1455 } 1456 1457 static int 1458 tegra124_car_reset_assert(device_t dev, void *priv) 1459 { 1460 struct tegra124_car_softc * const sc = device_private(dev); 1461 struct tegra124_car_rst *rst = priv; 1462 1463 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1464 1465 return 0; 1466 } 1467 1468 static int 1469 tegra124_car_reset_deassert(device_t dev, void *priv) 1470 { 1471 struct tegra124_car_softc * const sc = device_private(dev); 1472 struct tegra124_car_rst *rst = priv; 1473 1474 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1475 1476 return 0; 1477 } 1478
Indexes created Tue Sep 30 20:09:53 GMT 2025