tegra210_car.c revision 1.1
1 /* $NetBSD: tegra210_car.c,v 1.1 2017/07/21 01:01:22 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.1 2017/07/21 01:01:22 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static struct tegra_clk tegra210_car_clocks[] = { 428 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 429 430 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 431 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 432 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 433 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 434 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 435 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 436 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 437 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 438 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 439 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 440 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 441 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 442 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 443 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 444 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 445 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 446 447 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 448 mux_uart_p), 449 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 450 mux_uart_p), 451 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 452 mux_uart_p), 453 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 454 mux_uart_p), 455 456 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 457 mux_sdmmc1_p), 458 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 459 mux_sdmmc2_4_p), 460 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 461 mux_sdmmc3_p), 462 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 463 mux_sdmmc2_4_p), 464 465 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 466 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 467 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 468 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 469 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 470 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 471 472 CLK_DIV("DIV_UARTA", "MUX_UARTA", 473 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 474 CLK_DIV("DIV_UARTB", "MUX_UARTB", 475 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 476 CLK_DIV("DIV_UARTC", "MUX_UARTC", 477 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 478 CLK_DIV("DIV_UARTD", "MUX_UARTD", 479 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 480 481 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 482 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 483 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 484 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 485 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 486 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 487 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 488 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 489 490 CLK_DIV("DIV_I2C1", "MUX_I2C1", 491 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 492 CLK_DIV("DIV_I2C2", "MUX_I2C2", 493 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 494 CLK_DIV("DIV_I2C3", "MUX_I2C3", 495 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 496 CLK_DIV("DIV_I2C4", "MUX_I2C4", 497 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 498 CLK_DIV("DIV_I2C5", "MUX_I2C5", 499 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 500 CLK_DIV("DIV_I2C6", "MUX_I2C6", 501 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 502 503 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 504 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 505 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 506 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 507 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 508 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 509 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 510 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 511 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 512 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 513 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 514 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 515 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 516 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 517 }; 518 519 struct tegra210_init_parent { 520 const char *clock; 521 const char *parent; 522 } tegra210_init_parents[] = { 523 { "SDMMC1", "PLL_P" }, 524 { "SDMMC2", "PLL_P" }, 525 { "SDMMC3", "PLL_P" }, 526 { "SDMMC4", "PLL_P" }, 527 }; 528 529 struct tegra210_car_rst { 530 u_int set_reg; 531 u_int clr_reg; 532 u_int mask; 533 }; 534 535 static struct tegra210_car_reset_reg { 536 u_int set_reg; 537 u_int clr_reg; 538 } tegra210_car_reset_regs[] = { 539 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 540 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 541 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 542 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 543 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 544 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 545 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 546 }; 547 548 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 549 static void tegra210_car_reset_release(device_t, void *); 550 static int tegra210_car_reset_assert(device_t, void *); 551 static int tegra210_car_reset_deassert(device_t, void *); 552 553 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 554 .acquire = tegra210_car_reset_acquire, 555 .release = tegra210_car_reset_release, 556 .reset_assert = tegra210_car_reset_assert, 557 .reset_deassert = tegra210_car_reset_deassert, 558 }; 559 560 struct tegra210_car_softc { 561 device_t sc_dev; 562 bus_space_tag_t sc_bst; 563 bus_space_handle_t sc_bsh; 564 565 struct clk_domain sc_clkdom; 566 567 u_int sc_clock_cells; 568 u_int sc_reset_cells; 569 570 kmutex_t sc_rndlock; 571 krndsource_t sc_rndsource; 572 }; 573 574 static void tegra210_car_init(struct tegra210_car_softc *); 575 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 576 static void tegra210_car_parent_init(struct tegra210_car_softc *); 577 578 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 579 tegra210_car_match, tegra210_car_attach, NULL, NULL); 580 581 static int 582 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 583 { 584 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 585 struct fdt_attach_args * const faa = aux; 586 587 #if 0 588 return of_match_compatible(faa->faa_phandle, compatible); 589 #else 590 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 591 return 0; 592 593 return 999; 594 #endif 595 } 596 597 static void 598 tegra210_car_attach(device_t parent, device_t self, void *aux) 599 { 600 struct tegra210_car_softc * const sc = device_private(self); 601 struct fdt_attach_args * const faa = aux; 602 const int phandle = faa->faa_phandle; 603 bus_addr_t addr; 604 bus_size_t size; 605 int error, n; 606 607 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 608 aprint_error(": couldn't get registers\n"); 609 return; 610 } 611 612 sc->sc_dev = self; 613 sc->sc_bst = faa->faa_bst; 614 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 615 if (error) { 616 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 617 return; 618 } 619 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 620 sc->sc_clock_cells = 1; 621 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 622 sc->sc_reset_cells = 1; 623 624 aprint_naive("\n"); 625 aprint_normal(": CAR\n"); 626 627 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 628 sc->sc_clkdom.priv = sc; 629 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 630 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 631 632 fdtbus_register_clock_controller(self, phandle, 633 &tegra210_car_fdtclock_funcs); 634 fdtbus_register_reset_controller(self, phandle, 635 &tegra210_car_fdtreset_funcs); 636 637 tegra210_car_init(sc); 638 639 #ifdef TEGRA210_CAR_DEBUG 640 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 641 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 642 struct clk *clk_parent = clk_get_parent(clk); 643 device_printf(self, "clk %s (parent %s): ", clk->name, 644 clk_parent ? clk_parent->name : "none"); 645 printf("%u Hz\n", clk_get_rate(clk)); 646 } 647 #endif 648 } 649 650 static void 651 tegra210_car_init(struct tegra210_car_softc *sc) 652 { 653 tegra210_car_parent_init(sc); 654 #if notyet 655 tegra210_car_utmip_init(sc); 656 tegra210_car_xusb_init(sc); 657 #endif 658 tegra210_car_watchdog_init(sc); 659 } 660 661 static void 662 tegra210_car_parent_init(struct tegra210_car_softc *sc) 663 { 664 struct clk *clk, *clk_parent; 665 int error; 666 u_int n; 667 668 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 669 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 670 KASSERT(clk != NULL); 671 clk_parent = clk_get(&sc->sc_clkdom, 672 tegra210_init_parents[n].parent); 673 KASSERT(clk_parent != NULL); 674 675 error = clk_set_parent(clk, clk_parent); 676 if (error) { 677 aprint_error_dev(sc->sc_dev, 678 "couldn't set '%s' parent to '%s': %d\n", 679 clk->name, clk_parent->name, error); 680 } 681 clk_put(clk_parent); 682 clk_put(clk); 683 } 684 } 685 686 #if notyet 687 static void 688 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 689 { 690 bus_space_tag_t bst = sc->sc_bst; 691 bus_space_handle_t bsh = sc->sc_bsh; 692 693 const u_int enable_dly_count = 0x02; 694 const u_int stable_count = 0x2f; 695 const u_int active_dly_count = 0x04; 696 const u_int xtal_freq_count = 0x76; 697 698 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 699 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 700 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 701 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 702 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 703 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 704 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 705 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 706 707 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 708 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 709 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 710 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 711 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 712 713 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 714 0, 715 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 716 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 717 718 } 719 720 static void 721 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 722 { 723 const bus_space_tag_t bst = sc->sc_bst; 724 const bus_space_handle_t bsh = sc->sc_bsh; 725 uint32_t val; 726 727 /* XXX do this all better */ 728 729 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 730 731 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 732 0, CAR_PLLREFE_MISC_IDDQ); 733 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 734 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 735 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 736 737 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 738 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 739 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 740 CAR_PLLREFE_BASE_ENABLE, 0); 741 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 742 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 743 744 do { 745 delay(2); 746 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 747 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 748 749 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 750 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 751 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 752 CAR_PLLE_BASE_ENABLE, 0); 753 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 754 CAR_PLLE_MISC_LOCK_ENABLE, 0); 755 756 do { 757 delay(2); 758 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 759 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 760 761 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 762 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 763 } 764 #endif 765 766 static void 767 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 768 { 769 const bus_space_tag_t bst = sc->sc_bst; 770 const bus_space_handle_t bsh = sc->sc_bsh; 771 772 /* Enable watchdog timer reset for system */ 773 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 774 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 775 } 776 777 static struct tegra_clk * 778 tegra210_car_clock_find(const char *name) 779 { 780 u_int n; 781 782 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 783 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 784 return &tegra210_car_clocks[n]; 785 } 786 } 787 788 return NULL; 789 } 790 791 static struct tegra_clk * 792 tegra210_car_clock_find_by_id(u_int clock_id) 793 { 794 u_int n; 795 796 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 797 if (tegra210_car_clock_ids[n].id == clock_id) { 798 const char *name = tegra210_car_clock_ids[n].name; 799 return tegra210_car_clock_find(name); 800 } 801 } 802 803 return NULL; 804 } 805 806 static struct clk * 807 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 808 { 809 struct tegra210_car_softc * const sc = device_private(dev); 810 struct tegra_clk *tclk; 811 812 if (len != sc->sc_clock_cells * 4) { 813 return NULL; 814 } 815 816 const u_int clock_id = be32dec(data); 817 818 tclk = tegra210_car_clock_find_by_id(clock_id); 819 if (tclk) 820 return TEGRA_CLK_BASE(tclk); 821 822 return NULL; 823 } 824 825 static struct clk * 826 tegra210_car_clock_get(void *priv, const char *name) 827 { 828 struct tegra_clk *tclk; 829 830 tclk = tegra210_car_clock_find(name); 831 if (tclk == NULL) 832 return NULL; 833 834 atomic_inc_uint(&tclk->refcnt); 835 836 return TEGRA_CLK_BASE(tclk); 837 } 838 839 static void 840 tegra210_car_clock_put(void *priv, struct clk *clk) 841 { 842 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 843 844 KASSERT(tclk->refcnt > 0); 845 846 atomic_dec_uint(&tclk->refcnt); 847 } 848 849 static u_int 850 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 851 struct tegra_clk *tclk) 852 { 853 struct tegra_pll_clk *tpll = &tclk->u.pll; 854 struct tegra_clk *tclk_parent; 855 bus_space_tag_t bst = sc->sc_bst; 856 bus_space_handle_t bsh = sc->sc_bsh; 857 u_int divm, divn, divp; 858 uint64_t rate; 859 860 KASSERT(tclk->type == TEGRA_CLK_PLL); 861 862 tclk_parent = tegra210_car_clock_find(tclk->parent); 863 KASSERT(tclk_parent != NULL); 864 865 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 866 TEGRA_CLK_BASE(tclk_parent)); 867 868 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 869 divm = __SHIFTOUT(base, tpll->divm_mask); 870 divn = __SHIFTOUT(base, tpll->divn_mask); 871 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 872 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 873 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 874 /* XXX divp is not applied to PLLP's primary output */ 875 divp = 0; 876 } else { 877 divp = __SHIFTOUT(base, tpll->divp_mask); 878 } 879 880 rate = (uint64_t)rate_parent * divn; 881 return rate / (divm << divp); 882 } 883 884 static int 885 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 886 struct tegra_clk *tclk, u_int rate) 887 { 888 struct tegra_pll_clk *tpll = &tclk->u.pll; 889 bus_space_tag_t bst = sc->sc_bst; 890 bus_space_handle_t bsh = sc->sc_bsh; 891 struct clk *clk_parent; 892 uint32_t bp, base; 893 894 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 895 if (clk_parent == NULL) 896 return EIO; 897 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 898 if (rate_parent == 0) 899 return EIO; 900 901 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 902 const u_int divm = 1; 903 const u_int divn = rate / rate_parent; 904 const u_int divp = 0; 905 906 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 907 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 908 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 909 CAR_CCLKG_BURST_POLICY_CPU_STATE); 910 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 911 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 912 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 913 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 914 915 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 916 base &= ~CAR_PLLX_BASE_DIVM; 917 base &= ~CAR_PLLX_BASE_DIVN; 918 base &= ~CAR_PLLX_BASE_DIVP; 919 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 920 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 921 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 922 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 923 924 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 925 CAR_PLLX_MISC_LOCK_ENABLE, 0); 926 do { 927 delay(2); 928 base = bus_space_read_4(bst, bsh, tpll->base_reg); 929 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 930 delay(100); 931 932 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 933 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 934 CAR_CCLKG_BURST_POLICY_CPU_STATE); 935 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 936 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 937 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 938 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 939 940 return 0; 941 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 942 const u_int divm = 1; 943 const u_int pldiv = 1; 944 const u_int divn = (rate << pldiv) / rate_parent; 945 946 /* Set frequency */ 947 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 948 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 949 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 950 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 951 CAR_PLLD2_BASE_REF_SRC_SEL | 952 CAR_PLLD2_BASE_DIVM | 953 CAR_PLLD2_BASE_DIVN | 954 CAR_PLLD2_BASE_DIVP); 955 956 return 0; 957 } else { 958 /* TODO */ 959 return EOPNOTSUPP; 960 } 961 } 962 963 static int 964 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 965 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 966 { 967 struct tegra_mux_clk *tmux = &tclk->u.mux; 968 bus_space_tag_t bst = sc->sc_bst; 969 bus_space_handle_t bsh = sc->sc_bsh; 970 uint32_t v; 971 u_int src; 972 973 KASSERT(tclk->type == TEGRA_CLK_MUX); 974 975 for (src = 0; src < tmux->nparents; src++) { 976 if (tmux->parents[src] == NULL) { 977 continue; 978 } 979 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 980 break; 981 } 982 } 983 if (src == tmux->nparents) { 984 return EINVAL; 985 } 986 987 v = bus_space_read_4(bst, bsh, tmux->reg); 988 v &= ~tmux->bits; 989 v |= __SHIFTIN(src, tmux->bits); 990 bus_space_write_4(bst, bsh, tmux->reg, v); 991 992 return 0; 993 } 994 995 static struct tegra_clk * 996 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 997 struct tegra_clk *tclk) 998 { 999 struct tegra_mux_clk *tmux = &tclk->u.mux; 1000 bus_space_tag_t bst = sc->sc_bst; 1001 bus_space_handle_t bsh = sc->sc_bsh; 1002 1003 KASSERT(tclk->type == TEGRA_CLK_MUX); 1004 1005 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1006 const u_int src = __SHIFTOUT(v, tmux->bits); 1007 1008 KASSERT(src < tmux->nparents); 1009 1010 if (tmux->parents[src] == NULL) { 1011 return NULL; 1012 } 1013 1014 return tegra210_car_clock_find(tmux->parents[src]); 1015 } 1016 1017 static u_int 1018 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1019 struct tegra_clk *tclk) 1020 { 1021 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1022 struct clk *clk_parent; 1023 1024 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1025 if (clk_parent == NULL) 1026 return 0; 1027 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1028 1029 return parent_rate / tfixed_div->div; 1030 } 1031 1032 static u_int 1033 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1034 struct tegra_clk *tclk) 1035 { 1036 struct tegra_div_clk *tdiv = &tclk->u.div; 1037 bus_space_tag_t bst = sc->sc_bst; 1038 bus_space_handle_t bsh = sc->sc_bsh; 1039 struct clk *clk_parent; 1040 u_int rate; 1041 1042 KASSERT(tclk->type == TEGRA_CLK_DIV); 1043 1044 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1045 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1046 1047 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1048 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1049 1050 switch (tdiv->reg) { 1051 case CAR_CLKSRC_I2C1_REG: 1052 case CAR_CLKSRC_I2C2_REG: 1053 case CAR_CLKSRC_I2C3_REG: 1054 case CAR_CLKSRC_I2C4_REG: 1055 case CAR_CLKSRC_I2C5_REG: 1056 case CAR_CLKSRC_I2C6_REG: 1057 rate = parent_rate / (raw_div + 1); 1058 break; 1059 case CAR_CLKSRC_UARTA_REG: 1060 case CAR_CLKSRC_UARTB_REG: 1061 case CAR_CLKSRC_UARTC_REG: 1062 case CAR_CLKSRC_UARTD_REG: 1063 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1064 rate = parent_rate / ((raw_div / 2) + 1); 1065 } else { 1066 rate = parent_rate; 1067 } 1068 break; 1069 case CAR_CLKSRC_SDMMC2_REG: 1070 case CAR_CLKSRC_SDMMC4_REG: 1071 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1072 case 1: 1073 case 2: 1074 case 5: 1075 raw_div = 0; /* ignore divisor for _LJ options */ 1076 break; 1077 } 1078 /* FALLTHROUGH */ 1079 default: 1080 rate = parent_rate / ((raw_div / 2) + 1); 1081 break; 1082 } 1083 1084 return rate; 1085 } 1086 1087 static int 1088 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1089 struct tegra_clk *tclk, u_int rate) 1090 { 1091 struct tegra_div_clk *tdiv = &tclk->u.div; 1092 bus_space_tag_t bst = sc->sc_bst; 1093 bus_space_handle_t bsh = sc->sc_bsh; 1094 struct clk *clk_parent; 1095 u_int raw_div; 1096 uint32_t v; 1097 1098 KASSERT(tclk->type == TEGRA_CLK_DIV); 1099 1100 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1101 if (clk_parent == NULL) 1102 return EINVAL; 1103 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1104 1105 v = bus_space_read_4(bst, bsh, tdiv->reg); 1106 1107 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1108 1109 switch (tdiv->reg) { 1110 case CAR_CLKSRC_UARTA_REG: 1111 case CAR_CLKSRC_UARTB_REG: 1112 case CAR_CLKSRC_UARTC_REG: 1113 case CAR_CLKSRC_UARTD_REG: 1114 if (rate == parent_rate) { 1115 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1116 } else if (rate) { 1117 v |= CAR_CLKSRC_UART_DIV_ENB; 1118 raw_div = (parent_rate / rate) * 2 - 1; 1119 } 1120 break; 1121 case CAR_CLKSRC_I2C1_REG: 1122 case CAR_CLKSRC_I2C2_REG: 1123 case CAR_CLKSRC_I2C3_REG: 1124 case CAR_CLKSRC_I2C4_REG: 1125 case CAR_CLKSRC_I2C5_REG: 1126 case CAR_CLKSRC_I2C6_REG: 1127 if (rate) 1128 raw_div = (parent_rate / rate) - 1; 1129 break; 1130 case CAR_CLKSRC_SDMMC1_REG: 1131 case CAR_CLKSRC_SDMMC2_REG: 1132 case CAR_CLKSRC_SDMMC3_REG: 1133 case CAR_CLKSRC_SDMMC4_REG: 1134 if (rate) { 1135 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1136 u_int calc_rate = 1137 parent_rate / ((raw_div / 2) + 1); 1138 if (calc_rate <= rate) 1139 break; 1140 } 1141 if (raw_div == 0x100) 1142 return EINVAL; 1143 } 1144 break; 1145 default: 1146 if (rate) 1147 raw_div = (parent_rate / rate) * 2 - 1; 1148 break; 1149 } 1150 1151 v &= ~tdiv->bits; 1152 v |= __SHIFTIN(raw_div, tdiv->bits); 1153 1154 bus_space_write_4(bst, bsh, tdiv->reg, v); 1155 1156 return 0; 1157 } 1158 1159 static int 1160 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1161 struct tegra_clk *tclk, bool enable) 1162 { 1163 struct tegra_gate_clk *tgate = &tclk->u.gate; 1164 bus_space_tag_t bst = sc->sc_bst; 1165 bus_space_handle_t bsh = sc->sc_bsh; 1166 bus_size_t reg; 1167 1168 KASSERT(tclk->type == TEGRA_CLK_GATE); 1169 1170 if (tgate->set_reg == tgate->clr_reg) { 1171 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1172 if (enable) { 1173 v |= tgate->bits; 1174 } else { 1175 v &= ~tgate->bits; 1176 } 1177 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1178 } else { 1179 if (enable) { 1180 reg = tgate->set_reg; 1181 } else { 1182 reg = tgate->clr_reg; 1183 } 1184 bus_space_write_4(bst, bsh, reg, tgate->bits); 1185 } 1186 1187 return 0; 1188 } 1189 1190 static u_int 1191 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1192 { 1193 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1194 struct clk *clk_parent; 1195 1196 switch (tclk->type) { 1197 case TEGRA_CLK_FIXED: 1198 return tclk->u.fixed.rate; 1199 case TEGRA_CLK_PLL: 1200 return tegra210_car_clock_get_rate_pll(priv, tclk); 1201 case TEGRA_CLK_MUX: 1202 case TEGRA_CLK_GATE: 1203 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1204 if (clk_parent == NULL) 1205 return EINVAL; 1206 return tegra210_car_clock_get_rate(priv, clk_parent); 1207 case TEGRA_CLK_FIXED_DIV: 1208 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1209 case TEGRA_CLK_DIV: 1210 return tegra210_car_clock_get_rate_div(priv, tclk); 1211 default: 1212 panic("tegra210: unknown tclk type %d", tclk->type); 1213 } 1214 } 1215 1216 static int 1217 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1218 { 1219 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1220 struct clk *clk_parent; 1221 1222 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1223 1224 switch (tclk->type) { 1225 case TEGRA_CLK_FIXED: 1226 case TEGRA_CLK_MUX: 1227 return EIO; 1228 case TEGRA_CLK_FIXED_DIV: 1229 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1230 if (clk_parent == NULL) 1231 return EIO; 1232 return tegra210_car_clock_set_rate(priv, clk_parent, 1233 rate * tclk->u.fixed_div.div); 1234 case TEGRA_CLK_GATE: 1235 return EINVAL; 1236 case TEGRA_CLK_PLL: 1237 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1238 case TEGRA_CLK_DIV: 1239 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1240 default: 1241 panic("tegra210: unknown tclk type %d", tclk->type); 1242 } 1243 } 1244 1245 static int 1246 tegra210_car_clock_enable(void *priv, struct clk *clk) 1247 { 1248 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1249 struct clk *clk_parent; 1250 1251 if (tclk->type != TEGRA_CLK_GATE) { 1252 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1253 if (clk_parent == NULL) 1254 return 0; 1255 return tegra210_car_clock_enable(priv, clk_parent); 1256 } 1257 1258 return tegra210_car_clock_enable_gate(priv, tclk, true); 1259 } 1260 1261 static int 1262 tegra210_car_clock_disable(void *priv, struct clk *clk) 1263 { 1264 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1265 1266 if (tclk->type != TEGRA_CLK_GATE) 1267 return EINVAL; 1268 1269 return tegra210_car_clock_enable_gate(priv, tclk, false); 1270 } 1271 1272 static int 1273 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1274 struct clk *clk_parent) 1275 { 1276 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1277 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1278 struct clk *nclk_parent; 1279 1280 if (tclk->type != TEGRA_CLK_MUX) { 1281 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1282 if (nclk_parent == clk_parent || nclk_parent == NULL) 1283 return EINVAL; 1284 return tegra210_car_clock_set_parent(priv, nclk_parent, 1285 clk_parent); 1286 } 1287 1288 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1289 } 1290 1291 static struct clk * 1292 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1293 { 1294 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1295 struct tegra_clk *tclk_parent = NULL; 1296 1297 switch (tclk->type) { 1298 case TEGRA_CLK_FIXED: 1299 case TEGRA_CLK_PLL: 1300 case TEGRA_CLK_FIXED_DIV: 1301 case TEGRA_CLK_DIV: 1302 case TEGRA_CLK_GATE: 1303 if (tclk->parent) { 1304 tclk_parent = tegra210_car_clock_find(tclk->parent); 1305 } 1306 break; 1307 case TEGRA_CLK_MUX: 1308 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1309 break; 1310 } 1311 1312 if (tclk_parent == NULL) 1313 return NULL; 1314 1315 return TEGRA_CLK_BASE(tclk_parent); 1316 } 1317 1318 static void * 1319 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1320 { 1321 struct tegra210_car_softc * const sc = device_private(dev); 1322 struct tegra210_car_rst *rst; 1323 1324 if (len != sc->sc_reset_cells * 4) 1325 return NULL; 1326 1327 const u_int reset_id = be32dec(data); 1328 1329 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1330 return NULL; 1331 1332 const u_int reg = reset_id / 32; 1333 1334 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1335 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1336 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1337 rst->mask = __BIT(reset_id % 32); 1338 1339 return rst; 1340 } 1341 1342 static void 1343 tegra210_car_reset_release(device_t dev, void *priv) 1344 { 1345 struct tegra210_car_rst *rst = priv; 1346 1347 kmem_free(rst, sizeof(*rst)); 1348 } 1349 1350 static int 1351 tegra210_car_reset_assert(device_t dev, void *priv) 1352 { 1353 struct tegra210_car_softc * const sc = device_private(dev); 1354 struct tegra210_car_rst *rst = priv; 1355 1356 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1357 1358 return 0; 1359 } 1360 1361 static int 1362 tegra210_car_reset_deassert(device_t dev, void *priv) 1363 { 1364 struct tegra210_car_softc * const sc = device_private(dev); 1365 struct tegra210_car_rst *rst = priv; 1366 1367 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1368 1369 return 0; 1370 } 1371
Indexes created Tue Sep 30 17:09:57 GMT 2025