tegra210_car.c revision 1.11
1 /* $NetBSD: tegra210_car.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $ */ 2 #define TEGRA210_CAR_DEBUG 3 4 /*- 5 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/rndpool.h> 40 #include <sys/rndsource.h> 41 #include <sys/atomic.h> 42 #include <sys/kmem.h> 43 44 #include <dev/clk/clk_backend.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra210_carreg.h> 48 #include <arm/nvidia/tegra_clock.h> 49 #include <arm/nvidia/tegra_pmcreg.h> 50 #include <arm/nvidia/tegra_var.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 static int tegra210_car_match(device_t, cfdata_t, void *); 55 static void tegra210_car_attach(device_t, device_t, void *); 56 57 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 58 59 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 60 .decode = tegra210_car_clock_decode 61 }; 62 63 /* DT clock ID to clock name mappings */ 64 static struct tegra210_car_clock_id { 65 const char *name; 66 u_int id; 67 } tegra210_car_clock_ids[] = { 68 { "ISPB", 3 }, 69 { "RTC", 4 }, 70 { "TIMER", 5 }, 71 { "UARTA", 6 }, 72 { "GPIO", 8 }, 73 { "SDMMC2", 9 }, 74 { "I2S1", 11 }, 75 { "I2C1", 12 }, 76 { "SDMMC1", 14 }, 77 { "SDMMC4", 15 }, 78 { "PWM", 17 }, 79 { "I2S2", 18 }, 80 { "USBD", 22 }, 81 { "ISP", 23 }, 82 { "DISP2", 26 }, 83 { "DISP1", 27 }, 84 { "HOST1X", 28 }, 85 { "I2S0", 30 }, 86 { "MC", 32 }, 87 { "AHBDMA", 33 }, 88 { "APBDMA", 34 }, 89 { "PMC", 38 }, 90 { "KFUSE", 40 }, 91 { "SBC1", 41 }, 92 { "SBC2", 44 }, 93 { "SBC3", 46 }, 94 { "I2C5", 47 }, 95 { "DSIA", 48 }, 96 { "CSI", 52 }, 97 { "I2C2", 54 }, 98 { "UARTC", 55 }, 99 { "MIPI_CAL", 56 }, 100 { "EMC", 57 }, 101 { "USB2", 58 }, 102 { "BSEV", 63 }, 103 { "UARTD", 65 }, 104 { "I2C3", 67 }, 105 { "SBC4", 68 }, 106 { "SDMMC3", 69 }, 107 { "PCIE", 70 }, 108 { "OWR", 71 }, 109 { "AFI", 72 }, 110 { "CSITE", 73 }, 111 { "SOC_THERM", 78 }, 112 { "DTV", 79 }, 113 { "I2CSLOW", 81 }, 114 { "DSIB", 82 }, 115 { "TSEC", 83 }, 116 { "XUSB_HOST", 89 }, 117 { "CSUS", 92 }, 118 { "MSELECT", 99 }, 119 { "TSENSOR", 100 }, 120 { "I2S3", 101 }, 121 { "I2S4", 102 }, 122 { "I2C4", 103 }, 123 { "D_AUDIO", 106 }, 124 { "APB2APE", 107 }, 125 { "HDA2CODEC_2X", 111 }, 126 { "SPDIF_2X", 118 }, 127 { "ACTMON", 119 }, 128 { "EXTERN1", 120 }, 129 { "EXTERN2", 121 }, 130 { "EXTERN3", 122 }, 131 { "SATA_OOB", 123 }, 132 { "SATA", 124 }, 133 { "HDA", 125 }, 134 { "HDA2HDMI", 128 }, 135 { "XUSB_GATE", 143 }, 136 { "CILAB", 144 }, 137 { "CILCD", 145 }, 138 { "CILE", 146 }, 139 { "DSIALP", 147 }, 140 { "DSIBLP", 148 }, 141 { "ENTROPY", 149 }, 142 { "XUSB_SS", 156 }, 143 { "DMIC1", 161 }, 144 { "DMIC2", 162 }, 145 { "I2C6", 166 }, 146 { "VIM2_CLK", 171 }, 147 { "MIPIBIF", 173 }, 148 { "CLK72MHZ", 177 }, 149 { "VIC03", 178 }, 150 { "DPAUX", 181 }, 151 { "SOR0", 182 }, 152 { "SOR1", 183 }, 153 { "GPU", 184 }, 154 { "DBGAPB", 185 }, 155 { "PLL_P_OUT_ADSP", 187 }, 156 { "PLL_G_REF", 189 }, 157 { "SDMMC_LEGACY", 193 }, 158 { "NVDEC", 194 }, 159 { "NVJPG", 195 }, 160 { "DMIC3", 197 }, 161 { "APE", 198 }, 162 { "MAUD", 202 }, 163 { "TSECB", 206 }, 164 { "DPAUX1", 207 }, 165 { "VI_I2C", 208 }, 166 { "HSIC_TRK", 209 }, 167 { "USB2_TRK", 210 }, 168 { "QSPI", 211 }, 169 { "UARTAPE", 212 }, 170 { "NVENC", 219 }, 171 { "SOR_SAFE", 222 }, 172 { "PLL_P_OUT_CPU", 223 }, 173 { "UARTB", 224 }, 174 { "VFIR", 225 }, 175 { "SPDIF_IN", 226 }, 176 { "SPDIF_OUT", 227 }, 177 { "VI", 228 }, 178 { "VI_SENSOR", 229 }, 179 { "FUSE", 230 }, 180 { "FUSE_BURN", 231 }, 181 { "CLK_32K", 232 }, 182 { "CLK_M", 233 }, 183 { "CLK_M_DIV2", 234 }, 184 { "CLK_M_DIV4", 235 }, 185 { "PLL_REF", 236 }, 186 { "PLL_C", 237 }, 187 { "PLL_C_OUT1", 238 }, 188 { "PLL_C2", 239 }, 189 { "PLL_C3", 240 }, 190 { "PLL_M", 241 }, 191 { "PLL_M_OUT1", 242 }, 192 { "PLL_P", 243 }, 193 { "PLL_P_OUT1", 244 }, 194 { "PLL_P_OUT2", 245 }, 195 { "PLL_P_OUT3", 246 }, 196 { "PLL_P_OUT4", 247 }, 197 { "PLL_A", 248 }, 198 { "PLL_A_OUT0", 249 }, 199 { "PLL_D", 250 }, 200 { "PLL_D_OUT0", 251 }, 201 { "PLL_D2", 252 }, 202 { "PLL_D2_OUT0", 253 }, 203 { "PLL_U", 254 }, 204 { "PLL_U_480M", 255 }, 205 { "PLL_U_60M", 256 }, 206 { "PLL_U_48M", 257 }, 207 { "PLL_X", 259 }, 208 { "PLL_X_OUT0", 260 }, 209 { "PLL_RE_VCO", 261 }, 210 { "PLL_RE_OUT", 262 }, 211 { "PLL_E", 263 }, 212 { "SPDIF_IN_SYNC", 264 }, 213 { "I2S0_SYNC", 265 }, 214 { "I2S1_SYNC", 266 }, 215 { "I2S2_SYNC", 267 }, 216 { "I2S3_SYNC", 268 }, 217 { "I2S4_SYNC", 269 }, 218 { "VIMCLK_SYNC", 270 }, 219 { "AUDIO0", 271 }, 220 { "AUDIO1", 272 }, 221 { "AUDIO2", 273 }, 222 { "AUDIO3", 274 }, 223 { "AUDIO4", 275 }, 224 { "SPDIF", 276 }, 225 { "CLK_OUT_1", 277 }, 226 { "CLK_OUT_2", 278 }, 227 { "CLK_OUT_3", 279 }, 228 { "BLINK", 280 }, 229 { "SOR1_SRC", 282 }, 230 { "XUSB_HOST_SRC", 284 }, 231 { "XUSB_FALCON_SRC", 285 }, 232 { "XUSB_FS_SRC", 286 }, 233 { "XUSB_SS_SRC", 287 }, 234 { "XUSB_DEV_SRC", 288 }, 235 { "XUSB_DEV", 289 }, 236 { "XUSB_HS_SRC", 290 }, 237 { "SCLK", 291 }, 238 { "HCLK", 292 }, 239 { "PCLK", 293 }, 240 { "CCLK_G", 294 }, 241 { "CCLK_LP", 295 }, 242 { "DFLL_REF", 296 }, 243 { "DFLL_SOC", 297 }, 244 { "VI_SENSOR2", 298 }, 245 { "PLL_P_OUT5", 299 }, 246 { "CML0", 300 }, 247 { "CML1", 301 }, 248 { "PLL_C4", 302 }, 249 { "PLL_DP", 303 }, 250 { "PLL_E_MUX", 304 }, 251 { "PLL_MB", 305 }, 252 { "PLL_A1", 306 }, 253 { "PLL_D_DSI_OUT", 307 }, 254 { "PLL_C4_OUT0", 308 }, 255 { "PLL_C4_OUT1", 309 }, 256 { "PLL_C4_OUT2", 310 }, 257 { "PLL_C4_OUT3", 311 }, 258 { "PLL_U_OUT", 312 }, 259 { "PLL_U_OUT1", 313 }, 260 { "PLL_U_OUT2", 314 }, 261 { "USB2_HSIC_TRK", 315 }, 262 { "PLL_P_OUT_HSIO", 316 }, 263 { "PLL_P_OUT_XUSB", 317 }, 264 { "XUSB_SSP_SRC", 318 }, 265 { "PLL_RE_OUT1", 319 }, 266 { "AUDIO0_MUX", 350 }, 267 { "AUDIO1_MUX", 351 }, 268 { "AUDIO2_MUX", 352 }, 269 { "AUDIO3_MUX", 353 }, 270 { "AUDIO4_MUX", 354 }, 271 { "SPDIF_MUX", 355 }, 272 { "CLK_OUT_1_MUX", 356 }, 273 { "CLK_OUT_2_MUX", 357 }, 274 { "CLK_OUT_3_MUX", 358 }, 275 { "DSIA_MUX", 359 }, 276 { "DSIB_MUX", 360 }, 277 { "SOR0_LVDS", 361 }, 278 { "XUSB_SS_DIV2", 362 }, 279 { "PLL_M_UD", 363 }, 280 { "PLL_C_UD", 364 }, 281 { "SCLK_MUX", 365 }, 282 }; 283 284 static struct clk *tegra210_car_clock_get(void *, const char *); 285 static void tegra210_car_clock_put(void *, struct clk *); 286 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 287 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 288 static int tegra210_car_clock_enable(void *, struct clk *); 289 static int tegra210_car_clock_disable(void *, struct clk *); 290 static int tegra210_car_clock_set_parent(void *, struct clk *, 291 struct clk *); 292 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 293 294 static const struct clk_funcs tegra210_car_clock_funcs = { 295 .get = tegra210_car_clock_get, 296 .put = tegra210_car_clock_put, 297 .get_rate = tegra210_car_clock_get_rate, 298 .set_rate = tegra210_car_clock_set_rate, 299 .enable = tegra210_car_clock_enable, 300 .disable = tegra210_car_clock_disable, 301 .set_parent = tegra210_car_clock_set_parent, 302 .get_parent = tegra210_car_clock_get_parent, 303 }; 304 305 #define CLK_FIXED(_name, _rate) { \ 306 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 307 .u = { .fixed = { .rate = (_rate) } } \ 308 } 309 310 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 311 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 312 .parent = (_parent), \ 313 .u = { \ 314 .pll = { \ 315 .base_reg = (_base), \ 316 .divm_mask = (_divm), \ 317 .divn_mask = (_divn), \ 318 .divp_mask = (_divp), \ 319 } \ 320 } \ 321 } 322 323 #define CLK_MUX(_name, _reg, _bits, _p) { \ 324 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 325 .u = { \ 326 .mux = { \ 327 .nparents = __arraycount(_p), \ 328 .parents = (_p), \ 329 .reg = (_reg), \ 330 .bits = (_bits) \ 331 } \ 332 } \ 333 } 334 335 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 336 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 337 .parent = (_parent), \ 338 .u = { \ 339 .fixed_div = { \ 340 .div = (_div) \ 341 } \ 342 } \ 343 } 344 345 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 346 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 347 .parent = (_parent), \ 348 .u = { \ 349 .div = { \ 350 .reg = (_reg), \ 351 .bits = (_bits) \ 352 } \ 353 } \ 354 } 355 356 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 357 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 358 .type = TEGRA_CLK_GATE, \ 359 .parent = (_parent), \ 360 .u = { \ 361 .gate = { \ 362 .set_reg = (_set), \ 363 .clr_reg = (_clr), \ 364 .bits = (_bits), \ 365 } \ 366 } \ 367 } 368 369 #define CLK_GATE_L(_name, _parent, _bits) \ 370 CLK_GATE(_name, _parent, \ 371 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 372 _bits) 373 374 #define CLK_GATE_H(_name, _parent, _bits) \ 375 CLK_GATE(_name, _parent, \ 376 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 377 _bits) 378 379 #define CLK_GATE_U(_name, _parent, _bits) \ 380 CLK_GATE(_name, _parent, \ 381 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 382 _bits) 383 384 #define CLK_GATE_V(_name, _parent, _bits) \ 385 CLK_GATE(_name, _parent, \ 386 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 387 _bits) 388 389 #define CLK_GATE_W(_name, _parent, _bits) \ 390 CLK_GATE(_name, _parent, \ 391 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 392 _bits) 393 394 #define CLK_GATE_X(_name, _parent, _bits) \ 395 CLK_GATE(_name, _parent, \ 396 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 397 _bits) 398 399 #define CLK_GATE_Y(_name, _parent, _bits) \ 400 CLK_GATE(_name, _parent, \ 401 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 402 _bits) 403 404 405 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 406 CLK_GATE(_name, _parent, _reg, _reg, _bits) 407 408 static const char *mux_uart_p[] = 409 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 410 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 411 412 static const char *mux_sdmmc1_p[] = 413 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 414 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 415 416 static const char *mux_sdmmc2_4_p[] = 417 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 418 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 419 420 static const char *mux_sdmmc3_p[] = 421 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 422 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 423 424 static const char *mux_i2c_p[] = 425 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 426 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 427 428 static const char *mux_xusb_host_p[] = 429 { "CLK_M", "PLL_P", NULL, NULL, 430 NULL, "PLL_REF", NULL, NULL }; 431 432 static const char *mux_xusb_fs_p[] = 433 { "CLK_M", NULL, "PLL_U_48M", NULL, 434 "PLL_P", NULL, "PLL_U_480M", NULL }; 435 436 static const char *mux_xusb_ss_p[] = 437 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 438 NULL, NULL, NULL, NULL }; 439 440 static struct tegra_clk tegra210_car_clocks[] = { 441 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 442 443 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 444 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 445 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 446 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 447 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 448 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 449 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 450 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 451 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 452 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 453 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 454 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 455 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 456 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 457 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 458 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 459 460 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 461 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 462 463 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 464 mux_uart_p), 465 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 466 mux_uart_p), 467 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 468 mux_uart_p), 469 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 470 mux_uart_p), 471 472 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 473 mux_sdmmc1_p), 474 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 475 mux_sdmmc2_4_p), 476 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 477 mux_sdmmc3_p), 478 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 479 mux_sdmmc2_4_p), 480 481 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 487 488 CLK_MUX("MUX_XUSB_HOST", 489 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 490 mux_xusb_host_p), 491 CLK_MUX("MUX_XUSB_FALCON", 492 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 493 mux_xusb_host_p), 494 CLK_MUX("MUX_XUSB_SS", 495 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 496 mux_xusb_ss_p), 497 CLK_MUX("MUX_XUSB_FS", 498 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 499 mux_xusb_fs_p), 500 501 CLK_DIV("DIV_UARTA", "MUX_UARTA", 502 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 503 CLK_DIV("DIV_UARTB", "MUX_UARTB", 504 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 505 CLK_DIV("DIV_UARTC", "MUX_UARTC", 506 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 507 CLK_DIV("DIV_UARTD", "MUX_UARTD", 508 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 509 510 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 511 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 512 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 513 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 514 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 515 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 516 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 517 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 518 519 CLK_DIV("DIV_I2C1", "MUX_I2C1", 520 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 521 CLK_DIV("DIV_I2C2", "MUX_I2C2", 522 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 523 CLK_DIV("DIV_I2C3", "MUX_I2C3", 524 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 525 CLK_DIV("DIV_I2C4", "MUX_I2C4", 526 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 527 CLK_DIV("DIV_I2C5", "MUX_I2C5", 528 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 529 CLK_DIV("DIV_I2C6", "MUX_I2C6", 530 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 531 532 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 533 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 534 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 535 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 536 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 537 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 538 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 539 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 540 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 541 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 542 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 543 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 544 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 545 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 546 547 CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 548 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 549 CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 550 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 551 552 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 553 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 554 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 555 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 556 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 557 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 558 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 559 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 560 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 561 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 562 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 563 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 564 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 565 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 566 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 567 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 568 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 569 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 570 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 571 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 572 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 573 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 574 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 575 }; 576 577 struct tegra210_init_parent { 578 const char *clock; 579 const char *parent; 580 u_int rate; 581 u_int enable; 582 } tegra210_init_parents[] = { 583 { "SDMMC1", "PLL_P", 0, 0 }, 584 { "SDMMC2", "PLL_P", 0, 0 }, 585 { "SDMMC3", "PLL_P", 0, 0 }, 586 { "SDMMC4", "PLL_P", 0, 0 }, 587 { "XUSB_GATE", NULL, 0, 1 }, 588 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 589 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 590 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 591 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 592 { "PLL_U_OUT1", NULL, 48000000, 1 }, 593 { "PLL_U_OUT2", NULL, 60000000, 1 }, 594 }; 595 596 struct tegra210_car_rst { 597 u_int set_reg; 598 u_int clr_reg; 599 u_int mask; 600 }; 601 602 static struct tegra210_car_reset_reg { 603 u_int set_reg; 604 u_int clr_reg; 605 } tegra210_car_reset_regs[] = { 606 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 607 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 608 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 609 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 610 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 611 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 612 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 613 }; 614 615 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 616 static void tegra210_car_reset_release(device_t, void *); 617 static int tegra210_car_reset_assert(device_t, void *); 618 static int tegra210_car_reset_deassert(device_t, void *); 619 620 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 621 .acquire = tegra210_car_reset_acquire, 622 .release = tegra210_car_reset_release, 623 .reset_assert = tegra210_car_reset_assert, 624 .reset_deassert = tegra210_car_reset_deassert, 625 }; 626 627 struct tegra210_car_softc { 628 device_t sc_dev; 629 bus_space_tag_t sc_bst; 630 bus_space_handle_t sc_bsh; 631 632 struct clk_domain sc_clkdom; 633 634 u_int sc_clock_cells; 635 u_int sc_reset_cells; 636 637 kmutex_t sc_rndlock; 638 krndsource_t sc_rndsource; 639 }; 640 641 static void tegra210_car_init(struct tegra210_car_softc *); 642 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 643 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 644 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 645 static void tegra210_car_parent_init(struct tegra210_car_softc *); 646 647 648 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 649 tegra210_car_match, tegra210_car_attach, NULL, NULL); 650 651 static int 652 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 653 { 654 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 655 struct fdt_attach_args * const faa = aux; 656 657 #if 0 658 return of_match_compatible(faa->faa_phandle, compatible); 659 #else 660 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 661 return 0; 662 663 return 999; 664 #endif 665 } 666 667 static void 668 tegra210_car_attach(device_t parent, device_t self, void *aux) 669 { 670 struct tegra210_car_softc * const sc = device_private(self); 671 struct fdt_attach_args * const faa = aux; 672 const int phandle = faa->faa_phandle; 673 bus_addr_t addr; 674 bus_size_t size; 675 int error, n; 676 677 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 678 aprint_error(": couldn't get registers\n"); 679 return; 680 } 681 682 sc->sc_dev = self; 683 sc->sc_bst = faa->faa_bst; 684 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 685 if (error) { 686 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 687 return; 688 } 689 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 690 sc->sc_clock_cells = 1; 691 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 692 sc->sc_reset_cells = 1; 693 694 aprint_naive("\n"); 695 aprint_normal(": CAR\n"); 696 697 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 698 sc->sc_clkdom.priv = sc; 699 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 700 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 701 702 fdtbus_register_clock_controller(self, phandle, 703 &tegra210_car_fdtclock_funcs); 704 fdtbus_register_reset_controller(self, phandle, 705 &tegra210_car_fdtreset_funcs); 706 707 tegra210_car_init(sc); 708 709 #ifdef TEGRA210_CAR_DEBUG 710 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 711 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 712 struct clk *clk_parent = clk_get_parent(clk); 713 device_printf(self, "clk %s (parent %s): ", clk->name, 714 clk_parent ? clk_parent->name : "none"); 715 printf("%u Hz\n", clk_get_rate(clk)); 716 } 717 #endif 718 } 719 720 static void 721 tegra210_car_init(struct tegra210_car_softc *sc) 722 { 723 tegra210_car_parent_init(sc); 724 tegra210_car_utmip_init(sc); 725 tegra210_car_xusb_init(sc); 726 tegra210_car_watchdog_init(sc); 727 } 728 729 static void 730 tegra210_car_parent_init(struct tegra210_car_softc *sc) 731 { 732 struct clk *clk, *clk_parent; 733 int error; 734 u_int n; 735 736 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 737 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 738 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 739 740 if (tegra210_init_parents[n].parent != NULL) { 741 clk_parent = clk_get(&sc->sc_clkdom, 742 tegra210_init_parents[n].parent); 743 KASSERT(clk_parent != NULL); 744 745 error = clk_set_parent(clk, clk_parent); 746 if (error) { 747 aprint_error_dev(sc->sc_dev, 748 "couldn't set '%s' parent to '%s': %d\n", 749 clk->name, clk_parent->name, error); 750 } 751 clk_put(clk_parent); 752 } 753 if (tegra210_init_parents[n].rate != 0) { 754 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 755 if (error) { 756 aprint_error_dev(sc->sc_dev, 757 "couldn't set '%s' rate to %u Hz: %d\n", 758 clk->name, tegra210_init_parents[n].rate, 759 error); 760 } 761 } 762 if (tegra210_init_parents[n].enable) { 763 error = clk_enable(clk); 764 if (error) { 765 aprint_error_dev(sc->sc_dev, 766 "couldn't enable '%s': %d\n", clk->name, 767 error); 768 } 769 } 770 clk_put(clk); 771 } 772 } 773 774 static void 775 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 776 { 777 bus_space_tag_t bst = sc->sc_bst; 778 bus_space_handle_t bsh = sc->sc_bsh; 779 780 /* 781 * Set up the UTMI PLL. 782 */ 783 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 784 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 785 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 786 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 787 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 788 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 789 delay(10); 790 /* TODO UTMIP_PLL_CFG0 */ 791 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 792 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 793 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 794 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 795 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 796 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 797 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 798 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 799 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 800 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 801 802 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 803 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 804 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 805 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 806 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 807 808 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 809 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 810 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 811 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 812 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 813 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 814 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 815 816 /* 817 * Set up UTMI PLL under hardware control 818 */ 819 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 820 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 821 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 822 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 823 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 824 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 825 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 826 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 827 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 828 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 829 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 830 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 831 delay(1); 832 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 833 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 834 } 835 836 static void 837 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 838 { 839 const bus_space_tag_t bst = sc->sc_bst; 840 const bus_space_handle_t bsh = sc->sc_bsh; 841 uint32_t val; 842 843 /* 844 * Set up the PLLU. 845 */ 846 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 847 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 848 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 849 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 850 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 851 delay(5); 852 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 853 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 854 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 855 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 856 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 857 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 858 do { 859 delay(2); 860 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 861 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 862 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 863 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 864 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 865 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 866 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 867 delay(2); 868 869 /* 870 * Now switch PLLU to hw controlled mode. 871 */ 872 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 873 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 874 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 875 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 876 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 877 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 878 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 879 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 880 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 881 delay(1); 882 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 883 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 884 delay(1); 885 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 886 887 /* 888 * Set up PLLREFE 889 */ 890 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 891 0, CAR_PLLREFE_MISC_IDDQ); 892 delay(5); 893 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 894 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 895 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 896 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 897 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 898 CAR_PLLREFE_BASE_DIVM | 899 CAR_PLLREFE_BASE_DIVN | 900 CAR_PLLREFE_BASE_DIVP | 901 CAR_PLLREFE_BASE_KCP); 902 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 903 CAR_PLLREFE_BASE_ENABLE, 0); 904 do { 905 delay(2); 906 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 907 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 908 909 /* 910 * Set up the PLLE. 911 */ 912 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 913 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 914 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 915 delay(5); 916 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 917 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 918 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 919 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 920 CAR_PLLE_BASE_DIVP_CML | 921 CAR_PLLE_BASE_DIVN | 922 CAR_PLLE_BASE_DIVM); 923 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 924 CAR_PLLE_MISC_PTS, 925 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 926 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 927 do { 928 delay(2); 929 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 930 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 931 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 932 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 933 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 934 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 935 CAR_PLLE_SS_CNTL_SSCINC | 936 CAR_PLLE_SS_CNTL_SSCINCINTRV | 937 CAR_PLLE_SS_CNTL_SSCMAX | 938 CAR_PLLE_SS_CNTL_SSCINVERT | 939 CAR_PLLE_SS_CNTL_SSCCENTER | 940 CAR_PLLE_SS_CNTL_BYPASS_SS | 941 CAR_PLLE_SS_CNTL_SSCBYP); 942 delay(1); 943 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 944 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 945 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 946 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 947 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 948 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 949 delay(1); 950 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 951 952 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 953 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 954 } 955 956 static void 957 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 958 { 959 const bus_space_tag_t bst = sc->sc_bst; 960 const bus_space_handle_t bsh = sc->sc_bsh; 961 962 /* Enable watchdog timer reset for system */ 963 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 964 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 965 } 966 967 static struct tegra_clk * 968 tegra210_car_clock_find(const char *name) 969 { 970 u_int n; 971 972 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 973 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 974 return &tegra210_car_clocks[n]; 975 } 976 } 977 978 return NULL; 979 } 980 981 static struct tegra_clk * 982 tegra210_car_clock_find_by_id(u_int clock_id) 983 { 984 u_int n; 985 986 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 987 if (tegra210_car_clock_ids[n].id == clock_id) { 988 const char *name = tegra210_car_clock_ids[n].name; 989 return tegra210_car_clock_find(name); 990 } 991 } 992 993 return NULL; 994 } 995 996 static struct clk * 997 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 998 { 999 struct tegra210_car_softc * const sc = device_private(dev); 1000 struct tegra_clk *tclk; 1001 1002 if (len != sc->sc_clock_cells * 4) { 1003 return NULL; 1004 } 1005 1006 const u_int clock_id = be32dec(data); 1007 1008 tclk = tegra210_car_clock_find_by_id(clock_id); 1009 if (tclk) 1010 return TEGRA_CLK_BASE(tclk); 1011 1012 return NULL; 1013 } 1014 1015 static struct clk * 1016 tegra210_car_clock_get(void *priv, const char *name) 1017 { 1018 struct tegra_clk *tclk; 1019 1020 tclk = tegra210_car_clock_find(name); 1021 if (tclk == NULL) 1022 return NULL; 1023 1024 atomic_inc_uint(&tclk->refcnt); 1025 1026 return TEGRA_CLK_BASE(tclk); 1027 } 1028 1029 static void 1030 tegra210_car_clock_put(void *priv, struct clk *clk) 1031 { 1032 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1033 1034 KASSERT(tclk->refcnt > 0); 1035 1036 atomic_dec_uint(&tclk->refcnt); 1037 } 1038 1039 static u_int 1040 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1041 struct tegra_clk *tclk) 1042 { 1043 struct tegra_pll_clk *tpll = &tclk->u.pll; 1044 struct tegra_clk *tclk_parent; 1045 bus_space_tag_t bst = sc->sc_bst; 1046 bus_space_handle_t bsh = sc->sc_bsh; 1047 u_int divm, divn, divp; 1048 uint64_t rate; 1049 1050 KASSERT(tclk->type == TEGRA_CLK_PLL); 1051 1052 tclk_parent = tegra210_car_clock_find(tclk->parent); 1053 KASSERT(tclk_parent != NULL); 1054 1055 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1056 TEGRA_CLK_BASE(tclk_parent)); 1057 1058 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1059 divm = __SHIFTOUT(base, tpll->divm_mask); 1060 divn = __SHIFTOUT(base, tpll->divn_mask); 1061 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1062 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1063 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1064 /* XXX divp is not applied to PLLP's primary output */ 1065 divp = 0; 1066 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1067 divp = 0; 1068 divm *= __SHIFTOUT(base, tpll->divp_mask); 1069 } else { 1070 divp = __SHIFTOUT(base, tpll->divp_mask); 1071 } 1072 1073 rate = (uint64_t)rate_parent * divn; 1074 return rate / (divm << divp); 1075 } 1076 1077 static int 1078 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1079 struct tegra_clk *tclk, u_int rate) 1080 { 1081 struct tegra_pll_clk *tpll = &tclk->u.pll; 1082 bus_space_tag_t bst = sc->sc_bst; 1083 bus_space_handle_t bsh = sc->sc_bsh; 1084 struct clk *clk_parent; 1085 uint32_t bp, base; 1086 1087 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1088 if (clk_parent == NULL) 1089 return EIO; 1090 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1091 if (rate_parent == 0) 1092 return EIO; 1093 1094 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1095 const u_int divm = 1; 1096 const u_int divn = rate / rate_parent; 1097 const u_int divp = 0; 1098 1099 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1100 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1101 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1102 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1103 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1104 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1105 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1106 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1107 1108 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1109 base &= ~CAR_PLLX_BASE_DIVM; 1110 base &= ~CAR_PLLX_BASE_DIVN; 1111 base &= ~CAR_PLLX_BASE_DIVP; 1112 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1113 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1114 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1115 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1116 1117 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1118 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1119 do { 1120 delay(2); 1121 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1122 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1123 delay(100); 1124 1125 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1126 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1127 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1128 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1129 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1130 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1131 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1132 1133 return 0; 1134 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1135 const u_int divm = 1; 1136 const u_int pldiv = 1; 1137 const u_int divn = (rate << pldiv) / rate_parent; 1138 1139 /* Set frequency */ 1140 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1141 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1142 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1143 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1144 CAR_PLLD2_BASE_REF_SRC_SEL | 1145 CAR_PLLD2_BASE_DIVM | 1146 CAR_PLLD2_BASE_DIVN | 1147 CAR_PLLD2_BASE_DIVP); 1148 1149 return 0; 1150 } else { 1151 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1152 tclk->base.name, rate); 1153 /* TODO */ 1154 return EOPNOTSUPP; 1155 } 1156 } 1157 1158 static int 1159 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1160 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1161 { 1162 struct tegra_mux_clk *tmux = &tclk->u.mux; 1163 bus_space_tag_t bst = sc->sc_bst; 1164 bus_space_handle_t bsh = sc->sc_bsh; 1165 uint32_t v; 1166 u_int src; 1167 1168 KASSERT(tclk->type == TEGRA_CLK_MUX); 1169 1170 for (src = 0; src < tmux->nparents; src++) { 1171 if (tmux->parents[src] == NULL) { 1172 continue; 1173 } 1174 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1175 break; 1176 } 1177 } 1178 if (src == tmux->nparents) { 1179 return EINVAL; 1180 } 1181 1182 v = bus_space_read_4(bst, bsh, tmux->reg); 1183 v &= ~tmux->bits; 1184 v |= __SHIFTIN(src, tmux->bits); 1185 bus_space_write_4(bst, bsh, tmux->reg, v); 1186 1187 return 0; 1188 } 1189 1190 static struct tegra_clk * 1191 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1192 struct tegra_clk *tclk) 1193 { 1194 struct tegra_mux_clk *tmux = &tclk->u.mux; 1195 bus_space_tag_t bst = sc->sc_bst; 1196 bus_space_handle_t bsh = sc->sc_bsh; 1197 1198 KASSERT(tclk->type == TEGRA_CLK_MUX); 1199 1200 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1201 const u_int src = __SHIFTOUT(v, tmux->bits); 1202 1203 KASSERT(src < tmux->nparents); 1204 1205 if (tmux->parents[src] == NULL) { 1206 return NULL; 1207 } 1208 1209 return tegra210_car_clock_find(tmux->parents[src]); 1210 } 1211 1212 static u_int 1213 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1214 struct tegra_clk *tclk) 1215 { 1216 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1217 struct clk *clk_parent; 1218 1219 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1220 if (clk_parent == NULL) 1221 return 0; 1222 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1223 1224 return parent_rate / tfixed_div->div; 1225 } 1226 1227 static u_int 1228 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1229 struct tegra_clk *tclk) 1230 { 1231 struct tegra_div_clk *tdiv = &tclk->u.div; 1232 bus_space_tag_t bst = sc->sc_bst; 1233 bus_space_handle_t bsh = sc->sc_bsh; 1234 struct clk *clk_parent; 1235 u_int rate; 1236 1237 KASSERT(tclk->type == TEGRA_CLK_DIV); 1238 1239 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1240 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1241 1242 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1243 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1244 1245 switch (tdiv->reg) { 1246 case CAR_CLKSRC_I2C1_REG: 1247 case CAR_CLKSRC_I2C2_REG: 1248 case CAR_CLKSRC_I2C3_REG: 1249 case CAR_CLKSRC_I2C4_REG: 1250 case CAR_CLKSRC_I2C5_REG: 1251 case CAR_CLKSRC_I2C6_REG: 1252 rate = parent_rate / (raw_div + 1); 1253 break; 1254 case CAR_CLKSRC_UARTA_REG: 1255 case CAR_CLKSRC_UARTB_REG: 1256 case CAR_CLKSRC_UARTC_REG: 1257 case CAR_CLKSRC_UARTD_REG: 1258 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1259 rate = parent_rate / ((raw_div / 2) + 1); 1260 } else { 1261 rate = parent_rate; 1262 } 1263 break; 1264 case CAR_CLKSRC_SDMMC2_REG: 1265 case CAR_CLKSRC_SDMMC4_REG: 1266 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1267 case 1: 1268 case 2: 1269 case 5: 1270 raw_div = 0; /* ignore divisor for _LJ options */ 1271 break; 1272 } 1273 /* FALLTHROUGH */ 1274 default: 1275 rate = parent_rate / ((raw_div / 2) + 1); 1276 break; 1277 } 1278 1279 return rate; 1280 } 1281 1282 static int 1283 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1284 struct tegra_clk *tclk, u_int rate) 1285 { 1286 struct tegra_div_clk *tdiv = &tclk->u.div; 1287 bus_space_tag_t bst = sc->sc_bst; 1288 bus_space_handle_t bsh = sc->sc_bsh; 1289 struct clk *clk_parent; 1290 u_int raw_div; 1291 uint32_t v; 1292 1293 KASSERT(tclk->type == TEGRA_CLK_DIV); 1294 1295 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1296 if (clk_parent == NULL) 1297 return EINVAL; 1298 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1299 1300 v = bus_space_read_4(bst, bsh, tdiv->reg); 1301 1302 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1303 1304 switch (tdiv->reg) { 1305 case CAR_CLKSRC_UARTA_REG: 1306 case CAR_CLKSRC_UARTB_REG: 1307 case CAR_CLKSRC_UARTC_REG: 1308 case CAR_CLKSRC_UARTD_REG: 1309 if (rate == parent_rate) { 1310 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1311 } else if (rate) { 1312 v |= CAR_CLKSRC_UART_DIV_ENB; 1313 raw_div = (parent_rate / rate) * 2; 1314 if (raw_div >= 2) 1315 raw_div -= 2; 1316 } 1317 break; 1318 case CAR_CLKSRC_I2C1_REG: 1319 case CAR_CLKSRC_I2C2_REG: 1320 case CAR_CLKSRC_I2C3_REG: 1321 case CAR_CLKSRC_I2C4_REG: 1322 case CAR_CLKSRC_I2C5_REG: 1323 case CAR_CLKSRC_I2C6_REG: 1324 if (rate) 1325 raw_div = (parent_rate / rate) - 1; 1326 break; 1327 case CAR_CLKSRC_SDMMC1_REG: 1328 case CAR_CLKSRC_SDMMC2_REG: 1329 case CAR_CLKSRC_SDMMC3_REG: 1330 case CAR_CLKSRC_SDMMC4_REG: 1331 if (rate) { 1332 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1333 u_int calc_rate = 1334 parent_rate / ((raw_div / 2) + 1); 1335 if (calc_rate <= rate) 1336 break; 1337 } 1338 if (raw_div == 0x100) 1339 return EINVAL; 1340 } 1341 break; 1342 default: 1343 if (rate) { 1344 raw_div = (parent_rate / rate) * 2; 1345 if (raw_div >= 2) 1346 raw_div -= 2; 1347 } 1348 break; 1349 } 1350 1351 v &= ~tdiv->bits; 1352 v |= __SHIFTIN(raw_div, tdiv->bits); 1353 1354 bus_space_write_4(bst, bsh, tdiv->reg, v); 1355 1356 return 0; 1357 } 1358 1359 static int 1360 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1361 struct tegra_clk *tclk, bool enable) 1362 { 1363 struct tegra_gate_clk *tgate = &tclk->u.gate; 1364 bus_space_tag_t bst = sc->sc_bst; 1365 bus_space_handle_t bsh = sc->sc_bsh; 1366 bus_size_t reg; 1367 1368 KASSERT(tclk->type == TEGRA_CLK_GATE); 1369 1370 if (tgate->set_reg == tgate->clr_reg) { 1371 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1372 if (enable) { 1373 v |= tgate->bits; 1374 } else { 1375 v &= ~tgate->bits; 1376 } 1377 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1378 } else { 1379 if (enable) { 1380 reg = tgate->set_reg; 1381 } else { 1382 reg = tgate->clr_reg; 1383 } 1384 bus_space_write_4(bst, bsh, reg, tgate->bits); 1385 } 1386 1387 return 0; 1388 } 1389 1390 static u_int 1391 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1392 { 1393 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1394 struct clk *clk_parent; 1395 1396 switch (tclk->type) { 1397 case TEGRA_CLK_FIXED: 1398 return tclk->u.fixed.rate; 1399 case TEGRA_CLK_PLL: 1400 return tegra210_car_clock_get_rate_pll(priv, tclk); 1401 case TEGRA_CLK_MUX: 1402 case TEGRA_CLK_GATE: 1403 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1404 if (clk_parent == NULL) 1405 return EINVAL; 1406 return tegra210_car_clock_get_rate(priv, clk_parent); 1407 case TEGRA_CLK_FIXED_DIV: 1408 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1409 case TEGRA_CLK_DIV: 1410 return tegra210_car_clock_get_rate_div(priv, tclk); 1411 default: 1412 panic("tegra210: unknown tclk type %d", tclk->type); 1413 } 1414 } 1415 1416 static int 1417 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1418 { 1419 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1420 struct clk *clk_parent; 1421 1422 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1423 1424 switch (tclk->type) { 1425 case TEGRA_CLK_FIXED: 1426 case TEGRA_CLK_MUX: 1427 return EIO; 1428 case TEGRA_CLK_FIXED_DIV: 1429 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1430 if (clk_parent == NULL) 1431 return EIO; 1432 return tegra210_car_clock_set_rate(priv, clk_parent, 1433 rate * tclk->u.fixed_div.div); 1434 case TEGRA_CLK_GATE: 1435 return EINVAL; 1436 case TEGRA_CLK_PLL: 1437 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1438 case TEGRA_CLK_DIV: 1439 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1440 default: 1441 panic("tegra210: unknown tclk type %d", tclk->type); 1442 } 1443 } 1444 1445 static int 1446 tegra210_car_clock_enable(void *priv, struct clk *clk) 1447 { 1448 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1449 struct clk *clk_parent; 1450 1451 if (tclk->type != TEGRA_CLK_GATE) { 1452 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1453 if (clk_parent == NULL) 1454 return 0; 1455 return tegra210_car_clock_enable(priv, clk_parent); 1456 } 1457 1458 return tegra210_car_clock_enable_gate(priv, tclk, true); 1459 } 1460 1461 static int 1462 tegra210_car_clock_disable(void *priv, struct clk *clk) 1463 { 1464 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1465 1466 if (tclk->type != TEGRA_CLK_GATE) 1467 return EINVAL; 1468 1469 return tegra210_car_clock_enable_gate(priv, tclk, false); 1470 } 1471 1472 static int 1473 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1474 struct clk *clk_parent) 1475 { 1476 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1477 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1478 struct clk *nclk_parent; 1479 1480 if (tclk->type != TEGRA_CLK_MUX) { 1481 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1482 if (nclk_parent == clk_parent || nclk_parent == NULL) 1483 return EINVAL; 1484 return tegra210_car_clock_set_parent(priv, nclk_parent, 1485 clk_parent); 1486 } 1487 1488 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1489 } 1490 1491 static struct clk * 1492 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1493 { 1494 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1495 struct tegra_clk *tclk_parent = NULL; 1496 1497 switch (tclk->type) { 1498 case TEGRA_CLK_FIXED: 1499 case TEGRA_CLK_PLL: 1500 case TEGRA_CLK_FIXED_DIV: 1501 case TEGRA_CLK_DIV: 1502 case TEGRA_CLK_GATE: 1503 if (tclk->parent) { 1504 tclk_parent = tegra210_car_clock_find(tclk->parent); 1505 } 1506 break; 1507 case TEGRA_CLK_MUX: 1508 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1509 break; 1510 } 1511 1512 if (tclk_parent == NULL) 1513 return NULL; 1514 1515 return TEGRA_CLK_BASE(tclk_parent); 1516 } 1517 1518 static void * 1519 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1520 { 1521 struct tegra210_car_softc * const sc = device_private(dev); 1522 struct tegra210_car_rst *rst; 1523 1524 if (len != sc->sc_reset_cells * 4) 1525 return NULL; 1526 1527 const u_int reset_id = be32dec(data); 1528 1529 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1530 return NULL; 1531 1532 const u_int reg = reset_id / 32; 1533 1534 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1535 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1536 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1537 rst->mask = __BIT(reset_id % 32); 1538 1539 return rst; 1540 } 1541 1542 static void 1543 tegra210_car_reset_release(device_t dev, void *priv) 1544 { 1545 struct tegra210_car_rst *rst = priv; 1546 1547 kmem_free(rst, sizeof(*rst)); 1548 } 1549 1550 static int 1551 tegra210_car_reset_assert(device_t dev, void *priv) 1552 { 1553 struct tegra210_car_softc * const sc = device_private(dev); 1554 struct tegra210_car_rst *rst = priv; 1555 1556 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1557 1558 return 0; 1559 } 1560 1561 static int 1562 tegra210_car_reset_deassert(device_t dev, void *priv) 1563 { 1564 struct tegra210_car_softc * const sc = device_private(dev); 1565 struct tegra210_car_rst *rst = priv; 1566 1567 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1568 1569 return 0; 1570 } 1571 1572 void 1573 tegra210_car_xusbio_enable_hw_control(void) 1574 { 1575 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1576 KASSERT(dev != NULL); 1577 struct tegra210_car_softc * const sc = device_private(dev); 1578 bus_space_tag_t bst = sc->sc_bst; 1579 bus_space_handle_t bsh = sc->sc_bsh; 1580 1581 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1582 0, 1583 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1584 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1585 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1586 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1587 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1588 0); 1589 } 1590 1591 void 1592 tegra210_car_xusbio_enable_hw_seq(void) 1593 { 1594 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1595 KASSERT(dev != NULL); 1596 struct tegra210_car_softc * const sc = device_private(dev); 1597 bus_space_tag_t bst = sc->sc_bst; 1598 bus_space_handle_t bsh = sc->sc_bsh; 1599 1600 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1601 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1602 } 1603
Indexes created Tue Sep 30 11:09:46 GMT 2025