tegra210_car.c revision 1.12
1 /* $NetBSD: tegra210_car.c,v 1.12 2017/09/25 00:12:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.12 2017/09/25 00:12:21 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static struct tegra_clk tegra210_car_clocks[] = { 440 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 441 442 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 443 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 444 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 445 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 446 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 447 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 448 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 449 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 450 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 451 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 452 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 453 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 454 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 455 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 456 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 457 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 458 459 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 460 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 461 462 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 463 mux_uart_p), 464 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 465 mux_uart_p), 466 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 469 mux_uart_p), 470 471 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc1_p), 473 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc2_4_p), 475 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 476 mux_sdmmc3_p), 477 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 478 mux_sdmmc2_4_p), 479 480 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 487 CLK_MUX("MUX_XUSB_HOST", 488 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 489 mux_xusb_host_p), 490 CLK_MUX("MUX_XUSB_FALCON", 491 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 492 mux_xusb_host_p), 493 CLK_MUX("MUX_XUSB_SS", 494 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 495 mux_xusb_ss_p), 496 CLK_MUX("MUX_XUSB_FS", 497 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 498 mux_xusb_fs_p), 499 500 CLK_DIV("DIV_UARTA", "MUX_UARTA", 501 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 502 CLK_DIV("DIV_UARTB", "MUX_UARTB", 503 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 504 CLK_DIV("DIV_UARTC", "MUX_UARTC", 505 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 506 CLK_DIV("DIV_UARTD", "MUX_UARTD", 507 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 508 509 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 510 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 511 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 512 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 513 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 514 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 515 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 516 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 517 518 CLK_DIV("DIV_I2C1", "MUX_I2C1", 519 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 520 CLK_DIV("DIV_I2C2", "MUX_I2C2", 521 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 522 CLK_DIV("DIV_I2C3", "MUX_I2C3", 523 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 524 CLK_DIV("DIV_I2C4", "MUX_I2C4", 525 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 526 CLK_DIV("DIV_I2C5", "MUX_I2C5", 527 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 528 CLK_DIV("DIV_I2C6", "MUX_I2C6", 529 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 530 531 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 532 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 533 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 534 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 535 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 536 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 537 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 538 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 539 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 540 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 541 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 542 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 543 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 544 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 545 546 CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 547 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 548 CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 549 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 550 551 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 552 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 553 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 554 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 555 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 556 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 557 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 558 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 559 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 560 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 561 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 562 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 563 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 564 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 565 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 566 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 567 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 568 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 569 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 570 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 571 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 572 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 573 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 574 }; 575 576 struct tegra210_init_parent { 577 const char *clock; 578 const char *parent; 579 u_int rate; 580 u_int enable; 581 } tegra210_init_parents[] = { 582 { "SDMMC1", "PLL_P", 0, 0 }, 583 { "SDMMC2", "PLL_P", 0, 0 }, 584 { "SDMMC3", "PLL_P", 0, 0 }, 585 { "SDMMC4", "PLL_P", 0, 0 }, 586 { "XUSB_GATE", NULL, 0, 1 }, 587 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 588 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 589 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 590 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 591 { "PLL_U_OUT1", NULL, 48000000, 1 }, 592 { "PLL_U_OUT2", NULL, 60000000, 1 }, 593 }; 594 595 struct tegra210_car_rst { 596 u_int set_reg; 597 u_int clr_reg; 598 u_int mask; 599 }; 600 601 static struct tegra210_car_reset_reg { 602 u_int set_reg; 603 u_int clr_reg; 604 } tegra210_car_reset_regs[] = { 605 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 606 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 607 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 608 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 609 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 610 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 611 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 612 }; 613 614 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 615 static void tegra210_car_reset_release(device_t, void *); 616 static int tegra210_car_reset_assert(device_t, void *); 617 static int tegra210_car_reset_deassert(device_t, void *); 618 619 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 620 .acquire = tegra210_car_reset_acquire, 621 .release = tegra210_car_reset_release, 622 .reset_assert = tegra210_car_reset_assert, 623 .reset_deassert = tegra210_car_reset_deassert, 624 }; 625 626 struct tegra210_car_softc { 627 device_t sc_dev; 628 bus_space_tag_t sc_bst; 629 bus_space_handle_t sc_bsh; 630 631 struct clk_domain sc_clkdom; 632 633 u_int sc_clock_cells; 634 u_int sc_reset_cells; 635 636 kmutex_t sc_rndlock; 637 krndsource_t sc_rndsource; 638 }; 639 640 static void tegra210_car_init(struct tegra210_car_softc *); 641 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 642 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 643 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 644 static void tegra210_car_parent_init(struct tegra210_car_softc *); 645 646 647 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 648 tegra210_car_match, tegra210_car_attach, NULL, NULL); 649 650 static int 651 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 652 { 653 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 654 struct fdt_attach_args * const faa = aux; 655 656 #if 0 657 return of_match_compatible(faa->faa_phandle, compatible); 658 #else 659 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 660 return 0; 661 662 return 999; 663 #endif 664 } 665 666 static void 667 tegra210_car_attach(device_t parent, device_t self, void *aux) 668 { 669 struct tegra210_car_softc * const sc = device_private(self); 670 struct fdt_attach_args * const faa = aux; 671 const int phandle = faa->faa_phandle; 672 bus_addr_t addr; 673 bus_size_t size; 674 int error, n; 675 676 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 677 aprint_error(": couldn't get registers\n"); 678 return; 679 } 680 681 sc->sc_dev = self; 682 sc->sc_bst = faa->faa_bst; 683 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 684 if (error) { 685 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 686 return; 687 } 688 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 689 sc->sc_clock_cells = 1; 690 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 691 sc->sc_reset_cells = 1; 692 693 aprint_naive("\n"); 694 aprint_normal(": CAR\n"); 695 696 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 697 sc->sc_clkdom.priv = sc; 698 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 699 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 700 701 fdtbus_register_clock_controller(self, phandle, 702 &tegra210_car_fdtclock_funcs); 703 fdtbus_register_reset_controller(self, phandle, 704 &tegra210_car_fdtreset_funcs); 705 706 tegra210_car_init(sc); 707 708 #ifdef TEGRA210_CAR_DEBUG 709 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 710 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 711 struct clk *clk_parent = clk_get_parent(clk); 712 device_printf(self, "clk %s (parent %s): ", clk->name, 713 clk_parent ? clk_parent->name : "none"); 714 printf("%u Hz\n", clk_get_rate(clk)); 715 } 716 #endif 717 } 718 719 static void 720 tegra210_car_init(struct tegra210_car_softc *sc) 721 { 722 tegra210_car_parent_init(sc); 723 tegra210_car_utmip_init(sc); 724 tegra210_car_xusb_init(sc); 725 tegra210_car_watchdog_init(sc); 726 } 727 728 static void 729 tegra210_car_parent_init(struct tegra210_car_softc *sc) 730 { 731 struct clk *clk, *clk_parent; 732 int error; 733 u_int n; 734 735 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 736 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 737 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 738 739 if (tegra210_init_parents[n].parent != NULL) { 740 clk_parent = clk_get(&sc->sc_clkdom, 741 tegra210_init_parents[n].parent); 742 KASSERT(clk_parent != NULL); 743 744 error = clk_set_parent(clk, clk_parent); 745 if (error) { 746 aprint_error_dev(sc->sc_dev, 747 "couldn't set '%s' parent to '%s': %d\n", 748 clk->name, clk_parent->name, error); 749 } 750 clk_put(clk_parent); 751 } 752 if (tegra210_init_parents[n].rate != 0) { 753 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 754 if (error) { 755 aprint_error_dev(sc->sc_dev, 756 "couldn't set '%s' rate to %u Hz: %d\n", 757 clk->name, tegra210_init_parents[n].rate, 758 error); 759 } 760 } 761 if (tegra210_init_parents[n].enable) { 762 error = clk_enable(clk); 763 if (error) { 764 aprint_error_dev(sc->sc_dev, 765 "couldn't enable '%s': %d\n", clk->name, 766 error); 767 } 768 } 769 clk_put(clk); 770 } 771 } 772 773 static void 774 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 775 { 776 bus_space_tag_t bst = sc->sc_bst; 777 bus_space_handle_t bsh = sc->sc_bsh; 778 779 /* 780 * Set up the UTMI PLL. 781 */ 782 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 783 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 784 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 785 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 786 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 787 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 788 delay(10); 789 /* TODO UTMIP_PLL_CFG0 */ 790 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 791 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 792 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 793 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 794 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 795 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 796 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 797 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 798 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 799 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 800 801 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 802 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 803 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 804 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 805 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 806 807 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 808 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 809 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 810 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 811 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 812 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 813 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 814 815 /* 816 * Set up UTMI PLL under hardware control 817 */ 818 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 819 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 820 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 821 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 822 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 823 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 824 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 825 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 826 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 827 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 828 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 829 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 830 delay(1); 831 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 832 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 833 } 834 835 static void 836 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 837 { 838 const bus_space_tag_t bst = sc->sc_bst; 839 const bus_space_handle_t bsh = sc->sc_bsh; 840 uint32_t val; 841 842 /* 843 * Set up the PLLU. 844 */ 845 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 846 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 847 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 848 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 849 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 850 delay(5); 851 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 852 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 853 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 854 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 855 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 856 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 857 do { 858 delay(2); 859 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 860 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 861 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 862 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 863 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 864 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 865 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 866 delay(2); 867 868 /* 869 * Now switch PLLU to hw controlled mode. 870 */ 871 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 872 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 873 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 874 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 875 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 876 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 877 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 878 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 879 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 880 delay(1); 881 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 882 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 883 delay(1); 884 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 885 886 /* 887 * Set up PLLREFE 888 */ 889 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 890 0, CAR_PLLREFE_MISC_IDDQ); 891 delay(5); 892 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 893 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 894 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 895 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 896 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 897 CAR_PLLREFE_BASE_DIVM | 898 CAR_PLLREFE_BASE_DIVN | 899 CAR_PLLREFE_BASE_DIVP | 900 CAR_PLLREFE_BASE_KCP); 901 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 902 CAR_PLLREFE_BASE_ENABLE, 0); 903 do { 904 delay(2); 905 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 906 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 907 908 /* 909 * Set up the PLLE. 910 */ 911 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 912 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 913 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 914 delay(5); 915 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 916 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 917 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 918 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 919 CAR_PLLE_BASE_DIVP_CML | 920 CAR_PLLE_BASE_DIVN | 921 CAR_PLLE_BASE_DIVM); 922 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 923 CAR_PLLE_MISC_PTS, 924 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 925 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 926 do { 927 delay(2); 928 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 929 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 930 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 931 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 932 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 933 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 934 CAR_PLLE_SS_CNTL_SSCINC | 935 CAR_PLLE_SS_CNTL_SSCINCINTRV | 936 CAR_PLLE_SS_CNTL_SSCMAX | 937 CAR_PLLE_SS_CNTL_SSCINVERT | 938 CAR_PLLE_SS_CNTL_SSCCENTER | 939 CAR_PLLE_SS_CNTL_BYPASS_SS | 940 CAR_PLLE_SS_CNTL_SSCBYP); 941 delay(1); 942 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 943 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 944 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 945 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 946 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 947 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 948 delay(1); 949 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 950 951 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 952 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 953 } 954 955 static void 956 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 957 { 958 const bus_space_tag_t bst = sc->sc_bst; 959 const bus_space_handle_t bsh = sc->sc_bsh; 960 961 /* Enable watchdog timer reset for system */ 962 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 963 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 964 } 965 966 static struct tegra_clk * 967 tegra210_car_clock_find(const char *name) 968 { 969 u_int n; 970 971 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 972 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 973 return &tegra210_car_clocks[n]; 974 } 975 } 976 977 return NULL; 978 } 979 980 static struct tegra_clk * 981 tegra210_car_clock_find_by_id(u_int clock_id) 982 { 983 u_int n; 984 985 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 986 if (tegra210_car_clock_ids[n].id == clock_id) { 987 const char *name = tegra210_car_clock_ids[n].name; 988 return tegra210_car_clock_find(name); 989 } 990 } 991 992 return NULL; 993 } 994 995 static struct clk * 996 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 997 { 998 struct tegra210_car_softc * const sc = device_private(dev); 999 struct tegra_clk *tclk; 1000 1001 if (len != sc->sc_clock_cells * 4) { 1002 return NULL; 1003 } 1004 1005 const u_int clock_id = be32dec(data); 1006 1007 tclk = tegra210_car_clock_find_by_id(clock_id); 1008 if (tclk) 1009 return TEGRA_CLK_BASE(tclk); 1010 1011 return NULL; 1012 } 1013 1014 static struct clk * 1015 tegra210_car_clock_get(void *priv, const char *name) 1016 { 1017 struct tegra_clk *tclk; 1018 1019 tclk = tegra210_car_clock_find(name); 1020 if (tclk == NULL) 1021 return NULL; 1022 1023 atomic_inc_uint(&tclk->refcnt); 1024 1025 return TEGRA_CLK_BASE(tclk); 1026 } 1027 1028 static void 1029 tegra210_car_clock_put(void *priv, struct clk *clk) 1030 { 1031 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1032 1033 KASSERT(tclk->refcnt > 0); 1034 1035 atomic_dec_uint(&tclk->refcnt); 1036 } 1037 1038 static u_int 1039 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1040 struct tegra_clk *tclk) 1041 { 1042 struct tegra_pll_clk *tpll = &tclk->u.pll; 1043 struct tegra_clk *tclk_parent; 1044 bus_space_tag_t bst = sc->sc_bst; 1045 bus_space_handle_t bsh = sc->sc_bsh; 1046 u_int divm, divn, divp; 1047 uint64_t rate; 1048 1049 KASSERT(tclk->type == TEGRA_CLK_PLL); 1050 1051 tclk_parent = tegra210_car_clock_find(tclk->parent); 1052 KASSERT(tclk_parent != NULL); 1053 1054 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1055 TEGRA_CLK_BASE(tclk_parent)); 1056 1057 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1058 divm = __SHIFTOUT(base, tpll->divm_mask); 1059 divn = __SHIFTOUT(base, tpll->divn_mask); 1060 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1061 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1062 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1063 /* XXX divp is not applied to PLLP's primary output */ 1064 divp = 0; 1065 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1066 divp = 0; 1067 divm *= __SHIFTOUT(base, tpll->divp_mask); 1068 } else { 1069 divp = __SHIFTOUT(base, tpll->divp_mask); 1070 } 1071 1072 rate = (uint64_t)rate_parent * divn; 1073 return rate / (divm << divp); 1074 } 1075 1076 static int 1077 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1078 struct tegra_clk *tclk, u_int rate) 1079 { 1080 struct tegra_pll_clk *tpll = &tclk->u.pll; 1081 bus_space_tag_t bst = sc->sc_bst; 1082 bus_space_handle_t bsh = sc->sc_bsh; 1083 struct clk *clk_parent; 1084 uint32_t bp, base; 1085 1086 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1087 if (clk_parent == NULL) 1088 return EIO; 1089 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1090 if (rate_parent == 0) 1091 return EIO; 1092 1093 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1094 const u_int divm = 1; 1095 const u_int divn = rate / rate_parent; 1096 const u_int divp = 0; 1097 1098 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1099 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1100 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1101 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1102 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1103 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1104 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1105 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1106 1107 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1108 base &= ~CAR_PLLX_BASE_DIVM; 1109 base &= ~CAR_PLLX_BASE_DIVN; 1110 base &= ~CAR_PLLX_BASE_DIVP; 1111 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1112 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1113 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1114 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1115 1116 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1117 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1118 do { 1119 delay(2); 1120 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1121 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1122 delay(100); 1123 1124 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1125 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1126 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1127 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1128 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1129 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1130 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1131 1132 return 0; 1133 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1134 const u_int divm = 1; 1135 const u_int pldiv = 1; 1136 const u_int divn = (rate << pldiv) / rate_parent; 1137 1138 /* Set frequency */ 1139 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1140 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1141 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1142 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1143 CAR_PLLD2_BASE_REF_SRC_SEL | 1144 CAR_PLLD2_BASE_DIVM | 1145 CAR_PLLD2_BASE_DIVN | 1146 CAR_PLLD2_BASE_DIVP); 1147 1148 return 0; 1149 } else { 1150 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1151 tclk->base.name, rate); 1152 /* TODO */ 1153 return EOPNOTSUPP; 1154 } 1155 } 1156 1157 static int 1158 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1159 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1160 { 1161 struct tegra_mux_clk *tmux = &tclk->u.mux; 1162 bus_space_tag_t bst = sc->sc_bst; 1163 bus_space_handle_t bsh = sc->sc_bsh; 1164 uint32_t v; 1165 u_int src; 1166 1167 KASSERT(tclk->type == TEGRA_CLK_MUX); 1168 1169 for (src = 0; src < tmux->nparents; src++) { 1170 if (tmux->parents[src] == NULL) { 1171 continue; 1172 } 1173 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1174 break; 1175 } 1176 } 1177 if (src == tmux->nparents) { 1178 return EINVAL; 1179 } 1180 1181 v = bus_space_read_4(bst, bsh, tmux->reg); 1182 v &= ~tmux->bits; 1183 v |= __SHIFTIN(src, tmux->bits); 1184 bus_space_write_4(bst, bsh, tmux->reg, v); 1185 1186 return 0; 1187 } 1188 1189 static struct tegra_clk * 1190 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1191 struct tegra_clk *tclk) 1192 { 1193 struct tegra_mux_clk *tmux = &tclk->u.mux; 1194 bus_space_tag_t bst = sc->sc_bst; 1195 bus_space_handle_t bsh = sc->sc_bsh; 1196 1197 KASSERT(tclk->type == TEGRA_CLK_MUX); 1198 1199 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1200 const u_int src = __SHIFTOUT(v, tmux->bits); 1201 1202 KASSERT(src < tmux->nparents); 1203 1204 if (tmux->parents[src] == NULL) { 1205 return NULL; 1206 } 1207 1208 return tegra210_car_clock_find(tmux->parents[src]); 1209 } 1210 1211 static u_int 1212 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1213 struct tegra_clk *tclk) 1214 { 1215 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1216 struct clk *clk_parent; 1217 1218 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1219 if (clk_parent == NULL) 1220 return 0; 1221 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1222 1223 return parent_rate / tfixed_div->div; 1224 } 1225 1226 static u_int 1227 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1228 struct tegra_clk *tclk) 1229 { 1230 struct tegra_div_clk *tdiv = &tclk->u.div; 1231 bus_space_tag_t bst = sc->sc_bst; 1232 bus_space_handle_t bsh = sc->sc_bsh; 1233 struct clk *clk_parent; 1234 u_int rate; 1235 1236 KASSERT(tclk->type == TEGRA_CLK_DIV); 1237 1238 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1239 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1240 1241 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1242 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1243 1244 switch (tdiv->reg) { 1245 case CAR_CLKSRC_I2C1_REG: 1246 case CAR_CLKSRC_I2C2_REG: 1247 case CAR_CLKSRC_I2C3_REG: 1248 case CAR_CLKSRC_I2C4_REG: 1249 case CAR_CLKSRC_I2C5_REG: 1250 case CAR_CLKSRC_I2C6_REG: 1251 rate = parent_rate / (raw_div + 1); 1252 break; 1253 case CAR_CLKSRC_UARTA_REG: 1254 case CAR_CLKSRC_UARTB_REG: 1255 case CAR_CLKSRC_UARTC_REG: 1256 case CAR_CLKSRC_UARTD_REG: 1257 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1258 rate = parent_rate / ((raw_div / 2) + 1); 1259 } else { 1260 rate = parent_rate; 1261 } 1262 break; 1263 case CAR_CLKSRC_SDMMC2_REG: 1264 case CAR_CLKSRC_SDMMC4_REG: 1265 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1266 case 1: 1267 case 2: 1268 case 5: 1269 raw_div = 0; /* ignore divisor for _LJ options */ 1270 break; 1271 } 1272 /* FALLTHROUGH */ 1273 default: 1274 rate = parent_rate / ((raw_div / 2) + 1); 1275 break; 1276 } 1277 1278 return rate; 1279 } 1280 1281 static int 1282 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1283 struct tegra_clk *tclk, u_int rate) 1284 { 1285 struct tegra_div_clk *tdiv = &tclk->u.div; 1286 bus_space_tag_t bst = sc->sc_bst; 1287 bus_space_handle_t bsh = sc->sc_bsh; 1288 struct clk *clk_parent; 1289 u_int raw_div; 1290 uint32_t v; 1291 1292 KASSERT(tclk->type == TEGRA_CLK_DIV); 1293 1294 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1295 if (clk_parent == NULL) 1296 return EINVAL; 1297 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1298 1299 v = bus_space_read_4(bst, bsh, tdiv->reg); 1300 1301 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1302 1303 switch (tdiv->reg) { 1304 case CAR_CLKSRC_UARTA_REG: 1305 case CAR_CLKSRC_UARTB_REG: 1306 case CAR_CLKSRC_UARTC_REG: 1307 case CAR_CLKSRC_UARTD_REG: 1308 if (rate == parent_rate) { 1309 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1310 } else if (rate) { 1311 v |= CAR_CLKSRC_UART_DIV_ENB; 1312 raw_div = (parent_rate / rate) * 2; 1313 if (raw_div >= 2) 1314 raw_div -= 2; 1315 } 1316 break; 1317 case CAR_CLKSRC_I2C1_REG: 1318 case CAR_CLKSRC_I2C2_REG: 1319 case CAR_CLKSRC_I2C3_REG: 1320 case CAR_CLKSRC_I2C4_REG: 1321 case CAR_CLKSRC_I2C5_REG: 1322 case CAR_CLKSRC_I2C6_REG: 1323 if (rate) 1324 raw_div = (parent_rate / rate) - 1; 1325 break; 1326 case CAR_CLKSRC_SDMMC1_REG: 1327 case CAR_CLKSRC_SDMMC2_REG: 1328 case CAR_CLKSRC_SDMMC3_REG: 1329 case CAR_CLKSRC_SDMMC4_REG: 1330 if (rate) { 1331 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1332 u_int calc_rate = 1333 parent_rate / ((raw_div / 2) + 1); 1334 if (calc_rate <= rate) 1335 break; 1336 } 1337 if (raw_div == 0x100) 1338 return EINVAL; 1339 } 1340 break; 1341 default: 1342 if (rate) { 1343 raw_div = (parent_rate / rate) * 2; 1344 if (raw_div >= 2) 1345 raw_div -= 2; 1346 } 1347 break; 1348 } 1349 1350 v &= ~tdiv->bits; 1351 v |= __SHIFTIN(raw_div, tdiv->bits); 1352 1353 bus_space_write_4(bst, bsh, tdiv->reg, v); 1354 1355 return 0; 1356 } 1357 1358 static int 1359 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1360 struct tegra_clk *tclk, bool enable) 1361 { 1362 struct tegra_gate_clk *tgate = &tclk->u.gate; 1363 bus_space_tag_t bst = sc->sc_bst; 1364 bus_space_handle_t bsh = sc->sc_bsh; 1365 bus_size_t reg; 1366 1367 KASSERT(tclk->type == TEGRA_CLK_GATE); 1368 1369 if (tgate->set_reg == tgate->clr_reg) { 1370 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1371 if (enable) { 1372 v |= tgate->bits; 1373 } else { 1374 v &= ~tgate->bits; 1375 } 1376 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1377 } else { 1378 if (enable) { 1379 reg = tgate->set_reg; 1380 } else { 1381 reg = tgate->clr_reg; 1382 } 1383 bus_space_write_4(bst, bsh, reg, tgate->bits); 1384 } 1385 1386 return 0; 1387 } 1388 1389 static u_int 1390 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1391 { 1392 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1393 struct clk *clk_parent; 1394 1395 switch (tclk->type) { 1396 case TEGRA_CLK_FIXED: 1397 return tclk->u.fixed.rate; 1398 case TEGRA_CLK_PLL: 1399 return tegra210_car_clock_get_rate_pll(priv, tclk); 1400 case TEGRA_CLK_MUX: 1401 case TEGRA_CLK_GATE: 1402 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1403 if (clk_parent == NULL) 1404 return EINVAL; 1405 return tegra210_car_clock_get_rate(priv, clk_parent); 1406 case TEGRA_CLK_FIXED_DIV: 1407 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1408 case TEGRA_CLK_DIV: 1409 return tegra210_car_clock_get_rate_div(priv, tclk); 1410 default: 1411 panic("tegra210: unknown tclk type %d", tclk->type); 1412 } 1413 } 1414 1415 static int 1416 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1417 { 1418 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1419 struct clk *clk_parent; 1420 1421 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1422 1423 switch (tclk->type) { 1424 case TEGRA_CLK_FIXED: 1425 case TEGRA_CLK_MUX: 1426 return EIO; 1427 case TEGRA_CLK_FIXED_DIV: 1428 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1429 if (clk_parent == NULL) 1430 return EIO; 1431 return tegra210_car_clock_set_rate(priv, clk_parent, 1432 rate * tclk->u.fixed_div.div); 1433 case TEGRA_CLK_GATE: 1434 return EINVAL; 1435 case TEGRA_CLK_PLL: 1436 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1437 case TEGRA_CLK_DIV: 1438 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1439 default: 1440 panic("tegra210: unknown tclk type %d", tclk->type); 1441 } 1442 } 1443 1444 static int 1445 tegra210_car_clock_enable(void *priv, struct clk *clk) 1446 { 1447 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1448 struct clk *clk_parent; 1449 1450 if (tclk->type != TEGRA_CLK_GATE) { 1451 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1452 if (clk_parent == NULL) 1453 return 0; 1454 return tegra210_car_clock_enable(priv, clk_parent); 1455 } 1456 1457 return tegra210_car_clock_enable_gate(priv, tclk, true); 1458 } 1459 1460 static int 1461 tegra210_car_clock_disable(void *priv, struct clk *clk) 1462 { 1463 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1464 1465 if (tclk->type != TEGRA_CLK_GATE) 1466 return EINVAL; 1467 1468 return tegra210_car_clock_enable_gate(priv, tclk, false); 1469 } 1470 1471 static int 1472 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1473 struct clk *clk_parent) 1474 { 1475 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1476 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1477 struct clk *nclk_parent; 1478 1479 if (tclk->type != TEGRA_CLK_MUX) { 1480 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1481 if (nclk_parent == clk_parent || nclk_parent == NULL) 1482 return EINVAL; 1483 return tegra210_car_clock_set_parent(priv, nclk_parent, 1484 clk_parent); 1485 } 1486 1487 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1488 } 1489 1490 static struct clk * 1491 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1492 { 1493 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1494 struct tegra_clk *tclk_parent = NULL; 1495 1496 switch (tclk->type) { 1497 case TEGRA_CLK_FIXED: 1498 case TEGRA_CLK_PLL: 1499 case TEGRA_CLK_FIXED_DIV: 1500 case TEGRA_CLK_DIV: 1501 case TEGRA_CLK_GATE: 1502 if (tclk->parent) { 1503 tclk_parent = tegra210_car_clock_find(tclk->parent); 1504 } 1505 break; 1506 case TEGRA_CLK_MUX: 1507 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1508 break; 1509 } 1510 1511 if (tclk_parent == NULL) 1512 return NULL; 1513 1514 return TEGRA_CLK_BASE(tclk_parent); 1515 } 1516 1517 static void * 1518 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1519 { 1520 struct tegra210_car_softc * const sc = device_private(dev); 1521 struct tegra210_car_rst *rst; 1522 1523 if (len != sc->sc_reset_cells * 4) 1524 return NULL; 1525 1526 const u_int reset_id = be32dec(data); 1527 1528 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1529 return NULL; 1530 1531 const u_int reg = reset_id / 32; 1532 1533 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1534 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1535 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1536 rst->mask = __BIT(reset_id % 32); 1537 1538 return rst; 1539 } 1540 1541 static void 1542 tegra210_car_reset_release(device_t dev, void *priv) 1543 { 1544 struct tegra210_car_rst *rst = priv; 1545 1546 kmem_free(rst, sizeof(*rst)); 1547 } 1548 1549 static int 1550 tegra210_car_reset_assert(device_t dev, void *priv) 1551 { 1552 struct tegra210_car_softc * const sc = device_private(dev); 1553 struct tegra210_car_rst *rst = priv; 1554 1555 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1556 1557 return 0; 1558 } 1559 1560 static int 1561 tegra210_car_reset_deassert(device_t dev, void *priv) 1562 { 1563 struct tegra210_car_softc * const sc = device_private(dev); 1564 struct tegra210_car_rst *rst = priv; 1565 1566 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1567 1568 return 0; 1569 } 1570 1571 void 1572 tegra210_car_xusbio_enable_hw_control(void) 1573 { 1574 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1575 KASSERT(dev != NULL); 1576 struct tegra210_car_softc * const sc = device_private(dev); 1577 bus_space_tag_t bst = sc->sc_bst; 1578 bus_space_handle_t bsh = sc->sc_bsh; 1579 1580 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1581 0, 1582 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1583 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1584 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1585 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1586 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1587 0); 1588 } 1589 1590 void 1591 tegra210_car_xusbio_enable_hw_seq(void) 1592 { 1593 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1594 KASSERT(dev != NULL); 1595 struct tegra210_car_softc * const sc = device_private(dev); 1596 bus_space_tag_t bst = sc->sc_bst; 1597 bus_space_handle_t bsh = sc->sc_bsh; 1598 1599 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1600 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1601 } 1602
Indexes created Thu Oct 30 16:09:53 GMT 2025