tegra210_car.c revision 1.13
1 /* $NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static const char *mux_mselect_p[] = 440 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT2", 441 "PLL_C4_OUT1", "CLK_S", "CLK_M", "PLL_C4_OUT0" }; 442 443 static struct tegra_clk tegra210_car_clocks[] = { 444 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 445 446 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 447 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 448 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 449 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 450 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 451 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 452 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 453 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 454 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 455 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 456 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 457 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 458 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 459 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 460 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 461 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 462 463 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 464 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 465 466 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 469 mux_uart_p), 470 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 471 mux_uart_p), 472 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 473 mux_uart_p), 474 475 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 476 mux_sdmmc1_p), 477 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 478 mux_sdmmc2_4_p), 479 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 480 mux_sdmmc3_p), 481 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 482 mux_sdmmc2_4_p), 483 484 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 487 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 488 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 489 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 490 491 CLK_MUX("MUX_XUSB_HOST", 492 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 493 mux_xusb_host_p), 494 CLK_MUX("MUX_XUSB_FALCON", 495 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 496 mux_xusb_host_p), 497 CLK_MUX("MUX_XUSB_SS", 498 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 499 mux_xusb_ss_p), 500 CLK_MUX("MUX_XUSB_FS", 501 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 502 mux_xusb_fs_p), 503 504 CLK_MUX("MUX_MSELECT", 505 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 506 mux_mselect_p), 507 508 CLK_DIV("DIV_UARTA", "MUX_UARTA", 509 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 510 CLK_DIV("DIV_UARTB", "MUX_UARTB", 511 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 512 CLK_DIV("DIV_UARTC", "MUX_UARTC", 513 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 514 CLK_DIV("DIV_UARTD", "MUX_UARTD", 515 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 516 517 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 518 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 519 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 520 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 521 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 522 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 523 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 524 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 525 526 CLK_DIV("DIV_I2C1", "MUX_I2C1", 527 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 528 CLK_DIV("DIV_I2C2", "MUX_I2C2", 529 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 530 CLK_DIV("DIV_I2C3", "MUX_I2C3", 531 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 532 CLK_DIV("DIV_I2C4", "MUX_I2C4", 533 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 534 CLK_DIV("DIV_I2C5", "MUX_I2C5", 535 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 536 CLK_DIV("DIV_I2C6", "MUX_I2C6", 537 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 538 539 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 540 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 541 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 542 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 543 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 544 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 545 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 546 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 547 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 548 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 549 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 550 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 551 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 552 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 553 554 CLK_DIV("DIV_MSELECT", "MUX_MSELECT", 555 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 556 557 CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 558 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 559 CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 560 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 561 562 CLK_GATE("CML0", "PLL_E", 563 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 564 CLK_GATE("CML1", "PLL_E", 565 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 566 567 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 568 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 569 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 570 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 571 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 572 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 573 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 574 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 575 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 576 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 577 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 578 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 579 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 580 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 581 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 582 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 583 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 584 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 585 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 586 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 587 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 588 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 589 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 590 CLK_GATE_V("MSELECT", "DIV_MSELECT", CAR_DEV_V_MSELECT), 591 CLK_GATE_U("PCIE", "CLK_M", CAR_DEV_U_PCIE), 592 CLK_GATE_U("AFI", "MSELECT", CAR_DEV_U_AFI), 593 }; 594 595 struct tegra210_init_parent { 596 const char *clock; 597 const char *parent; 598 u_int rate; 599 u_int enable; 600 } tegra210_init_parents[] = { 601 { "SDMMC1", "PLL_P", 0, 0 }, 602 { "SDMMC2", "PLL_P", 0, 0 }, 603 { "SDMMC3", "PLL_P", 0, 0 }, 604 { "SDMMC4", "PLL_P", 0, 0 }, 605 { "XUSB_GATE", NULL, 0, 1 }, 606 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 607 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 608 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 609 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 610 { "PLL_U_OUT1", NULL, 48000000, 1 }, 611 { "PLL_U_OUT2", NULL, 60000000, 1 }, 612 }; 613 614 struct tegra210_car_rst { 615 u_int set_reg; 616 u_int clr_reg; 617 u_int mask; 618 }; 619 620 static struct tegra210_car_reset_reg { 621 u_int set_reg; 622 u_int clr_reg; 623 } tegra210_car_reset_regs[] = { 624 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 625 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 626 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 627 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 628 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 629 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 630 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 631 }; 632 633 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 634 static void tegra210_car_reset_release(device_t, void *); 635 static int tegra210_car_reset_assert(device_t, void *); 636 static int tegra210_car_reset_deassert(device_t, void *); 637 638 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 639 .acquire = tegra210_car_reset_acquire, 640 .release = tegra210_car_reset_release, 641 .reset_assert = tegra210_car_reset_assert, 642 .reset_deassert = tegra210_car_reset_deassert, 643 }; 644 645 struct tegra210_car_softc { 646 device_t sc_dev; 647 bus_space_tag_t sc_bst; 648 bus_space_handle_t sc_bsh; 649 650 struct clk_domain sc_clkdom; 651 652 u_int sc_clock_cells; 653 u_int sc_reset_cells; 654 655 kmutex_t sc_rndlock; 656 krndsource_t sc_rndsource; 657 }; 658 659 static void tegra210_car_init(struct tegra210_car_softc *); 660 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 661 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 662 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 663 static void tegra210_car_parent_init(struct tegra210_car_softc *); 664 665 666 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 667 tegra210_car_match, tegra210_car_attach, NULL, NULL); 668 669 static int 670 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 671 { 672 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 673 struct fdt_attach_args * const faa = aux; 674 675 #if 0 676 return of_match_compatible(faa->faa_phandle, compatible); 677 #else 678 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 679 return 0; 680 681 return 999; 682 #endif 683 } 684 685 static void 686 tegra210_car_attach(device_t parent, device_t self, void *aux) 687 { 688 struct tegra210_car_softc * const sc = device_private(self); 689 struct fdt_attach_args * const faa = aux; 690 const int phandle = faa->faa_phandle; 691 bus_addr_t addr; 692 bus_size_t size; 693 int error, n; 694 695 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 696 aprint_error(": couldn't get registers\n"); 697 return; 698 } 699 700 sc->sc_dev = self; 701 sc->sc_bst = faa->faa_bst; 702 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 703 if (error) { 704 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 705 return; 706 } 707 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 708 sc->sc_clock_cells = 1; 709 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 710 sc->sc_reset_cells = 1; 711 712 aprint_naive("\n"); 713 aprint_normal(": CAR\n"); 714 715 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 716 sc->sc_clkdom.priv = sc; 717 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 718 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 719 720 fdtbus_register_clock_controller(self, phandle, 721 &tegra210_car_fdtclock_funcs); 722 fdtbus_register_reset_controller(self, phandle, 723 &tegra210_car_fdtreset_funcs); 724 725 tegra210_car_init(sc); 726 727 #ifdef TEGRA210_CAR_DEBUG 728 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 729 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 730 struct clk *clk_parent = clk_get_parent(clk); 731 device_printf(self, "clk %s (parent %s): ", clk->name, 732 clk_parent ? clk_parent->name : "none"); 733 printf("%u Hz\n", clk_get_rate(clk)); 734 } 735 #endif 736 } 737 738 static void 739 tegra210_car_init(struct tegra210_car_softc *sc) 740 { 741 tegra210_car_parent_init(sc); 742 tegra210_car_utmip_init(sc); 743 tegra210_car_xusb_init(sc); 744 tegra210_car_watchdog_init(sc); 745 } 746 747 static void 748 tegra210_car_parent_init(struct tegra210_car_softc *sc) 749 { 750 struct clk *clk, *clk_parent; 751 int error; 752 u_int n; 753 754 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 755 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 756 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 757 758 if (tegra210_init_parents[n].parent != NULL) { 759 clk_parent = clk_get(&sc->sc_clkdom, 760 tegra210_init_parents[n].parent); 761 KASSERT(clk_parent != NULL); 762 763 error = clk_set_parent(clk, clk_parent); 764 if (error) { 765 aprint_error_dev(sc->sc_dev, 766 "couldn't set '%s' parent to '%s': %d\n", 767 clk->name, clk_parent->name, error); 768 } 769 clk_put(clk_parent); 770 } 771 if (tegra210_init_parents[n].rate != 0) { 772 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 773 if (error) { 774 aprint_error_dev(sc->sc_dev, 775 "couldn't set '%s' rate to %u Hz: %d\n", 776 clk->name, tegra210_init_parents[n].rate, 777 error); 778 } 779 } 780 if (tegra210_init_parents[n].enable) { 781 error = clk_enable(clk); 782 if (error) { 783 aprint_error_dev(sc->sc_dev, 784 "couldn't enable '%s': %d\n", clk->name, 785 error); 786 } 787 } 788 clk_put(clk); 789 } 790 } 791 792 static void 793 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 794 { 795 bus_space_tag_t bst = sc->sc_bst; 796 bus_space_handle_t bsh = sc->sc_bsh; 797 798 /* 799 * Set up the UTMI PLL. 800 */ 801 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 802 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 803 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 804 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 805 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 806 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 807 delay(10); 808 /* TODO UTMIP_PLL_CFG0 */ 809 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 810 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 811 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 812 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 813 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 814 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 815 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 816 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 817 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 818 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 819 820 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 821 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 822 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 823 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 824 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 825 826 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 827 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 828 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 829 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 830 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 831 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 832 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 833 834 /* 835 * Set up UTMI PLL under hardware control 836 */ 837 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 838 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 839 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 840 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 841 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 842 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 843 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 844 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 845 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 846 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 847 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 848 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 849 delay(1); 850 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 851 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 852 } 853 854 static void 855 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 856 { 857 const bus_space_tag_t bst = sc->sc_bst; 858 const bus_space_handle_t bsh = sc->sc_bsh; 859 uint32_t val; 860 861 /* 862 * Set up the PLLU. 863 */ 864 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 865 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 866 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 867 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 868 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 869 delay(5); 870 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 871 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 872 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 873 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 874 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 875 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 876 do { 877 delay(2); 878 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 879 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 880 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 881 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 882 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 883 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 884 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 885 delay(2); 886 887 /* 888 * Now switch PLLU to hw controlled mode. 889 */ 890 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 891 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 892 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 893 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 894 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 895 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 896 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 897 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 898 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 899 delay(1); 900 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 901 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 902 delay(1); 903 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 904 905 /* 906 * Set up PLLREFE 907 */ 908 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 909 0, CAR_PLLREFE_MISC_IDDQ); 910 delay(5); 911 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 912 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 913 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 914 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 915 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 916 CAR_PLLREFE_BASE_DIVM | 917 CAR_PLLREFE_BASE_DIVN | 918 CAR_PLLREFE_BASE_DIVP | 919 CAR_PLLREFE_BASE_KCP); 920 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 921 CAR_PLLREFE_BASE_ENABLE, 0); 922 do { 923 delay(2); 924 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 925 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 926 927 /* 928 * Set up the PLLE. 929 */ 930 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 931 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 932 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 933 delay(5); 934 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 935 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 936 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 937 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 938 CAR_PLLE_BASE_DIVP_CML | 939 CAR_PLLE_BASE_DIVN | 940 CAR_PLLE_BASE_DIVM); 941 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 942 CAR_PLLE_MISC_PTS, 943 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 944 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 945 do { 946 delay(2); 947 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 948 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 949 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 950 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 951 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 952 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 953 CAR_PLLE_SS_CNTL_SSCINC | 954 CAR_PLLE_SS_CNTL_SSCINCINTRV | 955 CAR_PLLE_SS_CNTL_SSCMAX | 956 CAR_PLLE_SS_CNTL_SSCINVERT | 957 CAR_PLLE_SS_CNTL_SSCCENTER | 958 CAR_PLLE_SS_CNTL_BYPASS_SS | 959 CAR_PLLE_SS_CNTL_SSCBYP); 960 delay(1); 961 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 962 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 963 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 964 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 965 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 966 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 967 delay(1); 968 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 969 970 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 971 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 972 } 973 974 static void 975 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 976 { 977 const bus_space_tag_t bst = sc->sc_bst; 978 const bus_space_handle_t bsh = sc->sc_bsh; 979 980 /* Enable watchdog timer reset for system */ 981 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 982 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 983 } 984 985 static struct tegra_clk * 986 tegra210_car_clock_find(const char *name) 987 { 988 u_int n; 989 990 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 991 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 992 return &tegra210_car_clocks[n]; 993 } 994 } 995 996 return NULL; 997 } 998 999 static struct tegra_clk * 1000 tegra210_car_clock_find_by_id(u_int clock_id) 1001 { 1002 u_int n; 1003 1004 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 1005 if (tegra210_car_clock_ids[n].id == clock_id) { 1006 const char *name = tegra210_car_clock_ids[n].name; 1007 return tegra210_car_clock_find(name); 1008 } 1009 } 1010 1011 return NULL; 1012 } 1013 1014 static struct clk * 1015 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 1016 { 1017 struct tegra210_car_softc * const sc = device_private(dev); 1018 struct tegra_clk *tclk; 1019 1020 if (len != sc->sc_clock_cells * 4) { 1021 return NULL; 1022 } 1023 1024 const u_int clock_id = be32dec(data); 1025 1026 tclk = tegra210_car_clock_find_by_id(clock_id); 1027 if (tclk) 1028 return TEGRA_CLK_BASE(tclk); 1029 1030 return NULL; 1031 } 1032 1033 static struct clk * 1034 tegra210_car_clock_get(void *priv, const char *name) 1035 { 1036 struct tegra_clk *tclk; 1037 1038 tclk = tegra210_car_clock_find(name); 1039 if (tclk == NULL) 1040 return NULL; 1041 1042 atomic_inc_uint(&tclk->refcnt); 1043 1044 return TEGRA_CLK_BASE(tclk); 1045 } 1046 1047 static void 1048 tegra210_car_clock_put(void *priv, struct clk *clk) 1049 { 1050 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1051 1052 KASSERT(tclk->refcnt > 0); 1053 1054 atomic_dec_uint(&tclk->refcnt); 1055 } 1056 1057 static u_int 1058 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1059 struct tegra_clk *tclk) 1060 { 1061 struct tegra_pll_clk *tpll = &tclk->u.pll; 1062 struct tegra_clk *tclk_parent; 1063 bus_space_tag_t bst = sc->sc_bst; 1064 bus_space_handle_t bsh = sc->sc_bsh; 1065 u_int divm, divn, divp; 1066 uint64_t rate; 1067 1068 KASSERT(tclk->type == TEGRA_CLK_PLL); 1069 1070 tclk_parent = tegra210_car_clock_find(tclk->parent); 1071 KASSERT(tclk_parent != NULL); 1072 1073 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1074 TEGRA_CLK_BASE(tclk_parent)); 1075 1076 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1077 divm = __SHIFTOUT(base, tpll->divm_mask); 1078 divn = __SHIFTOUT(base, tpll->divn_mask); 1079 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1080 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1081 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1082 /* XXX divp is not applied to PLLP's primary output */ 1083 divp = 0; 1084 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1085 divp = 0; 1086 divm *= __SHIFTOUT(base, tpll->divp_mask); 1087 } else { 1088 divp = __SHIFTOUT(base, tpll->divp_mask); 1089 } 1090 1091 rate = (uint64_t)rate_parent * divn; 1092 return rate / (divm << divp); 1093 } 1094 1095 static int 1096 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1097 struct tegra_clk *tclk, u_int rate) 1098 { 1099 struct tegra_pll_clk *tpll = &tclk->u.pll; 1100 bus_space_tag_t bst = sc->sc_bst; 1101 bus_space_handle_t bsh = sc->sc_bsh; 1102 struct clk *clk_parent; 1103 uint32_t bp, base; 1104 1105 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1106 if (clk_parent == NULL) 1107 return EIO; 1108 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1109 if (rate_parent == 0) 1110 return EIO; 1111 1112 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1113 const u_int divm = 1; 1114 const u_int divn = rate / rate_parent; 1115 const u_int divp = 0; 1116 1117 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1118 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1119 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1120 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1121 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1122 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1123 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1124 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1125 1126 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1127 base &= ~CAR_PLLX_BASE_DIVM; 1128 base &= ~CAR_PLLX_BASE_DIVN; 1129 base &= ~CAR_PLLX_BASE_DIVP; 1130 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1131 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1132 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1133 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1134 1135 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1136 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1137 do { 1138 delay(2); 1139 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1140 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1141 delay(100); 1142 1143 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1144 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1145 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1146 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1147 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1148 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1149 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1150 1151 return 0; 1152 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1153 const u_int divm = 1; 1154 const u_int pldiv = 1; 1155 const u_int divn = (rate << pldiv) / rate_parent; 1156 1157 /* Set frequency */ 1158 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1159 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1160 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1161 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1162 CAR_PLLD2_BASE_REF_SRC_SEL | 1163 CAR_PLLD2_BASE_DIVM | 1164 CAR_PLLD2_BASE_DIVN | 1165 CAR_PLLD2_BASE_DIVP); 1166 1167 return 0; 1168 } else { 1169 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1170 tclk->base.name, rate); 1171 /* TODO */ 1172 return EOPNOTSUPP; 1173 } 1174 } 1175 1176 static int 1177 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1178 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1179 { 1180 struct tegra_mux_clk *tmux = &tclk->u.mux; 1181 bus_space_tag_t bst = sc->sc_bst; 1182 bus_space_handle_t bsh = sc->sc_bsh; 1183 uint32_t v; 1184 u_int src; 1185 1186 KASSERT(tclk->type == TEGRA_CLK_MUX); 1187 1188 for (src = 0; src < tmux->nparents; src++) { 1189 if (tmux->parents[src] == NULL) { 1190 continue; 1191 } 1192 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1193 break; 1194 } 1195 } 1196 if (src == tmux->nparents) { 1197 return EINVAL; 1198 } 1199 1200 v = bus_space_read_4(bst, bsh, tmux->reg); 1201 v &= ~tmux->bits; 1202 v |= __SHIFTIN(src, tmux->bits); 1203 bus_space_write_4(bst, bsh, tmux->reg, v); 1204 1205 return 0; 1206 } 1207 1208 static struct tegra_clk * 1209 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1210 struct tegra_clk *tclk) 1211 { 1212 struct tegra_mux_clk *tmux = &tclk->u.mux; 1213 bus_space_tag_t bst = sc->sc_bst; 1214 bus_space_handle_t bsh = sc->sc_bsh; 1215 1216 KASSERT(tclk->type == TEGRA_CLK_MUX); 1217 1218 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1219 const u_int src = __SHIFTOUT(v, tmux->bits); 1220 1221 KASSERT(src < tmux->nparents); 1222 1223 if (tmux->parents[src] == NULL) { 1224 return NULL; 1225 } 1226 1227 return tegra210_car_clock_find(tmux->parents[src]); 1228 } 1229 1230 static u_int 1231 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1232 struct tegra_clk *tclk) 1233 { 1234 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1235 struct clk *clk_parent; 1236 1237 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1238 if (clk_parent == NULL) 1239 return 0; 1240 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1241 1242 return parent_rate / tfixed_div->div; 1243 } 1244 1245 static u_int 1246 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1247 struct tegra_clk *tclk) 1248 { 1249 struct tegra_div_clk *tdiv = &tclk->u.div; 1250 bus_space_tag_t bst = sc->sc_bst; 1251 bus_space_handle_t bsh = sc->sc_bsh; 1252 struct clk *clk_parent; 1253 u_int rate; 1254 1255 KASSERT(tclk->type == TEGRA_CLK_DIV); 1256 1257 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1258 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1259 1260 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1261 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1262 1263 switch (tdiv->reg) { 1264 case CAR_CLKSRC_I2C1_REG: 1265 case CAR_CLKSRC_I2C2_REG: 1266 case CAR_CLKSRC_I2C3_REG: 1267 case CAR_CLKSRC_I2C4_REG: 1268 case CAR_CLKSRC_I2C5_REG: 1269 case CAR_CLKSRC_I2C6_REG: 1270 rate = parent_rate / (raw_div + 1); 1271 break; 1272 case CAR_CLKSRC_UARTA_REG: 1273 case CAR_CLKSRC_UARTB_REG: 1274 case CAR_CLKSRC_UARTC_REG: 1275 case CAR_CLKSRC_UARTD_REG: 1276 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1277 rate = parent_rate / ((raw_div / 2) + 1); 1278 } else { 1279 rate = parent_rate; 1280 } 1281 break; 1282 case CAR_CLKSRC_SDMMC2_REG: 1283 case CAR_CLKSRC_SDMMC4_REG: 1284 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1285 case 1: 1286 case 2: 1287 case 5: 1288 raw_div = 0; /* ignore divisor for _LJ options */ 1289 break; 1290 } 1291 /* FALLTHROUGH */ 1292 default: 1293 rate = parent_rate / ((raw_div / 2) + 1); 1294 break; 1295 } 1296 1297 return rate; 1298 } 1299 1300 static int 1301 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1302 struct tegra_clk *tclk, u_int rate) 1303 { 1304 struct tegra_div_clk *tdiv = &tclk->u.div; 1305 bus_space_tag_t bst = sc->sc_bst; 1306 bus_space_handle_t bsh = sc->sc_bsh; 1307 struct clk *clk_parent; 1308 u_int raw_div; 1309 uint32_t v; 1310 1311 KASSERT(tclk->type == TEGRA_CLK_DIV); 1312 1313 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1314 if (clk_parent == NULL) 1315 return EINVAL; 1316 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1317 1318 v = bus_space_read_4(bst, bsh, tdiv->reg); 1319 1320 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1321 1322 switch (tdiv->reg) { 1323 case CAR_CLKSRC_UARTA_REG: 1324 case CAR_CLKSRC_UARTB_REG: 1325 case CAR_CLKSRC_UARTC_REG: 1326 case CAR_CLKSRC_UARTD_REG: 1327 if (rate == parent_rate) { 1328 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1329 } else if (rate) { 1330 v |= CAR_CLKSRC_UART_DIV_ENB; 1331 raw_div = (parent_rate / rate) * 2; 1332 if (raw_div >= 2) 1333 raw_div -= 2; 1334 } 1335 break; 1336 case CAR_CLKSRC_I2C1_REG: 1337 case CAR_CLKSRC_I2C2_REG: 1338 case CAR_CLKSRC_I2C3_REG: 1339 case CAR_CLKSRC_I2C4_REG: 1340 case CAR_CLKSRC_I2C5_REG: 1341 case CAR_CLKSRC_I2C6_REG: 1342 if (rate) 1343 raw_div = (parent_rate / rate) - 1; 1344 break; 1345 case CAR_CLKSRC_SDMMC1_REG: 1346 case CAR_CLKSRC_SDMMC2_REG: 1347 case CAR_CLKSRC_SDMMC3_REG: 1348 case CAR_CLKSRC_SDMMC4_REG: 1349 if (rate) { 1350 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1351 u_int calc_rate = 1352 parent_rate / ((raw_div / 2) + 1); 1353 if (calc_rate <= rate) 1354 break; 1355 } 1356 if (raw_div == 0x100) 1357 return EINVAL; 1358 } 1359 break; 1360 default: 1361 if (rate) { 1362 raw_div = (parent_rate / rate) * 2; 1363 if (raw_div >= 2) 1364 raw_div -= 2; 1365 } 1366 break; 1367 } 1368 1369 v &= ~tdiv->bits; 1370 v |= __SHIFTIN(raw_div, tdiv->bits); 1371 1372 bus_space_write_4(bst, bsh, tdiv->reg, v); 1373 1374 return 0; 1375 } 1376 1377 static int 1378 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1379 struct tegra_clk *tclk, bool enable) 1380 { 1381 struct tegra_gate_clk *tgate = &tclk->u.gate; 1382 bus_space_tag_t bst = sc->sc_bst; 1383 bus_space_handle_t bsh = sc->sc_bsh; 1384 bus_size_t reg; 1385 1386 KASSERT(tclk->type == TEGRA_CLK_GATE); 1387 1388 if (tgate->set_reg == tgate->clr_reg) { 1389 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1390 if (enable) { 1391 v |= tgate->bits; 1392 } else { 1393 v &= ~tgate->bits; 1394 } 1395 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1396 } else { 1397 if (enable) { 1398 reg = tgate->set_reg; 1399 } else { 1400 reg = tgate->clr_reg; 1401 } 1402 bus_space_write_4(bst, bsh, reg, tgate->bits); 1403 } 1404 1405 return 0; 1406 } 1407 1408 static u_int 1409 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1410 { 1411 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1412 struct clk *clk_parent; 1413 1414 switch (tclk->type) { 1415 case TEGRA_CLK_FIXED: 1416 return tclk->u.fixed.rate; 1417 case TEGRA_CLK_PLL: 1418 return tegra210_car_clock_get_rate_pll(priv, tclk); 1419 case TEGRA_CLK_MUX: 1420 case TEGRA_CLK_GATE: 1421 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1422 if (clk_parent == NULL) 1423 return EINVAL; 1424 return tegra210_car_clock_get_rate(priv, clk_parent); 1425 case TEGRA_CLK_FIXED_DIV: 1426 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1427 case TEGRA_CLK_DIV: 1428 return tegra210_car_clock_get_rate_div(priv, tclk); 1429 default: 1430 panic("tegra210: unknown tclk type %d", tclk->type); 1431 } 1432 } 1433 1434 static int 1435 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1436 { 1437 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1438 struct clk *clk_parent; 1439 1440 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1441 1442 switch (tclk->type) { 1443 case TEGRA_CLK_FIXED: 1444 case TEGRA_CLK_MUX: 1445 return EIO; 1446 case TEGRA_CLK_FIXED_DIV: 1447 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1448 if (clk_parent == NULL) 1449 return EIO; 1450 return tegra210_car_clock_set_rate(priv, clk_parent, 1451 rate * tclk->u.fixed_div.div); 1452 case TEGRA_CLK_GATE: 1453 return EINVAL; 1454 case TEGRA_CLK_PLL: 1455 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1456 case TEGRA_CLK_DIV: 1457 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1458 default: 1459 panic("tegra210: unknown tclk type %d", tclk->type); 1460 } 1461 } 1462 1463 static int 1464 tegra210_car_clock_enable(void *priv, struct clk *clk) 1465 { 1466 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1467 struct clk *clk_parent; 1468 1469 if (tclk->type != TEGRA_CLK_GATE) { 1470 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1471 if (clk_parent == NULL) 1472 return 0; 1473 return tegra210_car_clock_enable(priv, clk_parent); 1474 } 1475 1476 return tegra210_car_clock_enable_gate(priv, tclk, true); 1477 } 1478 1479 static int 1480 tegra210_car_clock_disable(void *priv, struct clk *clk) 1481 { 1482 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1483 1484 if (tclk->type != TEGRA_CLK_GATE) 1485 return EINVAL; 1486 1487 return tegra210_car_clock_enable_gate(priv, tclk, false); 1488 } 1489 1490 static int 1491 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1492 struct clk *clk_parent) 1493 { 1494 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1495 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1496 struct clk *nclk_parent; 1497 1498 if (tclk->type != TEGRA_CLK_MUX) { 1499 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1500 if (nclk_parent == clk_parent || nclk_parent == NULL) 1501 return EINVAL; 1502 return tegra210_car_clock_set_parent(priv, nclk_parent, 1503 clk_parent); 1504 } 1505 1506 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1507 } 1508 1509 static struct clk * 1510 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1511 { 1512 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1513 struct tegra_clk *tclk_parent = NULL; 1514 1515 switch (tclk->type) { 1516 case TEGRA_CLK_FIXED: 1517 case TEGRA_CLK_PLL: 1518 case TEGRA_CLK_FIXED_DIV: 1519 case TEGRA_CLK_DIV: 1520 case TEGRA_CLK_GATE: 1521 if (tclk->parent) { 1522 tclk_parent = tegra210_car_clock_find(tclk->parent); 1523 } 1524 break; 1525 case TEGRA_CLK_MUX: 1526 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1527 break; 1528 } 1529 1530 if (tclk_parent == NULL) 1531 return NULL; 1532 1533 return TEGRA_CLK_BASE(tclk_parent); 1534 } 1535 1536 static void * 1537 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1538 { 1539 struct tegra210_car_softc * const sc = device_private(dev); 1540 struct tegra210_car_rst *rst; 1541 1542 if (len != sc->sc_reset_cells * 4) 1543 return NULL; 1544 1545 const u_int reset_id = be32dec(data); 1546 1547 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1548 return NULL; 1549 1550 const u_int reg = reset_id / 32; 1551 1552 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1553 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1554 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1555 rst->mask = __BIT(reset_id % 32); 1556 1557 return rst; 1558 } 1559 1560 static void 1561 tegra210_car_reset_release(device_t dev, void *priv) 1562 { 1563 struct tegra210_car_rst *rst = priv; 1564 1565 kmem_free(rst, sizeof(*rst)); 1566 } 1567 1568 static int 1569 tegra210_car_reset_assert(device_t dev, void *priv) 1570 { 1571 struct tegra210_car_softc * const sc = device_private(dev); 1572 struct tegra210_car_rst *rst = priv; 1573 1574 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1575 1576 return 0; 1577 } 1578 1579 static int 1580 tegra210_car_reset_deassert(device_t dev, void *priv) 1581 { 1582 struct tegra210_car_softc * const sc = device_private(dev); 1583 struct tegra210_car_rst *rst = priv; 1584 1585 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1586 1587 return 0; 1588 } 1589 1590 void 1591 tegra210_car_xusbio_enable_hw_control(void) 1592 { 1593 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1594 KASSERT(dev != NULL); 1595 struct tegra210_car_softc * const sc = device_private(dev); 1596 bus_space_tag_t bst = sc->sc_bst; 1597 bus_space_handle_t bsh = sc->sc_bsh; 1598 1599 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1600 0, 1601 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1602 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1603 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1604 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1605 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1606 0); 1607 } 1608 1609 void 1610 tegra210_car_xusbio_enable_hw_seq(void) 1611 { 1612 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1613 KASSERT(dev != NULL); 1614 struct tegra210_car_softc * const sc = device_private(dev); 1615 bus_space_tag_t bst = sc->sc_bst; 1616 bus_space_handle_t bsh = sc->sc_bsh; 1617 1618 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1619 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1620 } 1621
Indexes created Tue Sep 30 20:09:53 GMT 2025