tegra210_car.c revision 1.15
1 /* $NetBSD: tegra210_car.c,v 1.15 2017/09/27 10:19:48 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.15 2017/09/27 10:19:48 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static const char *mux_mselect_p[] = 440 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT2", 441 "PLL_C4_OUT1", "CLK_S", "CLK_M", "PLL_C4_OUT0" }; 442 443 static const char *mux_tsensor_p[] = 444 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 445 "CLK_M", "PLL_C4_OUT1", "CLK_S", "PLL_C4_OUT2" }; 446 447 static const char *mux_soc_therm_p[] = 448 { "CLK_M", "PLL_C", "PLL_P", "PLL_A", 449 "PLL_C2", "PLL_C4_OUT0", "PLL_C4_OUT1", "PLL_C4_OUT2" }; 450 451 static struct tegra_clk tegra210_car_clocks[] = { 452 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 453 454 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 455 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 456 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 457 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 458 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 459 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 460 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 461 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 462 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 463 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 464 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 465 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 466 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 467 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 468 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 469 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 470 471 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 472 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 473 474 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 475 mux_uart_p), 476 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 477 mux_uart_p), 478 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 479 mux_uart_p), 480 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 481 mux_uart_p), 482 483 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 484 mux_sdmmc1_p), 485 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 486 mux_sdmmc2_4_p), 487 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 488 mux_sdmmc3_p), 489 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 490 mux_sdmmc2_4_p), 491 492 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 493 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 494 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 495 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 496 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 497 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 498 499 CLK_MUX("MUX_XUSB_HOST", 500 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 501 mux_xusb_host_p), 502 CLK_MUX("MUX_XUSB_FALCON", 503 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 504 mux_xusb_host_p), 505 CLK_MUX("MUX_XUSB_SS", 506 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 507 mux_xusb_ss_p), 508 CLK_MUX("MUX_XUSB_FS", 509 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 510 mux_xusb_fs_p), 511 512 CLK_MUX("MUX_MSELECT", 513 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 514 mux_mselect_p), 515 516 CLK_MUX("MUX_TSENSOR", 517 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 518 mux_tsensor_p), 519 CLK_MUX("MUX_SOC_THERM", 520 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 521 mux_soc_therm_p), 522 523 CLK_DIV("DIV_UARTA", "MUX_UARTA", 524 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 525 CLK_DIV("DIV_UARTB", "MUX_UARTB", 526 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 527 CLK_DIV("DIV_UARTC", "MUX_UARTC", 528 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 529 CLK_DIV("DIV_UARTD", "MUX_UARTD", 530 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 531 532 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 533 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 534 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 535 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 536 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 537 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 538 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 539 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 540 541 CLK_DIV("DIV_I2C1", "MUX_I2C1", 542 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 543 CLK_DIV("DIV_I2C2", "MUX_I2C2", 544 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 545 CLK_DIV("DIV_I2C3", "MUX_I2C3", 546 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 547 CLK_DIV("DIV_I2C4", "MUX_I2C4", 548 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 549 CLK_DIV("DIV_I2C5", "MUX_I2C5", 550 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 551 CLK_DIV("DIV_I2C6", "MUX_I2C6", 552 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 553 554 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 555 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 556 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 557 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 558 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 559 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 560 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 561 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 562 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 563 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 564 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 565 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 566 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 567 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 568 569 CLK_DIV("DIV_MSELECT", "MUX_MSELECT", 570 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 571 572 CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR", 573 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 574 CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM", 575 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 576 577 CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 578 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 579 CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 580 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 581 582 CLK_GATE("CML0", "PLL_E", 583 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 584 CLK_GATE("CML1", "PLL_E", 585 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 586 587 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 588 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 589 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 590 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 591 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 592 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 593 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 594 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 595 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 596 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 597 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 598 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 599 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 600 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 601 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 602 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 603 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 604 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 605 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 606 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 607 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 608 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 609 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 610 CLK_GATE_V("MSELECT", "DIV_MSELECT", CAR_DEV_V_MSELECT), 611 CLK_GATE_U("PCIE", "CLK_M", CAR_DEV_U_PCIE), 612 CLK_GATE_U("AFI", "MSELECT", CAR_DEV_U_AFI), 613 CLK_GATE_V("TSENSOR", "DIV_TSENSOR", CAR_DEV_V_TSENSOR), 614 CLK_GATE_U("SOC_THERM", "DIV_SOC_THERM", CAR_DEV_U_SOC_THERM), 615 }; 616 617 struct tegra210_init_parent { 618 const char *clock; 619 const char *parent; 620 u_int rate; 621 u_int enable; 622 } tegra210_init_parents[] = { 623 { "SDMMC1", "PLL_P", 0, 0 }, 624 { "SDMMC2", "PLL_P", 0, 0 }, 625 { "SDMMC3", "PLL_P", 0, 0 }, 626 { "SDMMC4", "PLL_P", 0, 0 }, 627 { "SOC_THERM", "PLL_P", 0, 0 }, 628 { "TSENSOR", "CLK_M", 0, 0 }, 629 { "XUSB_GATE", NULL, 0, 1 }, 630 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 631 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 632 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 633 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 634 { "PLL_U_OUT1", NULL, 48000000, 1 }, 635 { "PLL_U_OUT2", NULL, 60000000, 1 }, 636 { "CML0", NULL, 0, 1 }, 637 { "AFI", NULL, 0, 1 }, 638 { "PCIE", NULL, 0, 1 }, 639 }; 640 641 struct tegra210_car_rst { 642 u_int set_reg; 643 u_int clr_reg; 644 u_int mask; 645 }; 646 647 static struct tegra210_car_reset_reg { 648 u_int set_reg; 649 u_int clr_reg; 650 } tegra210_car_reset_regs[] = { 651 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 652 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 653 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 654 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 655 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 656 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 657 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 658 }; 659 660 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 661 static void tegra210_car_reset_release(device_t, void *); 662 static int tegra210_car_reset_assert(device_t, void *); 663 static int tegra210_car_reset_deassert(device_t, void *); 664 665 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 666 .acquire = tegra210_car_reset_acquire, 667 .release = tegra210_car_reset_release, 668 .reset_assert = tegra210_car_reset_assert, 669 .reset_deassert = tegra210_car_reset_deassert, 670 }; 671 672 struct tegra210_car_softc { 673 device_t sc_dev; 674 bus_space_tag_t sc_bst; 675 bus_space_handle_t sc_bsh; 676 677 struct clk_domain sc_clkdom; 678 679 u_int sc_clock_cells; 680 u_int sc_reset_cells; 681 682 kmutex_t sc_rndlock; 683 krndsource_t sc_rndsource; 684 }; 685 686 static void tegra210_car_init(struct tegra210_car_softc *); 687 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 688 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 689 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 690 static void tegra210_car_parent_init(struct tegra210_car_softc *); 691 692 693 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 694 tegra210_car_match, tegra210_car_attach, NULL, NULL); 695 696 static int 697 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 698 { 699 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 700 struct fdt_attach_args * const faa = aux; 701 702 #if 0 703 return of_match_compatible(faa->faa_phandle, compatible); 704 #else 705 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 706 return 0; 707 708 return 999; 709 #endif 710 } 711 712 static void 713 tegra210_car_attach(device_t parent, device_t self, void *aux) 714 { 715 struct tegra210_car_softc * const sc = device_private(self); 716 struct fdt_attach_args * const faa = aux; 717 const int phandle = faa->faa_phandle; 718 bus_addr_t addr; 719 bus_size_t size; 720 int error, n; 721 722 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 723 aprint_error(": couldn't get registers\n"); 724 return; 725 } 726 727 sc->sc_dev = self; 728 sc->sc_bst = faa->faa_bst; 729 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 730 if (error) { 731 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 732 return; 733 } 734 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 735 sc->sc_clock_cells = 1; 736 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 737 sc->sc_reset_cells = 1; 738 739 aprint_naive("\n"); 740 aprint_normal(": CAR\n"); 741 742 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 743 sc->sc_clkdom.priv = sc; 744 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 745 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 746 747 fdtbus_register_clock_controller(self, phandle, 748 &tegra210_car_fdtclock_funcs); 749 fdtbus_register_reset_controller(self, phandle, 750 &tegra210_car_fdtreset_funcs); 751 752 tegra210_car_init(sc); 753 754 #ifdef TEGRA210_CAR_DEBUG 755 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 756 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 757 struct clk *clk_parent = clk_get_parent(clk); 758 device_printf(self, "clk %s (parent %s): ", clk->name, 759 clk_parent ? clk_parent->name : "none"); 760 printf("%u Hz\n", clk_get_rate(clk)); 761 } 762 #endif 763 } 764 765 static void 766 tegra210_car_init(struct tegra210_car_softc *sc) 767 { 768 tegra210_car_parent_init(sc); 769 tegra210_car_utmip_init(sc); 770 tegra210_car_xusb_init(sc); 771 tegra210_car_watchdog_init(sc); 772 } 773 774 static void 775 tegra210_car_parent_init(struct tegra210_car_softc *sc) 776 { 777 struct clk *clk, *clk_parent; 778 int error; 779 u_int n; 780 781 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 782 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 783 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 784 785 if (tegra210_init_parents[n].parent != NULL) { 786 clk_parent = clk_get(&sc->sc_clkdom, 787 tegra210_init_parents[n].parent); 788 KASSERT(clk_parent != NULL); 789 790 error = clk_set_parent(clk, clk_parent); 791 if (error) { 792 aprint_error_dev(sc->sc_dev, 793 "couldn't set '%s' parent to '%s': %d\n", 794 clk->name, clk_parent->name, error); 795 } 796 clk_put(clk_parent); 797 } 798 if (tegra210_init_parents[n].rate != 0) { 799 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 800 if (error) { 801 aprint_error_dev(sc->sc_dev, 802 "couldn't set '%s' rate to %u Hz: %d\n", 803 clk->name, tegra210_init_parents[n].rate, 804 error); 805 } 806 } 807 if (tegra210_init_parents[n].enable) { 808 error = clk_enable(clk); 809 if (error) { 810 aprint_error_dev(sc->sc_dev, 811 "couldn't enable '%s': %d\n", clk->name, 812 error); 813 } 814 } 815 clk_put(clk); 816 } 817 } 818 819 static void 820 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 821 { 822 bus_space_tag_t bst = sc->sc_bst; 823 bus_space_handle_t bsh = sc->sc_bsh; 824 825 /* 826 * Set up the UTMI PLL. 827 */ 828 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 829 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 830 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 831 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 832 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 833 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 834 delay(10); 835 /* TODO UTMIP_PLL_CFG0 */ 836 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 837 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 838 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 839 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 840 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 841 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 842 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 843 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 844 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 845 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 846 847 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI); 848 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE); 849 850 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 851 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 852 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 853 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI); 854 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE); 855 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK); 856 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 857 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 858 859 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 860 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 861 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 862 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 863 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 864 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 865 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 866 867 /* 868 * Set up UTMI PLL under hardware control 869 */ 870 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 871 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 872 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 873 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 874 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 875 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 876 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 877 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 878 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 879 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 880 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 881 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 882 delay(1); 883 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 884 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 885 } 886 887 static void 888 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 889 { 890 const bus_space_tag_t bst = sc->sc_bst; 891 const bus_space_handle_t bsh = sc->sc_bsh; 892 uint32_t val; 893 894 /* 895 * Set up the PLLU. 896 */ 897 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 898 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 899 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 900 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 901 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 902 delay(5); 903 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 904 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 905 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 906 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 907 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 908 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 909 do { 910 delay(2); 911 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 912 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 913 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 914 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 915 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 916 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 917 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 918 delay(2); 919 920 /* 921 * Now switch PLLU to hw controlled mode. 922 */ 923 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 924 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 925 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 926 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 927 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 928 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 929 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 930 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 931 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 932 delay(1); 933 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 934 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 935 delay(1); 936 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 937 938 /* 939 * Set up PLLREFE 940 */ 941 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 942 0, CAR_PLLREFE_MISC_IDDQ); 943 delay(5); 944 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 945 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 946 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 947 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 948 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 949 CAR_PLLREFE_BASE_DIVM | 950 CAR_PLLREFE_BASE_DIVN | 951 CAR_PLLREFE_BASE_DIVP | 952 CAR_PLLREFE_BASE_KCP); 953 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 954 CAR_PLLREFE_BASE_ENABLE, 0); 955 do { 956 delay(2); 957 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 958 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 959 960 /* 961 * Set up the PLLE. 962 */ 963 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 964 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 965 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 966 delay(5); 967 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 968 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 969 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 970 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 971 CAR_PLLE_BASE_DIVP_CML | 972 CAR_PLLE_BASE_DIVN | 973 CAR_PLLE_BASE_DIVM); 974 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 975 CAR_PLLE_MISC_PTS, 976 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 977 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 978 do { 979 delay(2); 980 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 981 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 982 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 983 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 984 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 985 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 986 CAR_PLLE_SS_CNTL_SSCINC | 987 CAR_PLLE_SS_CNTL_SSCINCINTRV | 988 CAR_PLLE_SS_CNTL_SSCMAX | 989 CAR_PLLE_SS_CNTL_SSCINVERT | 990 CAR_PLLE_SS_CNTL_SSCCENTER | 991 CAR_PLLE_SS_CNTL_BYPASS_SS | 992 CAR_PLLE_SS_CNTL_SSCBYP); 993 delay(1); 994 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 995 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 996 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 997 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 998 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 999 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 1000 delay(1); 1001 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 1002 1003 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 1004 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 1005 } 1006 1007 static void 1008 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 1009 { 1010 const bus_space_tag_t bst = sc->sc_bst; 1011 const bus_space_handle_t bsh = sc->sc_bsh; 1012 1013 /* Enable watchdog timer reset for system */ 1014 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 1015 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 1016 } 1017 1018 static struct tegra_clk * 1019 tegra210_car_clock_find(const char *name) 1020 { 1021 u_int n; 1022 1023 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 1024 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 1025 return &tegra210_car_clocks[n]; 1026 } 1027 } 1028 1029 return NULL; 1030 } 1031 1032 static struct tegra_clk * 1033 tegra210_car_clock_find_by_id(u_int clock_id) 1034 { 1035 u_int n; 1036 1037 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 1038 if (tegra210_car_clock_ids[n].id == clock_id) { 1039 const char *name = tegra210_car_clock_ids[n].name; 1040 return tegra210_car_clock_find(name); 1041 } 1042 } 1043 1044 return NULL; 1045 } 1046 1047 static struct clk * 1048 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 1049 { 1050 struct tegra210_car_softc * const sc = device_private(dev); 1051 struct tegra_clk *tclk; 1052 1053 if (len != sc->sc_clock_cells * 4) { 1054 return NULL; 1055 } 1056 1057 const u_int clock_id = be32dec(data); 1058 1059 tclk = tegra210_car_clock_find_by_id(clock_id); 1060 if (tclk) 1061 return TEGRA_CLK_BASE(tclk); 1062 1063 return NULL; 1064 } 1065 1066 static struct clk * 1067 tegra210_car_clock_get(void *priv, const char *name) 1068 { 1069 struct tegra_clk *tclk; 1070 1071 tclk = tegra210_car_clock_find(name); 1072 if (tclk == NULL) 1073 return NULL; 1074 1075 atomic_inc_uint(&tclk->refcnt); 1076 1077 return TEGRA_CLK_BASE(tclk); 1078 } 1079 1080 static void 1081 tegra210_car_clock_put(void *priv, struct clk *clk) 1082 { 1083 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1084 1085 KASSERT(tclk->refcnt > 0); 1086 1087 atomic_dec_uint(&tclk->refcnt); 1088 } 1089 1090 static u_int 1091 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1092 struct tegra_clk *tclk) 1093 { 1094 struct tegra_pll_clk *tpll = &tclk->u.pll; 1095 struct tegra_clk *tclk_parent; 1096 bus_space_tag_t bst = sc->sc_bst; 1097 bus_space_handle_t bsh = sc->sc_bsh; 1098 u_int divm, divn, divp; 1099 uint64_t rate; 1100 1101 KASSERT(tclk->type == TEGRA_CLK_PLL); 1102 1103 tclk_parent = tegra210_car_clock_find(tclk->parent); 1104 KASSERT(tclk_parent != NULL); 1105 1106 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1107 TEGRA_CLK_BASE(tclk_parent)); 1108 1109 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1110 divm = __SHIFTOUT(base, tpll->divm_mask); 1111 divn = __SHIFTOUT(base, tpll->divn_mask); 1112 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1113 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1114 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1115 /* XXX divp is not applied to PLLP's primary output */ 1116 divp = 0; 1117 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1118 divp = 0; 1119 divm *= __SHIFTOUT(base, tpll->divp_mask); 1120 } else { 1121 divp = __SHIFTOUT(base, tpll->divp_mask); 1122 } 1123 1124 rate = (uint64_t)rate_parent * divn; 1125 return rate / (divm << divp); 1126 } 1127 1128 static int 1129 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1130 struct tegra_clk *tclk, u_int rate) 1131 { 1132 struct tegra_pll_clk *tpll = &tclk->u.pll; 1133 bus_space_tag_t bst = sc->sc_bst; 1134 bus_space_handle_t bsh = sc->sc_bsh; 1135 struct clk *clk_parent; 1136 uint32_t bp, base; 1137 1138 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1139 if (clk_parent == NULL) 1140 return EIO; 1141 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1142 if (rate_parent == 0) 1143 return EIO; 1144 1145 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1146 const u_int divm = 1; 1147 const u_int divn = rate / rate_parent; 1148 const u_int divp = 0; 1149 1150 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1151 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1152 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1153 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1154 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1155 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1156 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1157 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1158 1159 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1160 base &= ~CAR_PLLX_BASE_DIVM; 1161 base &= ~CAR_PLLX_BASE_DIVN; 1162 base &= ~CAR_PLLX_BASE_DIVP; 1163 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1164 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1165 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1166 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1167 1168 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1169 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1170 do { 1171 delay(2); 1172 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1173 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1174 delay(100); 1175 1176 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1177 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1178 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1179 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1180 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1181 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1182 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1183 1184 return 0; 1185 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1186 const u_int divm = 1; 1187 const u_int pldiv = 1; 1188 const u_int divn = (rate << pldiv) / rate_parent; 1189 1190 /* Set frequency */ 1191 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1192 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1193 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1194 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1195 CAR_PLLD2_BASE_REF_SRC_SEL | 1196 CAR_PLLD2_BASE_DIVM | 1197 CAR_PLLD2_BASE_DIVN | 1198 CAR_PLLD2_BASE_DIVP); 1199 1200 return 0; 1201 } else { 1202 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1203 tclk->base.name, rate); 1204 /* TODO */ 1205 return EOPNOTSUPP; 1206 } 1207 } 1208 1209 static int 1210 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1211 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1212 { 1213 struct tegra_mux_clk *tmux = &tclk->u.mux; 1214 bus_space_tag_t bst = sc->sc_bst; 1215 bus_space_handle_t bsh = sc->sc_bsh; 1216 uint32_t v; 1217 u_int src; 1218 1219 KASSERT(tclk->type == TEGRA_CLK_MUX); 1220 1221 for (src = 0; src < tmux->nparents; src++) { 1222 if (tmux->parents[src] == NULL) { 1223 continue; 1224 } 1225 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1226 break; 1227 } 1228 } 1229 if (src == tmux->nparents) { 1230 return EINVAL; 1231 } 1232 1233 v = bus_space_read_4(bst, bsh, tmux->reg); 1234 v &= ~tmux->bits; 1235 v |= __SHIFTIN(src, tmux->bits); 1236 bus_space_write_4(bst, bsh, tmux->reg, v); 1237 1238 return 0; 1239 } 1240 1241 static struct tegra_clk * 1242 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1243 struct tegra_clk *tclk) 1244 { 1245 struct tegra_mux_clk *tmux = &tclk->u.mux; 1246 bus_space_tag_t bst = sc->sc_bst; 1247 bus_space_handle_t bsh = sc->sc_bsh; 1248 1249 KASSERT(tclk->type == TEGRA_CLK_MUX); 1250 1251 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1252 const u_int src = __SHIFTOUT(v, tmux->bits); 1253 1254 KASSERT(src < tmux->nparents); 1255 1256 if (tmux->parents[src] == NULL) { 1257 return NULL; 1258 } 1259 1260 return tegra210_car_clock_find(tmux->parents[src]); 1261 } 1262 1263 static u_int 1264 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1265 struct tegra_clk *tclk) 1266 { 1267 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1268 struct clk *clk_parent; 1269 1270 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1271 if (clk_parent == NULL) 1272 return 0; 1273 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1274 1275 return parent_rate / tfixed_div->div; 1276 } 1277 1278 static u_int 1279 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1280 struct tegra_clk *tclk) 1281 { 1282 struct tegra_div_clk *tdiv = &tclk->u.div; 1283 bus_space_tag_t bst = sc->sc_bst; 1284 bus_space_handle_t bsh = sc->sc_bsh; 1285 struct clk *clk_parent; 1286 u_int rate; 1287 1288 KASSERT(tclk->type == TEGRA_CLK_DIV); 1289 1290 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1291 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1292 1293 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1294 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1295 1296 switch (tdiv->reg) { 1297 case CAR_CLKSRC_I2C1_REG: 1298 case CAR_CLKSRC_I2C2_REG: 1299 case CAR_CLKSRC_I2C3_REG: 1300 case CAR_CLKSRC_I2C4_REG: 1301 case CAR_CLKSRC_I2C5_REG: 1302 case CAR_CLKSRC_I2C6_REG: 1303 rate = parent_rate / (raw_div + 1); 1304 break; 1305 case CAR_CLKSRC_UARTA_REG: 1306 case CAR_CLKSRC_UARTB_REG: 1307 case CAR_CLKSRC_UARTC_REG: 1308 case CAR_CLKSRC_UARTD_REG: 1309 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1310 rate = parent_rate / ((raw_div / 2) + 1); 1311 } else { 1312 rate = parent_rate; 1313 } 1314 break; 1315 case CAR_CLKSRC_SDMMC2_REG: 1316 case CAR_CLKSRC_SDMMC4_REG: 1317 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1318 case 1: 1319 case 2: 1320 case 5: 1321 raw_div = 0; /* ignore divisor for _LJ options */ 1322 break; 1323 } 1324 /* FALLTHROUGH */ 1325 default: 1326 rate = parent_rate / ((raw_div / 2) + 1); 1327 break; 1328 } 1329 1330 return rate; 1331 } 1332 1333 static int 1334 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1335 struct tegra_clk *tclk, u_int rate) 1336 { 1337 struct tegra_div_clk *tdiv = &tclk->u.div; 1338 bus_space_tag_t bst = sc->sc_bst; 1339 bus_space_handle_t bsh = sc->sc_bsh; 1340 struct clk *clk_parent; 1341 u_int raw_div; 1342 uint32_t v; 1343 1344 KASSERT(tclk->type == TEGRA_CLK_DIV); 1345 1346 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1347 if (clk_parent == NULL) 1348 return EINVAL; 1349 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1350 1351 v = bus_space_read_4(bst, bsh, tdiv->reg); 1352 1353 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1354 1355 switch (tdiv->reg) { 1356 case CAR_CLKSRC_UARTA_REG: 1357 case CAR_CLKSRC_UARTB_REG: 1358 case CAR_CLKSRC_UARTC_REG: 1359 case CAR_CLKSRC_UARTD_REG: 1360 if (rate == parent_rate) { 1361 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1362 } else if (rate) { 1363 v |= CAR_CLKSRC_UART_DIV_ENB; 1364 raw_div = (parent_rate / rate) * 2; 1365 if (raw_div >= 2) 1366 raw_div -= 2; 1367 } 1368 break; 1369 case CAR_CLKSRC_I2C1_REG: 1370 case CAR_CLKSRC_I2C2_REG: 1371 case CAR_CLKSRC_I2C3_REG: 1372 case CAR_CLKSRC_I2C4_REG: 1373 case CAR_CLKSRC_I2C5_REG: 1374 case CAR_CLKSRC_I2C6_REG: 1375 if (rate) 1376 raw_div = (parent_rate / rate) - 1; 1377 break; 1378 case CAR_CLKSRC_SDMMC1_REG: 1379 case CAR_CLKSRC_SDMMC2_REG: 1380 case CAR_CLKSRC_SDMMC3_REG: 1381 case CAR_CLKSRC_SDMMC4_REG: 1382 if (rate) { 1383 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1384 u_int calc_rate = 1385 parent_rate / ((raw_div / 2) + 1); 1386 if (calc_rate <= rate) 1387 break; 1388 } 1389 if (raw_div == 0x100) 1390 return EINVAL; 1391 } 1392 break; 1393 default: 1394 if (rate) { 1395 raw_div = (parent_rate / rate) * 2; 1396 if (raw_div >= 2) 1397 raw_div -= 2; 1398 } 1399 break; 1400 } 1401 1402 v &= ~tdiv->bits; 1403 v |= __SHIFTIN(raw_div, tdiv->bits); 1404 1405 bus_space_write_4(bst, bsh, tdiv->reg, v); 1406 1407 return 0; 1408 } 1409 1410 static int 1411 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1412 struct tegra_clk *tclk, bool enable) 1413 { 1414 struct tegra_gate_clk *tgate = &tclk->u.gate; 1415 bus_space_tag_t bst = sc->sc_bst; 1416 bus_space_handle_t bsh = sc->sc_bsh; 1417 bus_size_t reg; 1418 1419 KASSERT(tclk->type == TEGRA_CLK_GATE); 1420 1421 if (tgate->set_reg == tgate->clr_reg) { 1422 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1423 if (enable) { 1424 v |= tgate->bits; 1425 } else { 1426 v &= ~tgate->bits; 1427 } 1428 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1429 } else { 1430 if (enable) { 1431 reg = tgate->set_reg; 1432 } else { 1433 reg = tgate->clr_reg; 1434 } 1435 bus_space_write_4(bst, bsh, reg, tgate->bits); 1436 } 1437 1438 return 0; 1439 } 1440 1441 static u_int 1442 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1443 { 1444 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1445 struct clk *clk_parent; 1446 1447 switch (tclk->type) { 1448 case TEGRA_CLK_FIXED: 1449 return tclk->u.fixed.rate; 1450 case TEGRA_CLK_PLL: 1451 return tegra210_car_clock_get_rate_pll(priv, tclk); 1452 case TEGRA_CLK_MUX: 1453 case TEGRA_CLK_GATE: 1454 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1455 if (clk_parent == NULL) 1456 return EINVAL; 1457 return tegra210_car_clock_get_rate(priv, clk_parent); 1458 case TEGRA_CLK_FIXED_DIV: 1459 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1460 case TEGRA_CLK_DIV: 1461 return tegra210_car_clock_get_rate_div(priv, tclk); 1462 default: 1463 panic("tegra210: unknown tclk type %d", tclk->type); 1464 } 1465 } 1466 1467 static int 1468 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1469 { 1470 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1471 struct clk *clk_parent; 1472 1473 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1474 1475 switch (tclk->type) { 1476 case TEGRA_CLK_FIXED: 1477 case TEGRA_CLK_MUX: 1478 return EIO; 1479 case TEGRA_CLK_FIXED_DIV: 1480 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1481 if (clk_parent == NULL) 1482 return EIO; 1483 return tegra210_car_clock_set_rate(priv, clk_parent, 1484 rate * tclk->u.fixed_div.div); 1485 case TEGRA_CLK_GATE: 1486 return EINVAL; 1487 case TEGRA_CLK_PLL: 1488 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1489 case TEGRA_CLK_DIV: 1490 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1491 default: 1492 panic("tegra210: unknown tclk type %d", tclk->type); 1493 } 1494 } 1495 1496 static int 1497 tegra210_car_clock_enable(void *priv, struct clk *clk) 1498 { 1499 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1500 struct clk *clk_parent; 1501 1502 if (tclk->type != TEGRA_CLK_GATE) { 1503 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1504 if (clk_parent == NULL) 1505 return 0; 1506 return tegra210_car_clock_enable(priv, clk_parent); 1507 } 1508 1509 return tegra210_car_clock_enable_gate(priv, tclk, true); 1510 } 1511 1512 static int 1513 tegra210_car_clock_disable(void *priv, struct clk *clk) 1514 { 1515 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1516 1517 if (tclk->type != TEGRA_CLK_GATE) 1518 return EINVAL; 1519 1520 return tegra210_car_clock_enable_gate(priv, tclk, false); 1521 } 1522 1523 static int 1524 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1525 struct clk *clk_parent) 1526 { 1527 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1528 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1529 struct clk *nclk_parent; 1530 1531 if (tclk->type != TEGRA_CLK_MUX) { 1532 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1533 if (nclk_parent == clk_parent || nclk_parent == NULL) 1534 return EINVAL; 1535 return tegra210_car_clock_set_parent(priv, nclk_parent, 1536 clk_parent); 1537 } 1538 1539 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1540 } 1541 1542 static struct clk * 1543 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1544 { 1545 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1546 struct tegra_clk *tclk_parent = NULL; 1547 1548 switch (tclk->type) { 1549 case TEGRA_CLK_FIXED: 1550 case TEGRA_CLK_PLL: 1551 case TEGRA_CLK_FIXED_DIV: 1552 case TEGRA_CLK_DIV: 1553 case TEGRA_CLK_GATE: 1554 if (tclk->parent) { 1555 tclk_parent = tegra210_car_clock_find(tclk->parent); 1556 } 1557 break; 1558 case TEGRA_CLK_MUX: 1559 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1560 break; 1561 } 1562 1563 if (tclk_parent == NULL) 1564 return NULL; 1565 1566 return TEGRA_CLK_BASE(tclk_parent); 1567 } 1568 1569 static void * 1570 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1571 { 1572 struct tegra210_car_softc * const sc = device_private(dev); 1573 struct tegra210_car_rst *rst; 1574 1575 if (len != sc->sc_reset_cells * 4) 1576 return NULL; 1577 1578 const u_int reset_id = be32dec(data); 1579 1580 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1581 return NULL; 1582 1583 const u_int reg = reset_id / 32; 1584 1585 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1586 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1587 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1588 rst->mask = __BIT(reset_id % 32); 1589 1590 return rst; 1591 } 1592 1593 static void 1594 tegra210_car_reset_release(device_t dev, void *priv) 1595 { 1596 struct tegra210_car_rst *rst = priv; 1597 1598 kmem_free(rst, sizeof(*rst)); 1599 } 1600 1601 static int 1602 tegra210_car_reset_assert(device_t dev, void *priv) 1603 { 1604 struct tegra210_car_softc * const sc = device_private(dev); 1605 struct tegra210_car_rst *rst = priv; 1606 1607 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1608 1609 return 0; 1610 } 1611 1612 static int 1613 tegra210_car_reset_deassert(device_t dev, void *priv) 1614 { 1615 struct tegra210_car_softc * const sc = device_private(dev); 1616 struct tegra210_car_rst *rst = priv; 1617 1618 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1619 1620 return 0; 1621 } 1622 1623 void 1624 tegra210_car_xusbio_enable_hw_control(void) 1625 { 1626 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1627 KASSERT(dev != NULL); 1628 struct tegra210_car_softc * const sc = device_private(dev); 1629 bus_space_tag_t bst = sc->sc_bst; 1630 bus_space_handle_t bsh = sc->sc_bsh; 1631 1632 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1633 0, 1634 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1635 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1636 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1637 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1638 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1639 0); 1640 } 1641 1642 void 1643 tegra210_car_xusbio_enable_hw_seq(void) 1644 { 1645 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1646 KASSERT(dev != NULL); 1647 struct tegra210_car_softc * const sc = device_private(dev); 1648 bus_space_tag_t bst = sc->sc_bst; 1649 bus_space_handle_t bsh = sc->sc_bsh; 1650 1651 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1652 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1653 } 1654
Indexes created Tue Sep 30 20:09:53 GMT 2025