tegra210_car.c revision 1.18
1 /* $NetBSD: tegra210_car.c,v 1.18 2018/07/16 23:11:47 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.18 2018/07/16 23:11:47 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static const char *mux_mselect_p[] = 440 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT2", 441 "PLL_C4_OUT1", "CLK_S", "CLK_M", "PLL_C4_OUT0" }; 442 443 static const char *mux_tsensor_p[] = 444 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 445 "CLK_M", "PLL_C4_OUT1", "CLK_S", "PLL_C4_OUT2" }; 446 447 static const char *mux_soc_therm_p[] = 448 { "CLK_M", "PLL_C", "PLL_P", "PLL_A", 449 "PLL_C2", "PLL_C4_OUT0", "PLL_C4_OUT1", "PLL_C4_OUT2" }; 450 451 static const char *mux_hda2codec_2x_p[] = 452 { "PLL_P", "PLL_C2", "PLL_C4_OUT0", "PLL_A", 453 "PLL_A", "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 454 455 static const char *mux_hda_p[] = 456 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 457 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 458 459 static struct tegra_clk tegra210_car_clocks[] = { 460 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 461 462 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 463 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 464 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 465 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 466 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 467 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 468 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 469 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 470 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 471 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 472 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 473 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 474 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 475 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 476 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 477 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 478 479 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 480 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 481 482 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 483 mux_uart_p), 484 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 485 mux_uart_p), 486 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 487 mux_uart_p), 488 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 489 mux_uart_p), 490 491 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 492 mux_sdmmc1_p), 493 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 494 mux_sdmmc2_4_p), 495 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 496 mux_sdmmc3_p), 497 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 498 mux_sdmmc2_4_p), 499 500 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 501 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 502 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 503 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 504 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 505 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 506 507 CLK_MUX("MUX_XUSB_HOST", 508 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 509 mux_xusb_host_p), 510 CLK_MUX("MUX_XUSB_FALCON", 511 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 512 mux_xusb_host_p), 513 CLK_MUX("MUX_XUSB_SS", 514 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 515 mux_xusb_ss_p), 516 CLK_MUX("MUX_XUSB_FS", 517 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 518 mux_xusb_fs_p), 519 520 CLK_MUX("MUX_MSELECT", 521 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 522 mux_mselect_p), 523 524 CLK_MUX("MUX_TSENSOR", 525 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 526 mux_tsensor_p), 527 CLK_MUX("MUX_SOC_THERM", 528 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 529 mux_soc_therm_p), 530 531 CLK_MUX("MUX_HDA2CODEC_2X", 532 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 533 mux_hda2codec_2x_p), 534 CLK_MUX("MUX_HDA", 535 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, 536 mux_hda_p), 537 538 CLK_DIV("DIV_UARTA", "MUX_UARTA", 539 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 540 CLK_DIV("DIV_UARTB", "MUX_UARTB", 541 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 542 CLK_DIV("DIV_UARTC", "MUX_UARTC", 543 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 544 CLK_DIV("DIV_UARTD", "MUX_UARTD", 545 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 546 547 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 548 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 549 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 550 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 551 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 552 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 553 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 554 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 555 556 CLK_DIV("DIV_I2C1", "MUX_I2C1", 557 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 558 CLK_DIV("DIV_I2C2", "MUX_I2C2", 559 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 560 CLK_DIV("DIV_I2C3", "MUX_I2C3", 561 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 562 CLK_DIV("DIV_I2C4", "MUX_I2C4", 563 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 564 CLK_DIV("DIV_I2C5", "MUX_I2C5", 565 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 566 CLK_DIV("DIV_I2C6", "MUX_I2C6", 567 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 568 569 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 570 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 571 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 572 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 573 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 574 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 575 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 576 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 577 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 578 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 579 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 580 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 581 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 582 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 583 584 CLK_DIV("DIV_MSELECT", "MUX_MSELECT", 585 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 586 587 CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR", 588 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 589 CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM", 590 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 591 592 CLK_DIV("DIV_HDA2CODEC_2X", "MUX_HDA2CODEC_2X", 593 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 594 CLK_DIV("DIV_HDA", "MUX_HDA", 595 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 596 597 CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 598 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 599 CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 600 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 601 602 CLK_GATE_SIMPLE("CML0", "PLL_E", 603 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 604 CLK_GATE_SIMPLE("CML1", "PLL_E", 605 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 606 607 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 608 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 609 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 610 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 611 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 612 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 613 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 614 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 615 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 616 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 617 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 618 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 619 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 620 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 621 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 622 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 623 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 624 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 625 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 626 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 627 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 628 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 629 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 630 CLK_GATE_V("MSELECT", "DIV_MSELECT", CAR_DEV_V_MSELECT), 631 CLK_GATE_U("PCIE", "CLK_M", CAR_DEV_U_PCIE), 632 CLK_GATE_U("AFI", "MSELECT", CAR_DEV_U_AFI), 633 CLK_GATE_V("TSENSOR", "DIV_TSENSOR", CAR_DEV_V_TSENSOR), 634 CLK_GATE_U("SOC_THERM", "DIV_SOC_THERM", CAR_DEV_U_SOC_THERM), 635 CLK_GATE_W("HDA2HDMI", "CLK_M", CAR_DEV_W_HDA2HDMICODEC), 636 CLK_GATE_V("HDA2CODEC_2X", "DIV_HDA2CODEC_2X", CAR_DEV_V_HDA2CODEC_2X), 637 CLK_GATE_V("HDA", "DIV_HDA", CAR_DEV_V_HDA), 638 }; 639 640 struct tegra210_init_parent { 641 const char *clock; 642 const char *parent; 643 u_int rate; 644 u_int enable; 645 } tegra210_init_parents[] = { 646 { "SDMMC1", "PLL_P", 0, 0 }, 647 { "SDMMC2", "PLL_P", 0, 0 }, 648 { "SDMMC3", "PLL_P", 0, 0 }, 649 { "SDMMC4", "PLL_P", 0, 0 }, 650 { "SOC_THERM", "PLL_P", 0, 0 }, 651 { "TSENSOR", "CLK_M", 0, 0 }, 652 { "XUSB_GATE", NULL, 0, 1 }, 653 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 654 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 655 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 656 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 657 { "PLL_U_OUT1", NULL, 48000000, 1 }, 658 { "PLL_U_OUT2", NULL, 60000000, 1 }, 659 { "CML0", NULL, 0, 1 }, 660 { "AFI", NULL, 0, 1 }, 661 { "PCIE", NULL, 0, 1 }, 662 }; 663 664 struct tegra210_car_rst { 665 u_int set_reg; 666 u_int clr_reg; 667 u_int mask; 668 }; 669 670 static struct tegra210_car_reset_reg { 671 u_int set_reg; 672 u_int clr_reg; 673 } tegra210_car_reset_regs[] = { 674 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 675 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 676 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 677 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 678 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 679 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 680 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 681 }; 682 683 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 684 static void tegra210_car_reset_release(device_t, void *); 685 static int tegra210_car_reset_assert(device_t, void *); 686 static int tegra210_car_reset_deassert(device_t, void *); 687 688 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 689 .acquire = tegra210_car_reset_acquire, 690 .release = tegra210_car_reset_release, 691 .reset_assert = tegra210_car_reset_assert, 692 .reset_deassert = tegra210_car_reset_deassert, 693 }; 694 695 struct tegra210_car_softc { 696 device_t sc_dev; 697 bus_space_tag_t sc_bst; 698 bus_space_handle_t sc_bsh; 699 700 struct clk_domain sc_clkdom; 701 702 u_int sc_clock_cells; 703 u_int sc_reset_cells; 704 705 kmutex_t sc_rndlock; 706 krndsource_t sc_rndsource; 707 }; 708 709 static void tegra210_car_init(struct tegra210_car_softc *); 710 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 711 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 712 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 713 static void tegra210_car_parent_init(struct tegra210_car_softc *); 714 715 716 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 717 tegra210_car_match, tegra210_car_attach, NULL, NULL); 718 719 static int 720 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 721 { 722 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 723 struct fdt_attach_args * const faa = aux; 724 725 #if 0 726 return of_match_compatible(faa->faa_phandle, compatible); 727 #else 728 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 729 return 0; 730 731 return 999; 732 #endif 733 } 734 735 static void 736 tegra210_car_attach(device_t parent, device_t self, void *aux) 737 { 738 struct tegra210_car_softc * const sc = device_private(self); 739 struct fdt_attach_args * const faa = aux; 740 const int phandle = faa->faa_phandle; 741 bus_addr_t addr; 742 bus_size_t size; 743 int error, n; 744 745 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 746 aprint_error(": couldn't get registers\n"); 747 return; 748 } 749 750 sc->sc_dev = self; 751 sc->sc_bst = faa->faa_bst; 752 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 753 if (error) { 754 aprint_error(": couldn't map %#" PRIx64 ": %d", 755 (uint64_t)addr, error); 756 return; 757 } 758 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 759 sc->sc_clock_cells = 1; 760 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 761 sc->sc_reset_cells = 1; 762 763 aprint_naive("\n"); 764 aprint_normal(": CAR\n"); 765 766 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 767 sc->sc_clkdom.priv = sc; 768 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 769 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 770 771 fdtbus_register_clock_controller(self, phandle, 772 &tegra210_car_fdtclock_funcs); 773 fdtbus_register_reset_controller(self, phandle, 774 &tegra210_car_fdtreset_funcs); 775 776 tegra210_car_init(sc); 777 778 #ifdef TEGRA210_CAR_DEBUG 779 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 780 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 781 struct clk *clk_parent = clk_get_parent(clk); 782 device_printf(self, "clk %s (parent %s): ", clk->name, 783 clk_parent ? clk_parent->name : "none"); 784 printf("%u Hz\n", clk_get_rate(clk)); 785 } 786 #endif 787 } 788 789 static void 790 tegra210_car_init(struct tegra210_car_softc *sc) 791 { 792 tegra210_car_parent_init(sc); 793 tegra210_car_utmip_init(sc); 794 tegra210_car_xusb_init(sc); 795 tegra210_car_watchdog_init(sc); 796 } 797 798 static void 799 tegra210_car_parent_init(struct tegra210_car_softc *sc) 800 { 801 struct clk *clk, *clk_parent; 802 int error; 803 u_int n; 804 805 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 806 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 807 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 808 809 if (tegra210_init_parents[n].parent != NULL) { 810 clk_parent = clk_get(&sc->sc_clkdom, 811 tegra210_init_parents[n].parent); 812 KASSERT(clk_parent != NULL); 813 814 error = clk_set_parent(clk, clk_parent); 815 if (error) { 816 aprint_error_dev(sc->sc_dev, 817 "couldn't set '%s' parent to '%s': %d\n", 818 clk->name, clk_parent->name, error); 819 } 820 clk_put(clk_parent); 821 } 822 if (tegra210_init_parents[n].rate != 0) { 823 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 824 if (error) { 825 aprint_error_dev(sc->sc_dev, 826 "couldn't set '%s' rate to %u Hz: %d\n", 827 clk->name, tegra210_init_parents[n].rate, 828 error); 829 } 830 } 831 if (tegra210_init_parents[n].enable) { 832 error = clk_enable(clk); 833 if (error) { 834 aprint_error_dev(sc->sc_dev, 835 "couldn't enable '%s': %d\n", clk->name, 836 error); 837 } 838 } 839 clk_put(clk); 840 } 841 } 842 843 static void 844 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 845 { 846 bus_space_tag_t bst = sc->sc_bst; 847 bus_space_handle_t bsh = sc->sc_bsh; 848 849 /* 850 * Set up the UTMI PLL. 851 */ 852 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 853 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 854 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 855 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 856 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 857 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 858 delay(10); 859 /* TODO UTMIP_PLL_CFG0 */ 860 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 861 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 862 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 863 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 864 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 865 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 866 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 867 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 868 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 869 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 870 871 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI); 872 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE); 873 874 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 875 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 876 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 877 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI); 878 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE); 879 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK); 880 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 881 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 882 883 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 884 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 885 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 886 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 887 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 888 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 889 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 890 891 /* 892 * Set up UTMI PLL under hardware control 893 */ 894 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 895 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 896 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 897 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 898 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 899 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 900 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 901 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 902 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 903 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 904 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 905 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 906 delay(1); 907 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 908 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 909 } 910 911 static void 912 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 913 { 914 const bus_space_tag_t bst = sc->sc_bst; 915 const bus_space_handle_t bsh = sc->sc_bsh; 916 uint32_t val; 917 918 /* 919 * Set up the PLLU. 920 */ 921 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 922 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 923 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 924 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 925 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 926 delay(5); 927 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 928 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 929 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 930 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 931 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 932 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 933 do { 934 delay(2); 935 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 936 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 937 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 938 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 939 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 940 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 941 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 942 delay(2); 943 944 /* 945 * Now switch PLLU to hw controlled mode. 946 */ 947 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 948 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 949 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 950 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 951 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 952 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 953 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 954 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 955 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 956 delay(1); 957 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 958 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 959 delay(1); 960 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 961 962 /* 963 * Set up PLLREFE 964 */ 965 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 966 0, CAR_PLLREFE_MISC_IDDQ); 967 delay(5); 968 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 969 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 970 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 971 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 972 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 973 CAR_PLLREFE_BASE_DIVM | 974 CAR_PLLREFE_BASE_DIVN | 975 CAR_PLLREFE_BASE_DIVP | 976 CAR_PLLREFE_BASE_KCP); 977 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 978 CAR_PLLREFE_BASE_ENABLE, 0); 979 do { 980 delay(2); 981 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 982 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 983 984 /* 985 * Set up the PLLE. 986 */ 987 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 988 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 989 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 990 delay(5); 991 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 992 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 993 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 994 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 995 CAR_PLLE_BASE_DIVP_CML | 996 CAR_PLLE_BASE_DIVN | 997 CAR_PLLE_BASE_DIVM); 998 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 999 CAR_PLLE_MISC_PTS, 1000 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 1001 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 1002 do { 1003 delay(2); 1004 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 1005 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 1006 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 1007 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 1008 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 1009 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 1010 CAR_PLLE_SS_CNTL_SSCINC | 1011 CAR_PLLE_SS_CNTL_SSCINCINTRV | 1012 CAR_PLLE_SS_CNTL_SSCMAX | 1013 CAR_PLLE_SS_CNTL_SSCINVERT | 1014 CAR_PLLE_SS_CNTL_SSCCENTER | 1015 CAR_PLLE_SS_CNTL_BYPASS_SS | 1016 CAR_PLLE_SS_CNTL_SSCBYP); 1017 delay(1); 1018 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 1019 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 1020 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 1021 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 1022 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 1023 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 1024 delay(1); 1025 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 1026 1027 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 1028 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 1029 } 1030 1031 static void 1032 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 1033 { 1034 const bus_space_tag_t bst = sc->sc_bst; 1035 const bus_space_handle_t bsh = sc->sc_bsh; 1036 1037 /* Enable watchdog timer reset for system */ 1038 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 1039 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 1040 } 1041 1042 static struct tegra_clk * 1043 tegra210_car_clock_find(const char *name) 1044 { 1045 u_int n; 1046 1047 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 1048 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 1049 return &tegra210_car_clocks[n]; 1050 } 1051 } 1052 1053 return NULL; 1054 } 1055 1056 static struct tegra_clk * 1057 tegra210_car_clock_find_by_id(u_int clock_id) 1058 { 1059 u_int n; 1060 1061 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 1062 if (tegra210_car_clock_ids[n].id == clock_id) { 1063 const char *name = tegra210_car_clock_ids[n].name; 1064 return tegra210_car_clock_find(name); 1065 } 1066 } 1067 1068 return NULL; 1069 } 1070 1071 static struct clk * 1072 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 1073 { 1074 struct tegra210_car_softc * const sc = device_private(dev); 1075 struct tegra_clk *tclk; 1076 1077 if (len != sc->sc_clock_cells * 4) { 1078 return NULL; 1079 } 1080 1081 const u_int clock_id = be32dec(data); 1082 1083 tclk = tegra210_car_clock_find_by_id(clock_id); 1084 if (tclk) 1085 return TEGRA_CLK_BASE(tclk); 1086 1087 return NULL; 1088 } 1089 1090 static struct clk * 1091 tegra210_car_clock_get(void *priv, const char *name) 1092 { 1093 struct tegra_clk *tclk; 1094 1095 tclk = tegra210_car_clock_find(name); 1096 if (tclk == NULL) 1097 return NULL; 1098 1099 atomic_inc_uint(&tclk->refcnt); 1100 1101 return TEGRA_CLK_BASE(tclk); 1102 } 1103 1104 static void 1105 tegra210_car_clock_put(void *priv, struct clk *clk) 1106 { 1107 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1108 1109 KASSERT(tclk->refcnt > 0); 1110 1111 atomic_dec_uint(&tclk->refcnt); 1112 } 1113 1114 static u_int 1115 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1116 struct tegra_clk *tclk) 1117 { 1118 struct tegra_pll_clk *tpll = &tclk->u.pll; 1119 struct tegra_clk *tclk_parent; 1120 bus_space_tag_t bst = sc->sc_bst; 1121 bus_space_handle_t bsh = sc->sc_bsh; 1122 u_int divm, divn, divp; 1123 uint64_t rate; 1124 1125 KASSERT(tclk->type == TEGRA_CLK_PLL); 1126 1127 tclk_parent = tegra210_car_clock_find(tclk->parent); 1128 KASSERT(tclk_parent != NULL); 1129 1130 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1131 TEGRA_CLK_BASE(tclk_parent)); 1132 1133 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1134 divm = __SHIFTOUT(base, tpll->divm_mask); 1135 divn = __SHIFTOUT(base, tpll->divn_mask); 1136 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1137 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1138 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1139 /* XXX divp is not applied to PLLP's primary output */ 1140 divp = 0; 1141 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1142 divp = 0; 1143 divm *= __SHIFTOUT(base, tpll->divp_mask); 1144 } else { 1145 divp = __SHIFTOUT(base, tpll->divp_mask); 1146 } 1147 1148 rate = (uint64_t)rate_parent * divn; 1149 return rate / (divm << divp); 1150 } 1151 1152 static int 1153 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1154 struct tegra_clk *tclk, u_int rate) 1155 { 1156 struct tegra_pll_clk *tpll = &tclk->u.pll; 1157 bus_space_tag_t bst = sc->sc_bst; 1158 bus_space_handle_t bsh = sc->sc_bsh; 1159 struct clk *clk_parent; 1160 uint32_t bp, base; 1161 1162 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1163 if (clk_parent == NULL) 1164 return EIO; 1165 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1166 if (rate_parent == 0) 1167 return EIO; 1168 1169 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1170 const u_int divm = 1; 1171 const u_int divn = rate / rate_parent; 1172 const u_int divp = 0; 1173 1174 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1175 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1176 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1177 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1178 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1179 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1180 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1181 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1182 1183 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1184 base &= ~CAR_PLLX_BASE_DIVM; 1185 base &= ~CAR_PLLX_BASE_DIVN; 1186 base &= ~CAR_PLLX_BASE_DIVP; 1187 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1188 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1189 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1190 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1191 1192 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1193 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1194 do { 1195 delay(2); 1196 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1197 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1198 delay(100); 1199 1200 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1201 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1202 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1203 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1204 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1205 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1206 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1207 1208 return 0; 1209 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1210 const u_int divm = 1; 1211 const u_int pldiv = 1; 1212 const u_int divn = (rate << pldiv) / rate_parent; 1213 1214 /* Set frequency */ 1215 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1216 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1217 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1218 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1219 CAR_PLLD2_BASE_REF_SRC_SEL | 1220 CAR_PLLD2_BASE_DIVM | 1221 CAR_PLLD2_BASE_DIVN | 1222 CAR_PLLD2_BASE_DIVP); 1223 1224 return 0; 1225 } else { 1226 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1227 tclk->base.name, rate); 1228 /* TODO */ 1229 return EOPNOTSUPP; 1230 } 1231 } 1232 1233 static int 1234 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1235 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1236 { 1237 struct tegra_mux_clk *tmux = &tclk->u.mux; 1238 bus_space_tag_t bst = sc->sc_bst; 1239 bus_space_handle_t bsh = sc->sc_bsh; 1240 uint32_t v; 1241 u_int src; 1242 1243 KASSERT(tclk->type == TEGRA_CLK_MUX); 1244 1245 for (src = 0; src < tmux->nparents; src++) { 1246 if (tmux->parents[src] == NULL) { 1247 continue; 1248 } 1249 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1250 break; 1251 } 1252 } 1253 if (src == tmux->nparents) { 1254 return EINVAL; 1255 } 1256 1257 v = bus_space_read_4(bst, bsh, tmux->reg); 1258 v &= ~tmux->bits; 1259 v |= __SHIFTIN(src, tmux->bits); 1260 bus_space_write_4(bst, bsh, tmux->reg, v); 1261 1262 return 0; 1263 } 1264 1265 static struct tegra_clk * 1266 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1267 struct tegra_clk *tclk) 1268 { 1269 struct tegra_mux_clk *tmux = &tclk->u.mux; 1270 bus_space_tag_t bst = sc->sc_bst; 1271 bus_space_handle_t bsh = sc->sc_bsh; 1272 1273 KASSERT(tclk->type == TEGRA_CLK_MUX); 1274 1275 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1276 const u_int src = __SHIFTOUT(v, tmux->bits); 1277 1278 KASSERT(src < tmux->nparents); 1279 1280 if (tmux->parents[src] == NULL) { 1281 return NULL; 1282 } 1283 1284 return tegra210_car_clock_find(tmux->parents[src]); 1285 } 1286 1287 static u_int 1288 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1289 struct tegra_clk *tclk) 1290 { 1291 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1292 struct clk *clk_parent; 1293 1294 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1295 if (clk_parent == NULL) 1296 return 0; 1297 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1298 1299 return parent_rate / tfixed_div->div; 1300 } 1301 1302 static u_int 1303 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1304 struct tegra_clk *tclk) 1305 { 1306 struct tegra_div_clk *tdiv = &tclk->u.div; 1307 bus_space_tag_t bst = sc->sc_bst; 1308 bus_space_handle_t bsh = sc->sc_bsh; 1309 struct clk *clk_parent; 1310 u_int rate; 1311 1312 KASSERT(tclk->type == TEGRA_CLK_DIV); 1313 1314 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1315 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1316 1317 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1318 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1319 1320 switch (tdiv->reg) { 1321 case CAR_CLKSRC_I2C1_REG: 1322 case CAR_CLKSRC_I2C2_REG: 1323 case CAR_CLKSRC_I2C3_REG: 1324 case CAR_CLKSRC_I2C4_REG: 1325 case CAR_CLKSRC_I2C5_REG: 1326 case CAR_CLKSRC_I2C6_REG: 1327 rate = parent_rate / (raw_div + 1); 1328 break; 1329 case CAR_CLKSRC_UARTA_REG: 1330 case CAR_CLKSRC_UARTB_REG: 1331 case CAR_CLKSRC_UARTC_REG: 1332 case CAR_CLKSRC_UARTD_REG: 1333 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1334 rate = parent_rate / ((raw_div / 2) + 1); 1335 } else { 1336 rate = parent_rate; 1337 } 1338 break; 1339 case CAR_CLKSRC_SDMMC2_REG: 1340 case CAR_CLKSRC_SDMMC4_REG: 1341 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1342 case 1: 1343 case 2: 1344 case 5: 1345 raw_div = 0; /* ignore divisor for _LJ options */ 1346 break; 1347 } 1348 /* FALLTHROUGH */ 1349 default: 1350 rate = parent_rate / ((raw_div / 2) + 1); 1351 break; 1352 } 1353 1354 return rate; 1355 } 1356 1357 static int 1358 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1359 struct tegra_clk *tclk, u_int rate) 1360 { 1361 struct tegra_div_clk *tdiv = &tclk->u.div; 1362 bus_space_tag_t bst = sc->sc_bst; 1363 bus_space_handle_t bsh = sc->sc_bsh; 1364 struct clk *clk_parent; 1365 u_int raw_div; 1366 uint32_t v; 1367 1368 KASSERT(tclk->type == TEGRA_CLK_DIV); 1369 1370 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1371 if (clk_parent == NULL) 1372 return EINVAL; 1373 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1374 1375 v = bus_space_read_4(bst, bsh, tdiv->reg); 1376 1377 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1378 1379 switch (tdiv->reg) { 1380 case CAR_CLKSRC_UARTA_REG: 1381 case CAR_CLKSRC_UARTB_REG: 1382 case CAR_CLKSRC_UARTC_REG: 1383 case CAR_CLKSRC_UARTD_REG: 1384 if (rate == parent_rate) { 1385 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1386 } else if (rate) { 1387 v |= CAR_CLKSRC_UART_DIV_ENB; 1388 raw_div = (parent_rate / rate) * 2; 1389 if (raw_div >= 2) 1390 raw_div -= 2; 1391 } 1392 break; 1393 case CAR_CLKSRC_I2C1_REG: 1394 case CAR_CLKSRC_I2C2_REG: 1395 case CAR_CLKSRC_I2C3_REG: 1396 case CAR_CLKSRC_I2C4_REG: 1397 case CAR_CLKSRC_I2C5_REG: 1398 case CAR_CLKSRC_I2C6_REG: 1399 if (rate) 1400 raw_div = (parent_rate / rate) - 1; 1401 break; 1402 case CAR_CLKSRC_SDMMC1_REG: 1403 case CAR_CLKSRC_SDMMC2_REG: 1404 case CAR_CLKSRC_SDMMC3_REG: 1405 case CAR_CLKSRC_SDMMC4_REG: 1406 if (rate) { 1407 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1408 u_int calc_rate = 1409 parent_rate / ((raw_div / 2) + 1); 1410 if (calc_rate <= rate) 1411 break; 1412 } 1413 if (raw_div == 0x100) 1414 return EINVAL; 1415 } 1416 break; 1417 default: 1418 if (rate) { 1419 raw_div = (parent_rate / rate) * 2; 1420 if (raw_div >= 2) 1421 raw_div -= 2; 1422 } 1423 break; 1424 } 1425 1426 v &= ~tdiv->bits; 1427 v |= __SHIFTIN(raw_div, tdiv->bits); 1428 1429 bus_space_write_4(bst, bsh, tdiv->reg, v); 1430 1431 return 0; 1432 } 1433 1434 static int 1435 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1436 struct tegra_clk *tclk, bool enable) 1437 { 1438 struct tegra_gate_clk *tgate = &tclk->u.gate; 1439 bus_space_tag_t bst = sc->sc_bst; 1440 bus_space_handle_t bsh = sc->sc_bsh; 1441 bus_size_t reg; 1442 1443 KASSERT(tclk->type == TEGRA_CLK_GATE); 1444 1445 if (tgate->set_reg == tgate->clr_reg) { 1446 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1447 if (enable) { 1448 v |= tgate->bits; 1449 } else { 1450 v &= ~tgate->bits; 1451 } 1452 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1453 } else { 1454 if (enable) { 1455 reg = tgate->set_reg; 1456 } else { 1457 reg = tgate->clr_reg; 1458 } 1459 bus_space_write_4(bst, bsh, reg, tgate->bits); 1460 } 1461 1462 return 0; 1463 } 1464 1465 static u_int 1466 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1467 { 1468 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1469 struct clk *clk_parent; 1470 1471 switch (tclk->type) { 1472 case TEGRA_CLK_FIXED: 1473 return tclk->u.fixed.rate; 1474 case TEGRA_CLK_PLL: 1475 return tegra210_car_clock_get_rate_pll(priv, tclk); 1476 case TEGRA_CLK_MUX: 1477 case TEGRA_CLK_GATE: 1478 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1479 if (clk_parent == NULL) 1480 return EINVAL; 1481 return tegra210_car_clock_get_rate(priv, clk_parent); 1482 case TEGRA_CLK_FIXED_DIV: 1483 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1484 case TEGRA_CLK_DIV: 1485 return tegra210_car_clock_get_rate_div(priv, tclk); 1486 default: 1487 panic("tegra210: unknown tclk type %d", tclk->type); 1488 } 1489 } 1490 1491 static int 1492 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1493 { 1494 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1495 struct clk *clk_parent; 1496 1497 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1498 1499 switch (tclk->type) { 1500 case TEGRA_CLK_FIXED: 1501 case TEGRA_CLK_MUX: 1502 return EIO; 1503 case TEGRA_CLK_FIXED_DIV: 1504 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1505 if (clk_parent == NULL) 1506 return EIO; 1507 return tegra210_car_clock_set_rate(priv, clk_parent, 1508 rate * tclk->u.fixed_div.div); 1509 case TEGRA_CLK_GATE: 1510 return EINVAL; 1511 case TEGRA_CLK_PLL: 1512 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1513 case TEGRA_CLK_DIV: 1514 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1515 default: 1516 panic("tegra210: unknown tclk type %d", tclk->type); 1517 } 1518 } 1519 1520 static int 1521 tegra210_car_clock_enable(void *priv, struct clk *clk) 1522 { 1523 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1524 struct clk *clk_parent; 1525 1526 if (tclk->type != TEGRA_CLK_GATE) { 1527 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1528 if (clk_parent == NULL) 1529 return 0; 1530 return tegra210_car_clock_enable(priv, clk_parent); 1531 } 1532 1533 return tegra210_car_clock_enable_gate(priv, tclk, true); 1534 } 1535 1536 static int 1537 tegra210_car_clock_disable(void *priv, struct clk *clk) 1538 { 1539 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1540 1541 if (tclk->type != TEGRA_CLK_GATE) 1542 return EINVAL; 1543 1544 return tegra210_car_clock_enable_gate(priv, tclk, false); 1545 } 1546 1547 static int 1548 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1549 struct clk *clk_parent) 1550 { 1551 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1552 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1553 struct clk *nclk_parent; 1554 1555 if (tclk->type != TEGRA_CLK_MUX) { 1556 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1557 if (nclk_parent == clk_parent || nclk_parent == NULL) 1558 return EINVAL; 1559 return tegra210_car_clock_set_parent(priv, nclk_parent, 1560 clk_parent); 1561 } 1562 1563 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1564 } 1565 1566 static struct clk * 1567 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1568 { 1569 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1570 struct tegra_clk *tclk_parent = NULL; 1571 1572 switch (tclk->type) { 1573 case TEGRA_CLK_FIXED: 1574 case TEGRA_CLK_PLL: 1575 case TEGRA_CLK_FIXED_DIV: 1576 case TEGRA_CLK_DIV: 1577 case TEGRA_CLK_GATE: 1578 if (tclk->parent) { 1579 tclk_parent = tegra210_car_clock_find(tclk->parent); 1580 } 1581 break; 1582 case TEGRA_CLK_MUX: 1583 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1584 break; 1585 } 1586 1587 if (tclk_parent == NULL) 1588 return NULL; 1589 1590 return TEGRA_CLK_BASE(tclk_parent); 1591 } 1592 1593 static void * 1594 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1595 { 1596 struct tegra210_car_softc * const sc = device_private(dev); 1597 struct tegra210_car_rst *rst; 1598 1599 if (len != sc->sc_reset_cells * 4) 1600 return NULL; 1601 1602 const u_int reset_id = be32dec(data); 1603 1604 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1605 return NULL; 1606 1607 const u_int reg = reset_id / 32; 1608 1609 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1610 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1611 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1612 rst->mask = __BIT(reset_id % 32); 1613 1614 return rst; 1615 } 1616 1617 static void 1618 tegra210_car_reset_release(device_t dev, void *priv) 1619 { 1620 struct tegra210_car_rst *rst = priv; 1621 1622 kmem_free(rst, sizeof(*rst)); 1623 } 1624 1625 static int 1626 tegra210_car_reset_assert(device_t dev, void *priv) 1627 { 1628 struct tegra210_car_softc * const sc = device_private(dev); 1629 struct tegra210_car_rst *rst = priv; 1630 1631 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1632 1633 return 0; 1634 } 1635 1636 static int 1637 tegra210_car_reset_deassert(device_t dev, void *priv) 1638 { 1639 struct tegra210_car_softc * const sc = device_private(dev); 1640 struct tegra210_car_rst *rst = priv; 1641 1642 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1643 1644 return 0; 1645 } 1646 1647 void 1648 tegra210_car_xusbio_enable_hw_control(void) 1649 { 1650 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1651 KASSERT(dev != NULL); 1652 struct tegra210_car_softc * const sc = device_private(dev); 1653 bus_space_tag_t bst = sc->sc_bst; 1654 bus_space_handle_t bsh = sc->sc_bsh; 1655 1656 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1657 0, 1658 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1659 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1660 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1661 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1662 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1663 0); 1664 } 1665 1666 void 1667 tegra210_car_xusbio_enable_hw_seq(void) 1668 { 1669 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1670 KASSERT(dev != NULL); 1671 struct tegra210_car_softc * const sc = device_private(dev); 1672 bus_space_tag_t bst = sc->sc_bst; 1673 bus_space_handle_t bsh = sc->sc_bsh; 1674 1675 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1676 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1677 } 1678
Indexes created Tue Sep 30 20:09:53 GMT 2025