tegra210_car.c revision 1.19
1 /* $NetBSD: tegra210_car.c,v 1.19 2018/09/09 07:21:17 aymeric Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.19 2018/09/09 07:21:17 aymeric Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, int, const void *, 57 size_t); 58 59 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 60 .decode = tegra210_car_clock_decode 61 }; 62 63 /* DT clock ID to clock name mappings */ 64 static struct tegra210_car_clock_id { 65 const char *name; 66 u_int id; 67 } tegra210_car_clock_ids[] = { 68 { "ISPB", 3 }, 69 { "RTC", 4 }, 70 { "TIMER", 5 }, 71 { "UARTA", 6 }, 72 { "GPIO", 8 }, 73 { "SDMMC2", 9 }, 74 { "I2S1", 11 }, 75 { "I2C1", 12 }, 76 { "SDMMC1", 14 }, 77 { "SDMMC4", 15 }, 78 { "PWM", 17 }, 79 { "I2S2", 18 }, 80 { "USBD", 22 }, 81 { "ISP", 23 }, 82 { "DISP2", 26 }, 83 { "DISP1", 27 }, 84 { "HOST1X", 28 }, 85 { "I2S0", 30 }, 86 { "MC", 32 }, 87 { "AHBDMA", 33 }, 88 { "APBDMA", 34 }, 89 { "PMC", 38 }, 90 { "KFUSE", 40 }, 91 { "SBC1", 41 }, 92 { "SBC2", 44 }, 93 { "SBC3", 46 }, 94 { "I2C5", 47 }, 95 { "DSIA", 48 }, 96 { "CSI", 52 }, 97 { "I2C2", 54 }, 98 { "UARTC", 55 }, 99 { "MIPI_CAL", 56 }, 100 { "EMC", 57 }, 101 { "USB2", 58 }, 102 { "BSEV", 63 }, 103 { "UARTD", 65 }, 104 { "I2C3", 67 }, 105 { "SBC4", 68 }, 106 { "SDMMC3", 69 }, 107 { "PCIE", 70 }, 108 { "OWR", 71 }, 109 { "AFI", 72 }, 110 { "CSITE", 73 }, 111 { "SOC_THERM", 78 }, 112 { "DTV", 79 }, 113 { "I2CSLOW", 81 }, 114 { "DSIB", 82 }, 115 { "TSEC", 83 }, 116 { "XUSB_HOST", 89 }, 117 { "CSUS", 92 }, 118 { "MSELECT", 99 }, 119 { "TSENSOR", 100 }, 120 { "I2S3", 101 }, 121 { "I2S4", 102 }, 122 { "I2C4", 103 }, 123 { "D_AUDIO", 106 }, 124 { "APB2APE", 107 }, 125 { "HDA2CODEC_2X", 111 }, 126 { "SPDIF_2X", 118 }, 127 { "ACTMON", 119 }, 128 { "EXTERN1", 120 }, 129 { "EXTERN2", 121 }, 130 { "EXTERN3", 122 }, 131 { "SATA_OOB", 123 }, 132 { "SATA", 124 }, 133 { "HDA", 125 }, 134 { "HDA2HDMI", 128 }, 135 { "XUSB_GATE", 143 }, 136 { "CILAB", 144 }, 137 { "CILCD", 145 }, 138 { "CILE", 146 }, 139 { "DSIALP", 147 }, 140 { "DSIBLP", 148 }, 141 { "ENTROPY", 149 }, 142 { "XUSB_SS", 156 }, 143 { "DMIC1", 161 }, 144 { "DMIC2", 162 }, 145 { "I2C6", 166 }, 146 { "VIM2_CLK", 171 }, 147 { "MIPIBIF", 173 }, 148 { "CLK72MHZ", 177 }, 149 { "VIC03", 178 }, 150 { "DPAUX", 181 }, 151 { "SOR0", 182 }, 152 { "SOR1", 183 }, 153 { "GPU", 184 }, 154 { "DBGAPB", 185 }, 155 { "PLL_P_OUT_ADSP", 187 }, 156 { "PLL_G_REF", 189 }, 157 { "SDMMC_LEGACY", 193 }, 158 { "NVDEC", 194 }, 159 { "NVJPG", 195 }, 160 { "DMIC3", 197 }, 161 { "APE", 198 }, 162 { "MAUD", 202 }, 163 { "TSECB", 206 }, 164 { "DPAUX1", 207 }, 165 { "VI_I2C", 208 }, 166 { "HSIC_TRK", 209 }, 167 { "USB2_TRK", 210 }, 168 { "QSPI", 211 }, 169 { "UARTAPE", 212 }, 170 { "NVENC", 219 }, 171 { "SOR_SAFE", 222 }, 172 { "PLL_P_OUT_CPU", 223 }, 173 { "UARTB", 224 }, 174 { "VFIR", 225 }, 175 { "SPDIF_IN", 226 }, 176 { "SPDIF_OUT", 227 }, 177 { "VI", 228 }, 178 { "VI_SENSOR", 229 }, 179 { "FUSE", 230 }, 180 { "FUSE_BURN", 231 }, 181 { "CLK_32K", 232 }, 182 { "CLK_M", 233 }, 183 { "CLK_M_DIV2", 234 }, 184 { "CLK_M_DIV4", 235 }, 185 { "PLL_REF", 236 }, 186 { "PLL_C", 237 }, 187 { "PLL_C_OUT1", 238 }, 188 { "PLL_C2", 239 }, 189 { "PLL_C3", 240 }, 190 { "PLL_M", 241 }, 191 { "PLL_M_OUT1", 242 }, 192 { "PLL_P", 243 }, 193 { "PLL_P_OUT1", 244 }, 194 { "PLL_P_OUT2", 245 }, 195 { "PLL_P_OUT3", 246 }, 196 { "PLL_P_OUT4", 247 }, 197 { "PLL_A", 248 }, 198 { "PLL_A_OUT0", 249 }, 199 { "PLL_D", 250 }, 200 { "PLL_D_OUT0", 251 }, 201 { "PLL_D2", 252 }, 202 { "PLL_D2_OUT0", 253 }, 203 { "PLL_U", 254 }, 204 { "PLL_U_480M", 255 }, 205 { "PLL_U_60M", 256 }, 206 { "PLL_U_48M", 257 }, 207 { "PLL_X", 259 }, 208 { "PLL_X_OUT0", 260 }, 209 { "PLL_RE_VCO", 261 }, 210 { "PLL_RE_OUT", 262 }, 211 { "PLL_E", 263 }, 212 { "SPDIF_IN_SYNC", 264 }, 213 { "I2S0_SYNC", 265 }, 214 { "I2S1_SYNC", 266 }, 215 { "I2S2_SYNC", 267 }, 216 { "I2S3_SYNC", 268 }, 217 { "I2S4_SYNC", 269 }, 218 { "VIMCLK_SYNC", 270 }, 219 { "AUDIO0", 271 }, 220 { "AUDIO1", 272 }, 221 { "AUDIO2", 273 }, 222 { "AUDIO3", 274 }, 223 { "AUDIO4", 275 }, 224 { "SPDIF", 276 }, 225 { "CLK_OUT_1", 277 }, 226 { "CLK_OUT_2", 278 }, 227 { "CLK_OUT_3", 279 }, 228 { "BLINK", 280 }, 229 { "SOR1_SRC", 282 }, 230 { "XUSB_HOST_SRC", 284 }, 231 { "XUSB_FALCON_SRC", 285 }, 232 { "XUSB_FS_SRC", 286 }, 233 { "XUSB_SS_SRC", 287 }, 234 { "XUSB_DEV_SRC", 288 }, 235 { "XUSB_DEV", 289 }, 236 { "XUSB_HS_SRC", 290 }, 237 { "SCLK", 291 }, 238 { "HCLK", 292 }, 239 { "PCLK", 293 }, 240 { "CCLK_G", 294 }, 241 { "CCLK_LP", 295 }, 242 { "DFLL_REF", 296 }, 243 { "DFLL_SOC", 297 }, 244 { "VI_SENSOR2", 298 }, 245 { "PLL_P_OUT5", 299 }, 246 { "CML0", 300 }, 247 { "CML1", 301 }, 248 { "PLL_C4", 302 }, 249 { "PLL_DP", 303 }, 250 { "PLL_E_MUX", 304 }, 251 { "PLL_MB", 305 }, 252 { "PLL_A1", 306 }, 253 { "PLL_D_DSI_OUT", 307 }, 254 { "PLL_C4_OUT0", 308 }, 255 { "PLL_C4_OUT1", 309 }, 256 { "PLL_C4_OUT2", 310 }, 257 { "PLL_C4_OUT3", 311 }, 258 { "PLL_U_OUT", 312 }, 259 { "PLL_U_OUT1", 313 }, 260 { "PLL_U_OUT2", 314 }, 261 { "USB2_HSIC_TRK", 315 }, 262 { "PLL_P_OUT_HSIO", 316 }, 263 { "PLL_P_OUT_XUSB", 317 }, 264 { "XUSB_SSP_SRC", 318 }, 265 { "PLL_RE_OUT1", 319 }, 266 { "AUDIO0_MUX", 350 }, 267 { "AUDIO1_MUX", 351 }, 268 { "AUDIO2_MUX", 352 }, 269 { "AUDIO3_MUX", 353 }, 270 { "AUDIO4_MUX", 354 }, 271 { "SPDIF_MUX", 355 }, 272 { "CLK_OUT_1_MUX", 356 }, 273 { "CLK_OUT_2_MUX", 357 }, 274 { "CLK_OUT_3_MUX", 358 }, 275 { "DSIA_MUX", 359 }, 276 { "DSIB_MUX", 360 }, 277 { "SOR0_LVDS", 361 }, 278 { "XUSB_SS_DIV2", 362 }, 279 { "PLL_M_UD", 363 }, 280 { "PLL_C_UD", 364 }, 281 { "SCLK_MUX", 365 }, 282 }; 283 284 static struct clk *tegra210_car_clock_get(void *, const char *); 285 static void tegra210_car_clock_put(void *, struct clk *); 286 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 287 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 288 static int tegra210_car_clock_enable(void *, struct clk *); 289 static int tegra210_car_clock_disable(void *, struct clk *); 290 static int tegra210_car_clock_set_parent(void *, struct clk *, 291 struct clk *); 292 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 293 294 static const struct clk_funcs tegra210_car_clock_funcs = { 295 .get = tegra210_car_clock_get, 296 .put = tegra210_car_clock_put, 297 .get_rate = tegra210_car_clock_get_rate, 298 .set_rate = tegra210_car_clock_set_rate, 299 .enable = tegra210_car_clock_enable, 300 .disable = tegra210_car_clock_disable, 301 .set_parent = tegra210_car_clock_set_parent, 302 .get_parent = tegra210_car_clock_get_parent, 303 }; 304 305 #define CLK_FIXED(_name, _rate) { \ 306 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 307 .u = { .fixed = { .rate = (_rate) } } \ 308 } 309 310 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 311 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 312 .parent = (_parent), \ 313 .u = { \ 314 .pll = { \ 315 .base_reg = (_base), \ 316 .divm_mask = (_divm), \ 317 .divn_mask = (_divn), \ 318 .divp_mask = (_divp), \ 319 } \ 320 } \ 321 } 322 323 #define CLK_MUX(_name, _reg, _bits, _p) { \ 324 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 325 .u = { \ 326 .mux = { \ 327 .nparents = __arraycount(_p), \ 328 .parents = (_p), \ 329 .reg = (_reg), \ 330 .bits = (_bits) \ 331 } \ 332 } \ 333 } 334 335 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 336 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 337 .parent = (_parent), \ 338 .u = { \ 339 .fixed_div = { \ 340 .div = (_div) \ 341 } \ 342 } \ 343 } 344 345 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 346 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 347 .parent = (_parent), \ 348 .u = { \ 349 .div = { \ 350 .reg = (_reg), \ 351 .bits = (_bits) \ 352 } \ 353 } \ 354 } 355 356 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 357 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 358 .type = TEGRA_CLK_GATE, \ 359 .parent = (_parent), \ 360 .u = { \ 361 .gate = { \ 362 .set_reg = (_set), \ 363 .clr_reg = (_clr), \ 364 .bits = (_bits), \ 365 } \ 366 } \ 367 } 368 369 #define CLK_GATE_L(_name, _parent, _bits) \ 370 CLK_GATE(_name, _parent, \ 371 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 372 _bits) 373 374 #define CLK_GATE_H(_name, _parent, _bits) \ 375 CLK_GATE(_name, _parent, \ 376 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 377 _bits) 378 379 #define CLK_GATE_U(_name, _parent, _bits) \ 380 CLK_GATE(_name, _parent, \ 381 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 382 _bits) 383 384 #define CLK_GATE_V(_name, _parent, _bits) \ 385 CLK_GATE(_name, _parent, \ 386 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 387 _bits) 388 389 #define CLK_GATE_W(_name, _parent, _bits) \ 390 CLK_GATE(_name, _parent, \ 391 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 392 _bits) 393 394 #define CLK_GATE_X(_name, _parent, _bits) \ 395 CLK_GATE(_name, _parent, \ 396 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 397 _bits) 398 399 #define CLK_GATE_Y(_name, _parent, _bits) \ 400 CLK_GATE(_name, _parent, \ 401 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 402 _bits) 403 404 405 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 406 CLK_GATE(_name, _parent, _reg, _reg, _bits) 407 408 static const char *mux_uart_p[] = 409 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 410 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 411 412 static const char *mux_sdmmc1_p[] = 413 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 414 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 415 416 static const char *mux_sdmmc2_4_p[] = 417 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 418 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 419 420 static const char *mux_sdmmc3_p[] = 421 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 422 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 423 424 static const char *mux_i2c_p[] = 425 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 426 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 427 428 static const char *mux_xusb_host_p[] = 429 { "CLK_M", "PLL_P", NULL, NULL, 430 NULL, "PLL_REF", NULL, NULL }; 431 432 static const char *mux_xusb_fs_p[] = 433 { "CLK_M", NULL, "PLL_U_48M", NULL, 434 "PLL_P", NULL, "PLL_U_480M", NULL }; 435 436 static const char *mux_xusb_ss_p[] = 437 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 438 NULL, NULL, NULL, NULL }; 439 440 static const char *mux_mselect_p[] = 441 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT2", 442 "PLL_C4_OUT1", "CLK_S", "CLK_M", "PLL_C4_OUT0" }; 443 444 static const char *mux_tsensor_p[] = 445 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 446 "CLK_M", "PLL_C4_OUT1", "CLK_S", "PLL_C4_OUT2" }; 447 448 static const char *mux_soc_therm_p[] = 449 { "CLK_M", "PLL_C", "PLL_P", "PLL_A", 450 "PLL_C2", "PLL_C4_OUT0", "PLL_C4_OUT1", "PLL_C4_OUT2" }; 451 452 static const char *mux_hda2codec_2x_p[] = 453 { "PLL_P", "PLL_C2", "PLL_C4_OUT0", "PLL_A", 454 "PLL_A", "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 455 456 static const char *mux_hda_p[] = 457 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 458 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 459 460 static struct tegra_clk tegra210_car_clocks[] = { 461 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 462 463 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 464 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 465 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 466 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 467 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 468 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 469 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 470 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 471 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 472 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 473 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 474 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 475 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 476 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 477 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 478 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 479 480 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 481 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 482 483 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 484 mux_uart_p), 485 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 486 mux_uart_p), 487 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 488 mux_uart_p), 489 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 490 mux_uart_p), 491 492 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 493 mux_sdmmc1_p), 494 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 495 mux_sdmmc2_4_p), 496 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 497 mux_sdmmc3_p), 498 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 499 mux_sdmmc2_4_p), 500 501 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 502 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 503 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 504 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 505 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 506 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 507 508 CLK_MUX("MUX_XUSB_HOST", 509 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 510 mux_xusb_host_p), 511 CLK_MUX("MUX_XUSB_FALCON", 512 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 513 mux_xusb_host_p), 514 CLK_MUX("MUX_XUSB_SS", 515 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 516 mux_xusb_ss_p), 517 CLK_MUX("MUX_XUSB_FS", 518 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 519 mux_xusb_fs_p), 520 521 CLK_MUX("MUX_MSELECT", 522 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 523 mux_mselect_p), 524 525 CLK_MUX("MUX_TSENSOR", 526 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 527 mux_tsensor_p), 528 CLK_MUX("MUX_SOC_THERM", 529 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 530 mux_soc_therm_p), 531 532 CLK_MUX("MUX_HDA2CODEC_2X", 533 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 534 mux_hda2codec_2x_p), 535 CLK_MUX("MUX_HDA", 536 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, 537 mux_hda_p), 538 539 CLK_DIV("DIV_UARTA", "MUX_UARTA", 540 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 541 CLK_DIV("DIV_UARTB", "MUX_UARTB", 542 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 543 CLK_DIV("DIV_UARTC", "MUX_UARTC", 544 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 545 CLK_DIV("DIV_UARTD", "MUX_UARTD", 546 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 547 548 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 549 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 550 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 551 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 552 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 553 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 554 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 555 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 556 557 CLK_DIV("DIV_I2C1", "MUX_I2C1", 558 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 559 CLK_DIV("DIV_I2C2", "MUX_I2C2", 560 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 561 CLK_DIV("DIV_I2C3", "MUX_I2C3", 562 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 563 CLK_DIV("DIV_I2C4", "MUX_I2C4", 564 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 565 CLK_DIV("DIV_I2C5", "MUX_I2C5", 566 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 567 CLK_DIV("DIV_I2C6", "MUX_I2C6", 568 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 569 570 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 571 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 572 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 573 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 574 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 575 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 576 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 577 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 578 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 579 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 580 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 581 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 582 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 583 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 584 585 CLK_DIV("DIV_MSELECT", "MUX_MSELECT", 586 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 587 588 CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR", 589 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 590 CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM", 591 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 592 593 CLK_DIV("DIV_HDA2CODEC_2X", "MUX_HDA2CODEC_2X", 594 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 595 CLK_DIV("DIV_HDA", "MUX_HDA", 596 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 597 598 CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 599 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 600 CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 601 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 602 603 CLK_GATE_SIMPLE("CML0", "PLL_E", 604 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 605 CLK_GATE_SIMPLE("CML1", "PLL_E", 606 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 607 608 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 609 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 610 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 611 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 612 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 613 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 614 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 615 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 616 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 617 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 618 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 619 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 620 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 621 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 622 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 623 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 624 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 625 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 626 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 627 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 628 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 629 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 630 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 631 CLK_GATE_V("MSELECT", "DIV_MSELECT", CAR_DEV_V_MSELECT), 632 CLK_GATE_U("PCIE", "CLK_M", CAR_DEV_U_PCIE), 633 CLK_GATE_U("AFI", "MSELECT", CAR_DEV_U_AFI), 634 CLK_GATE_V("TSENSOR", "DIV_TSENSOR", CAR_DEV_V_TSENSOR), 635 CLK_GATE_U("SOC_THERM", "DIV_SOC_THERM", CAR_DEV_U_SOC_THERM), 636 CLK_GATE_W("HDA2HDMI", "CLK_M", CAR_DEV_W_HDA2HDMICODEC), 637 CLK_GATE_V("HDA2CODEC_2X", "DIV_HDA2CODEC_2X", CAR_DEV_V_HDA2CODEC_2X), 638 CLK_GATE_V("HDA", "DIV_HDA", CAR_DEV_V_HDA), 639 }; 640 641 struct tegra210_init_parent { 642 const char *clock; 643 const char *parent; 644 u_int rate; 645 u_int enable; 646 } tegra210_init_parents[] = { 647 { "SDMMC1", "PLL_P", 0, 0 }, 648 { "SDMMC2", "PLL_P", 0, 0 }, 649 { "SDMMC3", "PLL_P", 0, 0 }, 650 { "SDMMC4", "PLL_P", 0, 0 }, 651 { "SOC_THERM", "PLL_P", 0, 0 }, 652 { "TSENSOR", "CLK_M", 0, 0 }, 653 { "XUSB_GATE", NULL, 0, 1 }, 654 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 655 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 656 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 657 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 658 { "PLL_U_OUT1", NULL, 48000000, 1 }, 659 { "PLL_U_OUT2", NULL, 60000000, 1 }, 660 { "CML0", NULL, 0, 1 }, 661 { "AFI", NULL, 0, 1 }, 662 { "PCIE", NULL, 0, 1 }, 663 }; 664 665 struct tegra210_car_rst { 666 u_int set_reg; 667 u_int clr_reg; 668 u_int mask; 669 }; 670 671 static struct tegra210_car_reset_reg { 672 u_int set_reg; 673 u_int clr_reg; 674 } tegra210_car_reset_regs[] = { 675 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 676 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 677 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 678 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 679 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 680 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 681 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 682 }; 683 684 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 685 static void tegra210_car_reset_release(device_t, void *); 686 static int tegra210_car_reset_assert(device_t, void *); 687 static int tegra210_car_reset_deassert(device_t, void *); 688 689 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 690 .acquire = tegra210_car_reset_acquire, 691 .release = tegra210_car_reset_release, 692 .reset_assert = tegra210_car_reset_assert, 693 .reset_deassert = tegra210_car_reset_deassert, 694 }; 695 696 struct tegra210_car_softc { 697 device_t sc_dev; 698 bus_space_tag_t sc_bst; 699 bus_space_handle_t sc_bsh; 700 701 struct clk_domain sc_clkdom; 702 703 u_int sc_clock_cells; 704 u_int sc_reset_cells; 705 706 kmutex_t sc_rndlock; 707 krndsource_t sc_rndsource; 708 }; 709 710 static void tegra210_car_init(struct tegra210_car_softc *); 711 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 712 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 713 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 714 static void tegra210_car_parent_init(struct tegra210_car_softc *); 715 716 717 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 718 tegra210_car_match, tegra210_car_attach, NULL, NULL); 719 720 static int 721 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 722 { 723 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 724 struct fdt_attach_args * const faa = aux; 725 726 #if 0 727 return of_match_compatible(faa->faa_phandle, compatible); 728 #else 729 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 730 return 0; 731 732 return 999; 733 #endif 734 } 735 736 static void 737 tegra210_car_attach(device_t parent, device_t self, void *aux) 738 { 739 struct tegra210_car_softc * const sc = device_private(self); 740 struct fdt_attach_args * const faa = aux; 741 const int phandle = faa->faa_phandle; 742 bus_addr_t addr; 743 bus_size_t size; 744 int error, n; 745 746 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 747 aprint_error(": couldn't get registers\n"); 748 return; 749 } 750 751 sc->sc_dev = self; 752 sc->sc_bst = faa->faa_bst; 753 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 754 if (error) { 755 aprint_error(": couldn't map %#" PRIx64 ": %d", 756 (uint64_t)addr, error); 757 return; 758 } 759 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 760 sc->sc_clock_cells = 1; 761 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 762 sc->sc_reset_cells = 1; 763 764 aprint_naive("\n"); 765 aprint_normal(": CAR\n"); 766 767 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 768 sc->sc_clkdom.priv = sc; 769 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 770 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 771 772 fdtbus_register_clock_controller(self, phandle, 773 &tegra210_car_fdtclock_funcs); 774 fdtbus_register_reset_controller(self, phandle, 775 &tegra210_car_fdtreset_funcs); 776 777 tegra210_car_init(sc); 778 779 #ifdef TEGRA210_CAR_DEBUG 780 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 781 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 782 struct clk *clk_parent = clk_get_parent(clk); 783 device_printf(self, "clk %s (parent %s): ", clk->name, 784 clk_parent ? clk_parent->name : "none"); 785 printf("%u Hz\n", clk_get_rate(clk)); 786 } 787 #endif 788 } 789 790 static void 791 tegra210_car_init(struct tegra210_car_softc *sc) 792 { 793 tegra210_car_parent_init(sc); 794 tegra210_car_utmip_init(sc); 795 tegra210_car_xusb_init(sc); 796 tegra210_car_watchdog_init(sc); 797 } 798 799 static void 800 tegra210_car_parent_init(struct tegra210_car_softc *sc) 801 { 802 struct clk *clk, *clk_parent; 803 int error; 804 u_int n; 805 806 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 807 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 808 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 809 810 if (tegra210_init_parents[n].parent != NULL) { 811 clk_parent = clk_get(&sc->sc_clkdom, 812 tegra210_init_parents[n].parent); 813 KASSERT(clk_parent != NULL); 814 815 error = clk_set_parent(clk, clk_parent); 816 if (error) { 817 aprint_error_dev(sc->sc_dev, 818 "couldn't set '%s' parent to '%s': %d\n", 819 clk->name, clk_parent->name, error); 820 } 821 clk_put(clk_parent); 822 } 823 if (tegra210_init_parents[n].rate != 0) { 824 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 825 if (error) { 826 aprint_error_dev(sc->sc_dev, 827 "couldn't set '%s' rate to %u Hz: %d\n", 828 clk->name, tegra210_init_parents[n].rate, 829 error); 830 } 831 } 832 if (tegra210_init_parents[n].enable) { 833 error = clk_enable(clk); 834 if (error) { 835 aprint_error_dev(sc->sc_dev, 836 "couldn't enable '%s': %d\n", clk->name, 837 error); 838 } 839 } 840 clk_put(clk); 841 } 842 } 843 844 static void 845 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 846 { 847 bus_space_tag_t bst = sc->sc_bst; 848 bus_space_handle_t bsh = sc->sc_bsh; 849 850 /* 851 * Set up the UTMI PLL. 852 */ 853 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 854 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 855 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 856 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 857 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 858 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 859 delay(10); 860 /* TODO UTMIP_PLL_CFG0 */ 861 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 862 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 863 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 864 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 865 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 866 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 867 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 868 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 869 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 870 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 871 872 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI); 873 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE); 874 875 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 876 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 877 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 878 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI); 879 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE); 880 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK); 881 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 882 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 883 884 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 885 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 886 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 887 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 888 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 889 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 890 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 891 892 /* 893 * Set up UTMI PLL under hardware control 894 */ 895 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 896 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 897 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 898 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 899 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 900 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 901 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 902 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 903 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 904 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 905 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 906 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 907 delay(1); 908 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 909 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 910 } 911 912 static void 913 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 914 { 915 const bus_space_tag_t bst = sc->sc_bst; 916 const bus_space_handle_t bsh = sc->sc_bsh; 917 uint32_t val; 918 919 /* 920 * Set up the PLLU. 921 */ 922 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 923 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 924 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 925 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 926 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 927 delay(5); 928 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 929 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 930 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 931 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 932 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 933 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 934 do { 935 delay(2); 936 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 937 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 938 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 939 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 940 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 941 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 942 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 943 delay(2); 944 945 /* 946 * Now switch PLLU to hw controlled mode. 947 */ 948 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 949 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 950 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 951 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 952 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 953 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 954 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 955 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 956 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 957 delay(1); 958 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 959 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 960 delay(1); 961 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 962 963 /* 964 * Set up PLLREFE 965 */ 966 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 967 0, CAR_PLLREFE_MISC_IDDQ); 968 delay(5); 969 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 970 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 971 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 972 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 973 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 974 CAR_PLLREFE_BASE_DIVM | 975 CAR_PLLREFE_BASE_DIVN | 976 CAR_PLLREFE_BASE_DIVP | 977 CAR_PLLREFE_BASE_KCP); 978 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 979 CAR_PLLREFE_BASE_ENABLE, 0); 980 do { 981 delay(2); 982 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 983 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 984 985 /* 986 * Set up the PLLE. 987 */ 988 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 989 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 990 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 991 delay(5); 992 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 993 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 994 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 995 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 996 CAR_PLLE_BASE_DIVP_CML | 997 CAR_PLLE_BASE_DIVN | 998 CAR_PLLE_BASE_DIVM); 999 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 1000 CAR_PLLE_MISC_PTS, 1001 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 1002 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 1003 do { 1004 delay(2); 1005 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 1006 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 1007 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 1008 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 1009 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 1010 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 1011 CAR_PLLE_SS_CNTL_SSCINC | 1012 CAR_PLLE_SS_CNTL_SSCINCINTRV | 1013 CAR_PLLE_SS_CNTL_SSCMAX | 1014 CAR_PLLE_SS_CNTL_SSCINVERT | 1015 CAR_PLLE_SS_CNTL_SSCCENTER | 1016 CAR_PLLE_SS_CNTL_BYPASS_SS | 1017 CAR_PLLE_SS_CNTL_SSCBYP); 1018 delay(1); 1019 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 1020 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 1021 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 1022 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 1023 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 1024 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 1025 delay(1); 1026 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 1027 1028 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 1029 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 1030 } 1031 1032 static void 1033 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 1034 { 1035 const bus_space_tag_t bst = sc->sc_bst; 1036 const bus_space_handle_t bsh = sc->sc_bsh; 1037 1038 /* Enable watchdog timer reset for system */ 1039 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 1040 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 1041 } 1042 1043 static struct tegra_clk * 1044 tegra210_car_clock_find(const char *name) 1045 { 1046 u_int n; 1047 1048 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 1049 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 1050 return &tegra210_car_clocks[n]; 1051 } 1052 } 1053 1054 return NULL; 1055 } 1056 1057 static struct tegra_clk * 1058 tegra210_car_clock_find_by_id(u_int clock_id) 1059 { 1060 u_int n; 1061 1062 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 1063 if (tegra210_car_clock_ids[n].id == clock_id) { 1064 const char *name = tegra210_car_clock_ids[n].name; 1065 return tegra210_car_clock_find(name); 1066 } 1067 } 1068 1069 return NULL; 1070 } 1071 1072 static struct clk * 1073 tegra210_car_clock_decode(device_t dev, int cc_phandle, const void *data, 1074 size_t len) 1075 { 1076 struct tegra210_car_softc * const sc = device_private(dev); 1077 struct tegra_clk *tclk; 1078 1079 if (len != sc->sc_clock_cells * 4) { 1080 return NULL; 1081 } 1082 1083 const u_int clock_id = be32dec(data); 1084 1085 tclk = tegra210_car_clock_find_by_id(clock_id); 1086 if (tclk) 1087 return TEGRA_CLK_BASE(tclk); 1088 1089 return NULL; 1090 } 1091 1092 static struct clk * 1093 tegra210_car_clock_get(void *priv, const char *name) 1094 { 1095 struct tegra_clk *tclk; 1096 1097 tclk = tegra210_car_clock_find(name); 1098 if (tclk == NULL) 1099 return NULL; 1100 1101 atomic_inc_uint(&tclk->refcnt); 1102 1103 return TEGRA_CLK_BASE(tclk); 1104 } 1105 1106 static void 1107 tegra210_car_clock_put(void *priv, struct clk *clk) 1108 { 1109 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1110 1111 KASSERT(tclk->refcnt > 0); 1112 1113 atomic_dec_uint(&tclk->refcnt); 1114 } 1115 1116 static u_int 1117 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1118 struct tegra_clk *tclk) 1119 { 1120 struct tegra_pll_clk *tpll = &tclk->u.pll; 1121 struct tegra_clk *tclk_parent; 1122 bus_space_tag_t bst = sc->sc_bst; 1123 bus_space_handle_t bsh = sc->sc_bsh; 1124 u_int divm, divn, divp; 1125 uint64_t rate; 1126 1127 KASSERT(tclk->type == TEGRA_CLK_PLL); 1128 1129 tclk_parent = tegra210_car_clock_find(tclk->parent); 1130 KASSERT(tclk_parent != NULL); 1131 1132 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1133 TEGRA_CLK_BASE(tclk_parent)); 1134 1135 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1136 divm = __SHIFTOUT(base, tpll->divm_mask); 1137 divn = __SHIFTOUT(base, tpll->divn_mask); 1138 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1139 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1140 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1141 /* XXX divp is not applied to PLLP's primary output */ 1142 divp = 0; 1143 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1144 divp = 0; 1145 divm *= __SHIFTOUT(base, tpll->divp_mask); 1146 } else { 1147 divp = __SHIFTOUT(base, tpll->divp_mask); 1148 } 1149 1150 rate = (uint64_t)rate_parent * divn; 1151 return rate / (divm << divp); 1152 } 1153 1154 static int 1155 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1156 struct tegra_clk *tclk, u_int rate) 1157 { 1158 struct tegra_pll_clk *tpll = &tclk->u.pll; 1159 bus_space_tag_t bst = sc->sc_bst; 1160 bus_space_handle_t bsh = sc->sc_bsh; 1161 struct clk *clk_parent; 1162 uint32_t bp, base; 1163 1164 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1165 if (clk_parent == NULL) 1166 return EIO; 1167 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1168 if (rate_parent == 0) 1169 return EIO; 1170 1171 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1172 const u_int divm = 1; 1173 const u_int divn = rate / rate_parent; 1174 const u_int divp = 0; 1175 1176 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1177 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1178 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1179 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1180 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1181 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1182 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1183 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1184 1185 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1186 base &= ~CAR_PLLX_BASE_DIVM; 1187 base &= ~CAR_PLLX_BASE_DIVN; 1188 base &= ~CAR_PLLX_BASE_DIVP; 1189 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1190 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1191 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1192 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1193 1194 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1195 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1196 do { 1197 delay(2); 1198 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1199 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1200 delay(100); 1201 1202 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1203 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1204 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1205 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1206 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1207 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1208 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1209 1210 return 0; 1211 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1212 const u_int divm = 1; 1213 const u_int pldiv = 1; 1214 const u_int divn = (rate << pldiv) / rate_parent; 1215 1216 /* Set frequency */ 1217 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1218 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1219 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1220 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1221 CAR_PLLD2_BASE_REF_SRC_SEL | 1222 CAR_PLLD2_BASE_DIVM | 1223 CAR_PLLD2_BASE_DIVN | 1224 CAR_PLLD2_BASE_DIVP); 1225 1226 return 0; 1227 } else { 1228 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1229 tclk->base.name, rate); 1230 /* TODO */ 1231 return EOPNOTSUPP; 1232 } 1233 } 1234 1235 static int 1236 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1237 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1238 { 1239 struct tegra_mux_clk *tmux = &tclk->u.mux; 1240 bus_space_tag_t bst = sc->sc_bst; 1241 bus_space_handle_t bsh = sc->sc_bsh; 1242 uint32_t v; 1243 u_int src; 1244 1245 KASSERT(tclk->type == TEGRA_CLK_MUX); 1246 1247 for (src = 0; src < tmux->nparents; src++) { 1248 if (tmux->parents[src] == NULL) { 1249 continue; 1250 } 1251 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1252 break; 1253 } 1254 } 1255 if (src == tmux->nparents) { 1256 return EINVAL; 1257 } 1258 1259 v = bus_space_read_4(bst, bsh, tmux->reg); 1260 v &= ~tmux->bits; 1261 v |= __SHIFTIN(src, tmux->bits); 1262 bus_space_write_4(bst, bsh, tmux->reg, v); 1263 1264 return 0; 1265 } 1266 1267 static struct tegra_clk * 1268 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1269 struct tegra_clk *tclk) 1270 { 1271 struct tegra_mux_clk *tmux = &tclk->u.mux; 1272 bus_space_tag_t bst = sc->sc_bst; 1273 bus_space_handle_t bsh = sc->sc_bsh; 1274 1275 KASSERT(tclk->type == TEGRA_CLK_MUX); 1276 1277 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1278 const u_int src = __SHIFTOUT(v, tmux->bits); 1279 1280 KASSERT(src < tmux->nparents); 1281 1282 if (tmux->parents[src] == NULL) { 1283 return NULL; 1284 } 1285 1286 return tegra210_car_clock_find(tmux->parents[src]); 1287 } 1288 1289 static u_int 1290 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1291 struct tegra_clk *tclk) 1292 { 1293 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1294 struct clk *clk_parent; 1295 1296 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1297 if (clk_parent == NULL) 1298 return 0; 1299 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1300 1301 return parent_rate / tfixed_div->div; 1302 } 1303 1304 static u_int 1305 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1306 struct tegra_clk *tclk) 1307 { 1308 struct tegra_div_clk *tdiv = &tclk->u.div; 1309 bus_space_tag_t bst = sc->sc_bst; 1310 bus_space_handle_t bsh = sc->sc_bsh; 1311 struct clk *clk_parent; 1312 u_int rate; 1313 1314 KASSERT(tclk->type == TEGRA_CLK_DIV); 1315 1316 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1317 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1318 1319 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1320 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1321 1322 switch (tdiv->reg) { 1323 case CAR_CLKSRC_I2C1_REG: 1324 case CAR_CLKSRC_I2C2_REG: 1325 case CAR_CLKSRC_I2C3_REG: 1326 case CAR_CLKSRC_I2C4_REG: 1327 case CAR_CLKSRC_I2C5_REG: 1328 case CAR_CLKSRC_I2C6_REG: 1329 rate = parent_rate / (raw_div + 1); 1330 break; 1331 case CAR_CLKSRC_UARTA_REG: 1332 case CAR_CLKSRC_UARTB_REG: 1333 case CAR_CLKSRC_UARTC_REG: 1334 case CAR_CLKSRC_UARTD_REG: 1335 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1336 rate = parent_rate / ((raw_div / 2) + 1); 1337 } else { 1338 rate = parent_rate; 1339 } 1340 break; 1341 case CAR_CLKSRC_SDMMC2_REG: 1342 case CAR_CLKSRC_SDMMC4_REG: 1343 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1344 case 1: 1345 case 2: 1346 case 5: 1347 raw_div = 0; /* ignore divisor for _LJ options */ 1348 break; 1349 } 1350 /* FALLTHROUGH */ 1351 default: 1352 rate = parent_rate / ((raw_div / 2) + 1); 1353 break; 1354 } 1355 1356 return rate; 1357 } 1358 1359 static int 1360 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1361 struct tegra_clk *tclk, u_int rate) 1362 { 1363 struct tegra_div_clk *tdiv = &tclk->u.div; 1364 bus_space_tag_t bst = sc->sc_bst; 1365 bus_space_handle_t bsh = sc->sc_bsh; 1366 struct clk *clk_parent; 1367 u_int raw_div; 1368 uint32_t v; 1369 1370 KASSERT(tclk->type == TEGRA_CLK_DIV); 1371 1372 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1373 if (clk_parent == NULL) 1374 return EINVAL; 1375 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1376 1377 v = bus_space_read_4(bst, bsh, tdiv->reg); 1378 1379 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1380 1381 switch (tdiv->reg) { 1382 case CAR_CLKSRC_UARTA_REG: 1383 case CAR_CLKSRC_UARTB_REG: 1384 case CAR_CLKSRC_UARTC_REG: 1385 case CAR_CLKSRC_UARTD_REG: 1386 if (rate == parent_rate) { 1387 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1388 } else if (rate) { 1389 v |= CAR_CLKSRC_UART_DIV_ENB; 1390 raw_div = (parent_rate / rate) * 2; 1391 if (raw_div >= 2) 1392 raw_div -= 2; 1393 } 1394 break; 1395 case CAR_CLKSRC_I2C1_REG: 1396 case CAR_CLKSRC_I2C2_REG: 1397 case CAR_CLKSRC_I2C3_REG: 1398 case CAR_CLKSRC_I2C4_REG: 1399 case CAR_CLKSRC_I2C5_REG: 1400 case CAR_CLKSRC_I2C6_REG: 1401 if (rate) 1402 raw_div = (parent_rate / rate) - 1; 1403 break; 1404 case CAR_CLKSRC_SDMMC1_REG: 1405 case CAR_CLKSRC_SDMMC2_REG: 1406 case CAR_CLKSRC_SDMMC3_REG: 1407 case CAR_CLKSRC_SDMMC4_REG: 1408 if (rate) { 1409 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1410 u_int calc_rate = 1411 parent_rate / ((raw_div / 2) + 1); 1412 if (calc_rate <= rate) 1413 break; 1414 } 1415 if (raw_div == 0x100) 1416 return EINVAL; 1417 } 1418 break; 1419 default: 1420 if (rate) { 1421 raw_div = (parent_rate / rate) * 2; 1422 if (raw_div >= 2) 1423 raw_div -= 2; 1424 } 1425 break; 1426 } 1427 1428 v &= ~tdiv->bits; 1429 v |= __SHIFTIN(raw_div, tdiv->bits); 1430 1431 bus_space_write_4(bst, bsh, tdiv->reg, v); 1432 1433 return 0; 1434 } 1435 1436 static int 1437 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1438 struct tegra_clk *tclk, bool enable) 1439 { 1440 struct tegra_gate_clk *tgate = &tclk->u.gate; 1441 bus_space_tag_t bst = sc->sc_bst; 1442 bus_space_handle_t bsh = sc->sc_bsh; 1443 bus_size_t reg; 1444 1445 KASSERT(tclk->type == TEGRA_CLK_GATE); 1446 1447 if (tgate->set_reg == tgate->clr_reg) { 1448 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1449 if (enable) { 1450 v |= tgate->bits; 1451 } else { 1452 v &= ~tgate->bits; 1453 } 1454 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1455 } else { 1456 if (enable) { 1457 reg = tgate->set_reg; 1458 } else { 1459 reg = tgate->clr_reg; 1460 } 1461 bus_space_write_4(bst, bsh, reg, tgate->bits); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static u_int 1468 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1469 { 1470 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1471 struct clk *clk_parent; 1472 1473 switch (tclk->type) { 1474 case TEGRA_CLK_FIXED: 1475 return tclk->u.fixed.rate; 1476 case TEGRA_CLK_PLL: 1477 return tegra210_car_clock_get_rate_pll(priv, tclk); 1478 case TEGRA_CLK_MUX: 1479 case TEGRA_CLK_GATE: 1480 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1481 if (clk_parent == NULL) 1482 return EINVAL; 1483 return tegra210_car_clock_get_rate(priv, clk_parent); 1484 case TEGRA_CLK_FIXED_DIV: 1485 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1486 case TEGRA_CLK_DIV: 1487 return tegra210_car_clock_get_rate_div(priv, tclk); 1488 default: 1489 panic("tegra210: unknown tclk type %d", tclk->type); 1490 } 1491 } 1492 1493 static int 1494 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1495 { 1496 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1497 struct clk *clk_parent; 1498 1499 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1500 1501 switch (tclk->type) { 1502 case TEGRA_CLK_FIXED: 1503 case TEGRA_CLK_MUX: 1504 return EIO; 1505 case TEGRA_CLK_FIXED_DIV: 1506 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1507 if (clk_parent == NULL) 1508 return EIO; 1509 return tegra210_car_clock_set_rate(priv, clk_parent, 1510 rate * tclk->u.fixed_div.div); 1511 case TEGRA_CLK_GATE: 1512 return EINVAL; 1513 case TEGRA_CLK_PLL: 1514 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1515 case TEGRA_CLK_DIV: 1516 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1517 default: 1518 panic("tegra210: unknown tclk type %d", tclk->type); 1519 } 1520 } 1521 1522 static int 1523 tegra210_car_clock_enable(void *priv, struct clk *clk) 1524 { 1525 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1526 struct clk *clk_parent; 1527 1528 if (tclk->type != TEGRA_CLK_GATE) { 1529 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1530 if (clk_parent == NULL) 1531 return 0; 1532 return tegra210_car_clock_enable(priv, clk_parent); 1533 } 1534 1535 return tegra210_car_clock_enable_gate(priv, tclk, true); 1536 } 1537 1538 static int 1539 tegra210_car_clock_disable(void *priv, struct clk *clk) 1540 { 1541 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1542 1543 if (tclk->type != TEGRA_CLK_GATE) 1544 return EINVAL; 1545 1546 return tegra210_car_clock_enable_gate(priv, tclk, false); 1547 } 1548 1549 static int 1550 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1551 struct clk *clk_parent) 1552 { 1553 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1554 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1555 struct clk *nclk_parent; 1556 1557 if (tclk->type != TEGRA_CLK_MUX) { 1558 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1559 if (nclk_parent == clk_parent || nclk_parent == NULL) 1560 return EINVAL; 1561 return tegra210_car_clock_set_parent(priv, nclk_parent, 1562 clk_parent); 1563 } 1564 1565 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1566 } 1567 1568 static struct clk * 1569 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1570 { 1571 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1572 struct tegra_clk *tclk_parent = NULL; 1573 1574 switch (tclk->type) { 1575 case TEGRA_CLK_FIXED: 1576 case TEGRA_CLK_PLL: 1577 case TEGRA_CLK_FIXED_DIV: 1578 case TEGRA_CLK_DIV: 1579 case TEGRA_CLK_GATE: 1580 if (tclk->parent) { 1581 tclk_parent = tegra210_car_clock_find(tclk->parent); 1582 } 1583 break; 1584 case TEGRA_CLK_MUX: 1585 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1586 break; 1587 } 1588 1589 if (tclk_parent == NULL) 1590 return NULL; 1591 1592 return TEGRA_CLK_BASE(tclk_parent); 1593 } 1594 1595 static void * 1596 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1597 { 1598 struct tegra210_car_softc * const sc = device_private(dev); 1599 struct tegra210_car_rst *rst; 1600 1601 if (len != sc->sc_reset_cells * 4) 1602 return NULL; 1603 1604 const u_int reset_id = be32dec(data); 1605 1606 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1607 return NULL; 1608 1609 const u_int reg = reset_id / 32; 1610 1611 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1612 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1613 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1614 rst->mask = __BIT(reset_id % 32); 1615 1616 return rst; 1617 } 1618 1619 static void 1620 tegra210_car_reset_release(device_t dev, void *priv) 1621 { 1622 struct tegra210_car_rst *rst = priv; 1623 1624 kmem_free(rst, sizeof(*rst)); 1625 } 1626 1627 static int 1628 tegra210_car_reset_assert(device_t dev, void *priv) 1629 { 1630 struct tegra210_car_softc * const sc = device_private(dev); 1631 struct tegra210_car_rst *rst = priv; 1632 1633 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1634 1635 return 0; 1636 } 1637 1638 static int 1639 tegra210_car_reset_deassert(device_t dev, void *priv) 1640 { 1641 struct tegra210_car_softc * const sc = device_private(dev); 1642 struct tegra210_car_rst *rst = priv; 1643 1644 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1645 1646 return 0; 1647 } 1648 1649 void 1650 tegra210_car_xusbio_enable_hw_control(void) 1651 { 1652 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1653 KASSERT(dev != NULL); 1654 struct tegra210_car_softc * const sc = device_private(dev); 1655 bus_space_tag_t bst = sc->sc_bst; 1656 bus_space_handle_t bsh = sc->sc_bsh; 1657 1658 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1659 0, 1660 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1661 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1662 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1663 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1664 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1665 0); 1666 } 1667 1668 void 1669 tegra210_car_xusbio_enable_hw_seq(void) 1670 { 1671 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1672 KASSERT(dev != NULL); 1673 struct tegra210_car_softc * const sc = device_private(dev); 1674 bus_space_tag_t bst = sc->sc_bst; 1675 bus_space_handle_t bsh = sc->sc_bsh; 1676 1677 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1678 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1679 } 1680
Indexes created Tue Sep 30 20:09:53 GMT 2025