tegra210_car.c revision 1.2
1 /* $NetBSD: tegra210_car.c,v 1.2 2017/09/19 20:45:09 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.2 2017/09/19 20:45:09 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static struct tegra_clk tegra210_car_clocks[] = { 440 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 441 442 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 443 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 444 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 445 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 446 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 447 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 448 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 449 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 450 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 451 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 452 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 453 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 454 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 455 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 456 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 457 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 458 459 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 460 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 461 462 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 463 mux_uart_p), 464 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 465 mux_uart_p), 466 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 469 mux_uart_p), 470 471 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc1_p), 473 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc2_4_p), 475 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 476 mux_sdmmc3_p), 477 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 478 mux_sdmmc2_4_p), 479 480 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 487 CLK_MUX("MUX_XUSB_HOST", 488 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 489 mux_xusb_host_p), 490 CLK_MUX("MUX_XUSB_FALCON", 491 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 492 mux_xusb_host_p), 493 CLK_MUX("MUX_XUSB_SS", 494 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 495 mux_xusb_ss_p), 496 CLK_MUX("MUX_XUSB_FS", 497 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 498 mux_xusb_fs_p), 499 500 CLK_DIV("DIV_UARTA", "MUX_UARTA", 501 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 502 CLK_DIV("DIV_UARTB", "MUX_UARTB", 503 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 504 CLK_DIV("DIV_UARTC", "MUX_UARTC", 505 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 506 CLK_DIV("DIV_UARTD", "MUX_UARTD", 507 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 508 509 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 510 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 511 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 512 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 513 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 514 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 515 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 516 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 517 518 CLK_DIV("DIV_I2C1", "MUX_I2C1", 519 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 520 CLK_DIV("DIV_I2C2", "MUX_I2C2", 521 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 522 CLK_DIV("DIV_I2C3", "MUX_I2C3", 523 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 524 CLK_DIV("DIV_I2C4", "MUX_I2C4", 525 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 526 CLK_DIV("DIV_I2C5", "MUX_I2C5", 527 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 528 CLK_DIV("DIV_I2C6", "MUX_I2C6", 529 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 530 531 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 532 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 533 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 534 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 535 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 536 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 537 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 538 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 539 540 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 541 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 542 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 543 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 544 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 545 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 546 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 547 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 548 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 549 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 550 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 551 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 552 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 553 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 554 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 555 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 556 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 557 }; 558 559 struct tegra210_init_parent { 560 const char *clock; 561 const char *parent; 562 } tegra210_init_parents[] = { 563 { "SDMMC1", "PLL_P" }, 564 { "SDMMC2", "PLL_P" }, 565 { "SDMMC3", "PLL_P" }, 566 { "SDMMC4", "PLL_P" }, 567 { "XUSB_HOST_SRC", "PLL_P" }, 568 { "XUSB_FALCON_SRC", "PLL_P" }, 569 { "XUSB_SS_SRC", "PLL_U_480M" }, 570 { "XUSB_FS_SRC", "PLL_U_48M" }, 571 }; 572 573 struct tegra210_car_rst { 574 u_int set_reg; 575 u_int clr_reg; 576 u_int mask; 577 }; 578 579 static struct tegra210_car_reset_reg { 580 u_int set_reg; 581 u_int clr_reg; 582 } tegra210_car_reset_regs[] = { 583 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 584 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 585 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 586 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 587 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 588 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 589 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 590 }; 591 592 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 593 static void tegra210_car_reset_release(device_t, void *); 594 static int tegra210_car_reset_assert(device_t, void *); 595 static int tegra210_car_reset_deassert(device_t, void *); 596 597 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 598 .acquire = tegra210_car_reset_acquire, 599 .release = tegra210_car_reset_release, 600 .reset_assert = tegra210_car_reset_assert, 601 .reset_deassert = tegra210_car_reset_deassert, 602 }; 603 604 struct tegra210_car_softc { 605 device_t sc_dev; 606 bus_space_tag_t sc_bst; 607 bus_space_handle_t sc_bsh; 608 609 struct clk_domain sc_clkdom; 610 611 u_int sc_clock_cells; 612 u_int sc_reset_cells; 613 614 kmutex_t sc_rndlock; 615 krndsource_t sc_rndsource; 616 }; 617 618 static void tegra210_car_init(struct tegra210_car_softc *); 619 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 620 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 621 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 622 static void tegra210_car_parent_init(struct tegra210_car_softc *); 623 624 625 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 626 tegra210_car_match, tegra210_car_attach, NULL, NULL); 627 628 static int 629 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 630 { 631 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 632 struct fdt_attach_args * const faa = aux; 633 634 #if 0 635 return of_match_compatible(faa->faa_phandle, compatible); 636 #else 637 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 638 return 0; 639 640 return 999; 641 #endif 642 } 643 644 static void 645 tegra210_car_attach(device_t parent, device_t self, void *aux) 646 { 647 struct tegra210_car_softc * const sc = device_private(self); 648 struct fdt_attach_args * const faa = aux; 649 const int phandle = faa->faa_phandle; 650 bus_addr_t addr; 651 bus_size_t size; 652 int error, n; 653 654 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 655 aprint_error(": couldn't get registers\n"); 656 return; 657 } 658 659 sc->sc_dev = self; 660 sc->sc_bst = faa->faa_bst; 661 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 662 if (error) { 663 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 664 return; 665 } 666 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 667 sc->sc_clock_cells = 1; 668 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 669 sc->sc_reset_cells = 1; 670 671 aprint_naive("\n"); 672 aprint_normal(": CAR\n"); 673 674 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 675 sc->sc_clkdom.priv = sc; 676 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 677 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 678 679 fdtbus_register_clock_controller(self, phandle, 680 &tegra210_car_fdtclock_funcs); 681 fdtbus_register_reset_controller(self, phandle, 682 &tegra210_car_fdtreset_funcs); 683 684 tegra210_car_init(sc); 685 686 #ifdef TEGRA210_CAR_DEBUG 687 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 688 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 689 struct clk *clk_parent = clk_get_parent(clk); 690 device_printf(self, "clk %s (parent %s): ", clk->name, 691 clk_parent ? clk_parent->name : "none"); 692 printf("%u Hz\n", clk_get_rate(clk)); 693 } 694 #endif 695 } 696 697 static void 698 tegra210_car_init(struct tegra210_car_softc *sc) 699 { 700 tegra210_car_parent_init(sc); 701 tegra210_car_utmip_init(sc); 702 tegra210_car_xusb_init(sc); 703 tegra210_car_watchdog_init(sc); 704 } 705 706 static void 707 tegra210_car_parent_init(struct tegra210_car_softc *sc) 708 { 709 struct clk *clk, *clk_parent; 710 int error; 711 u_int n; 712 713 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 714 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 715 KASSERT(clk != NULL); 716 clk_parent = clk_get(&sc->sc_clkdom, 717 tegra210_init_parents[n].parent); 718 KASSERT(clk_parent != NULL); 719 720 error = clk_set_parent(clk, clk_parent); 721 if (error) { 722 aprint_error_dev(sc->sc_dev, 723 "couldn't set '%s' parent to '%s': %d\n", 724 clk->name, clk_parent->name, error); 725 } 726 clk_put(clk_parent); 727 clk_put(clk); 728 } 729 } 730 731 static void 732 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 733 { 734 bus_space_tag_t bst = sc->sc_bst; 735 bus_space_handle_t bsh = sc->sc_bsh; 736 737 const u_int enable_dly_count = 0x02; 738 const u_int stable_count = 0x2f; 739 const u_int active_dly_count = 0x04; 740 const u_int xtal_freq_count = 0x76; 741 742 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 743 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 744 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 745 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 746 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 747 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN | 748 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 749 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 750 751 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 752 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 753 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 754 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 755 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 756 757 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 758 0, 759 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 760 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 761 762 } 763 764 static void 765 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 766 { 767 const bus_space_tag_t bst = sc->sc_bst; 768 const bus_space_handle_t bsh = sc->sc_bsh; 769 uint32_t val; 770 771 /* XXX do this all better */ 772 773 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 774 775 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 776 0, CAR_PLLREFE_MISC_IDDQ); 777 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) | 778 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM); 779 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val); 780 781 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 782 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE); 783 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 784 CAR_PLLREFE_BASE_ENABLE, 0); 785 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 786 CAR_PLLREFE_MISC_LOCK_ENABLE, 0); 787 788 do { 789 delay(2); 790 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 791 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 792 793 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 794 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE); 795 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 796 CAR_PLLE_BASE_ENABLE, 0); 797 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 798 CAR_PLLE_MISC_LOCK_ENABLE, 0); 799 800 do { 801 delay(2); 802 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 803 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 804 805 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG, 806 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0); 807 } 808 809 static void 810 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 811 { 812 const bus_space_tag_t bst = sc->sc_bst; 813 const bus_space_handle_t bsh = sc->sc_bsh; 814 815 /* Enable watchdog timer reset for system */ 816 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 817 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 818 } 819 820 static struct tegra_clk * 821 tegra210_car_clock_find(const char *name) 822 { 823 u_int n; 824 825 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 826 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 827 return &tegra210_car_clocks[n]; 828 } 829 } 830 831 return NULL; 832 } 833 834 static struct tegra_clk * 835 tegra210_car_clock_find_by_id(u_int clock_id) 836 { 837 u_int n; 838 839 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 840 if (tegra210_car_clock_ids[n].id == clock_id) { 841 const char *name = tegra210_car_clock_ids[n].name; 842 return tegra210_car_clock_find(name); 843 } 844 } 845 846 return NULL; 847 } 848 849 static struct clk * 850 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 851 { 852 struct tegra210_car_softc * const sc = device_private(dev); 853 struct tegra_clk *tclk; 854 855 if (len != sc->sc_clock_cells * 4) { 856 return NULL; 857 } 858 859 const u_int clock_id = be32dec(data); 860 861 tclk = tegra210_car_clock_find_by_id(clock_id); 862 if (tclk) 863 return TEGRA_CLK_BASE(tclk); 864 865 return NULL; 866 } 867 868 static struct clk * 869 tegra210_car_clock_get(void *priv, const char *name) 870 { 871 struct tegra_clk *tclk; 872 873 tclk = tegra210_car_clock_find(name); 874 if (tclk == NULL) 875 return NULL; 876 877 atomic_inc_uint(&tclk->refcnt); 878 879 return TEGRA_CLK_BASE(tclk); 880 } 881 882 static void 883 tegra210_car_clock_put(void *priv, struct clk *clk) 884 { 885 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 886 887 KASSERT(tclk->refcnt > 0); 888 889 atomic_dec_uint(&tclk->refcnt); 890 } 891 892 static u_int 893 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 894 struct tegra_clk *tclk) 895 { 896 struct tegra_pll_clk *tpll = &tclk->u.pll; 897 struct tegra_clk *tclk_parent; 898 bus_space_tag_t bst = sc->sc_bst; 899 bus_space_handle_t bsh = sc->sc_bsh; 900 u_int divm, divn, divp; 901 uint64_t rate; 902 903 KASSERT(tclk->type == TEGRA_CLK_PLL); 904 905 tclk_parent = tegra210_car_clock_find(tclk->parent); 906 KASSERT(tclk_parent != NULL); 907 908 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 909 TEGRA_CLK_BASE(tclk_parent)); 910 911 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 912 divm = __SHIFTOUT(base, tpll->divm_mask); 913 divn = __SHIFTOUT(base, tpll->divn_mask); 914 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 915 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 916 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 917 /* XXX divp is not applied to PLLP's primary output */ 918 divp = 0; 919 } else { 920 divp = __SHIFTOUT(base, tpll->divp_mask); 921 } 922 923 rate = (uint64_t)rate_parent * divn; 924 return rate / (divm << divp); 925 } 926 927 static int 928 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 929 struct tegra_clk *tclk, u_int rate) 930 { 931 struct tegra_pll_clk *tpll = &tclk->u.pll; 932 bus_space_tag_t bst = sc->sc_bst; 933 bus_space_handle_t bsh = sc->sc_bsh; 934 struct clk *clk_parent; 935 uint32_t bp, base; 936 937 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 938 if (clk_parent == NULL) 939 return EIO; 940 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 941 if (rate_parent == 0) 942 return EIO; 943 944 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 945 const u_int divm = 1; 946 const u_int divn = rate / rate_parent; 947 const u_int divp = 0; 948 949 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 950 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 951 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 952 CAR_CCLKG_BURST_POLICY_CPU_STATE); 953 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 954 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 955 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 956 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 957 958 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 959 base &= ~CAR_PLLX_BASE_DIVM; 960 base &= ~CAR_PLLX_BASE_DIVN; 961 base &= ~CAR_PLLX_BASE_DIVP; 962 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 963 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 964 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 965 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 966 967 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 968 CAR_PLLX_MISC_LOCK_ENABLE, 0); 969 do { 970 delay(2); 971 base = bus_space_read_4(bst, bsh, tpll->base_reg); 972 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 973 delay(100); 974 975 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 976 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 977 CAR_CCLKG_BURST_POLICY_CPU_STATE); 978 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 979 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 980 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 981 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 982 983 return 0; 984 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 985 const u_int divm = 1; 986 const u_int pldiv = 1; 987 const u_int divn = (rate << pldiv) / rate_parent; 988 989 /* Set frequency */ 990 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 991 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 992 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 993 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 994 CAR_PLLD2_BASE_REF_SRC_SEL | 995 CAR_PLLD2_BASE_DIVM | 996 CAR_PLLD2_BASE_DIVN | 997 CAR_PLLD2_BASE_DIVP); 998 999 return 0; 1000 } else { 1001 /* TODO */ 1002 return EOPNOTSUPP; 1003 } 1004 } 1005 1006 static int 1007 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1008 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1009 { 1010 struct tegra_mux_clk *tmux = &tclk->u.mux; 1011 bus_space_tag_t bst = sc->sc_bst; 1012 bus_space_handle_t bsh = sc->sc_bsh; 1013 uint32_t v; 1014 u_int src; 1015 1016 KASSERT(tclk->type == TEGRA_CLK_MUX); 1017 1018 for (src = 0; src < tmux->nparents; src++) { 1019 if (tmux->parents[src] == NULL) { 1020 continue; 1021 } 1022 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1023 break; 1024 } 1025 } 1026 if (src == tmux->nparents) { 1027 return EINVAL; 1028 } 1029 1030 v = bus_space_read_4(bst, bsh, tmux->reg); 1031 v &= ~tmux->bits; 1032 v |= __SHIFTIN(src, tmux->bits); 1033 bus_space_write_4(bst, bsh, tmux->reg, v); 1034 1035 return 0; 1036 } 1037 1038 static struct tegra_clk * 1039 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1040 struct tegra_clk *tclk) 1041 { 1042 struct tegra_mux_clk *tmux = &tclk->u.mux; 1043 bus_space_tag_t bst = sc->sc_bst; 1044 bus_space_handle_t bsh = sc->sc_bsh; 1045 1046 KASSERT(tclk->type == TEGRA_CLK_MUX); 1047 1048 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1049 const u_int src = __SHIFTOUT(v, tmux->bits); 1050 1051 KASSERT(src < tmux->nparents); 1052 1053 if (tmux->parents[src] == NULL) { 1054 return NULL; 1055 } 1056 1057 return tegra210_car_clock_find(tmux->parents[src]); 1058 } 1059 1060 static u_int 1061 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1062 struct tegra_clk *tclk) 1063 { 1064 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1065 struct clk *clk_parent; 1066 1067 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1068 if (clk_parent == NULL) 1069 return 0; 1070 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1071 1072 return parent_rate / tfixed_div->div; 1073 } 1074 1075 static u_int 1076 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1077 struct tegra_clk *tclk) 1078 { 1079 struct tegra_div_clk *tdiv = &tclk->u.div; 1080 bus_space_tag_t bst = sc->sc_bst; 1081 bus_space_handle_t bsh = sc->sc_bsh; 1082 struct clk *clk_parent; 1083 u_int rate; 1084 1085 KASSERT(tclk->type == TEGRA_CLK_DIV); 1086 1087 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1088 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1089 1090 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1091 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1092 1093 switch (tdiv->reg) { 1094 case CAR_CLKSRC_I2C1_REG: 1095 case CAR_CLKSRC_I2C2_REG: 1096 case CAR_CLKSRC_I2C3_REG: 1097 case CAR_CLKSRC_I2C4_REG: 1098 case CAR_CLKSRC_I2C5_REG: 1099 case CAR_CLKSRC_I2C6_REG: 1100 rate = parent_rate / (raw_div + 1); 1101 break; 1102 case CAR_CLKSRC_UARTA_REG: 1103 case CAR_CLKSRC_UARTB_REG: 1104 case CAR_CLKSRC_UARTC_REG: 1105 case CAR_CLKSRC_UARTD_REG: 1106 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1107 rate = parent_rate / ((raw_div / 2) + 1); 1108 } else { 1109 rate = parent_rate; 1110 } 1111 break; 1112 case CAR_CLKSRC_SDMMC2_REG: 1113 case CAR_CLKSRC_SDMMC4_REG: 1114 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1115 case 1: 1116 case 2: 1117 case 5: 1118 raw_div = 0; /* ignore divisor for _LJ options */ 1119 break; 1120 } 1121 /* FALLTHROUGH */ 1122 default: 1123 rate = parent_rate / ((raw_div / 2) + 1); 1124 break; 1125 } 1126 1127 return rate; 1128 } 1129 1130 static int 1131 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1132 struct tegra_clk *tclk, u_int rate) 1133 { 1134 struct tegra_div_clk *tdiv = &tclk->u.div; 1135 bus_space_tag_t bst = sc->sc_bst; 1136 bus_space_handle_t bsh = sc->sc_bsh; 1137 struct clk *clk_parent; 1138 u_int raw_div; 1139 uint32_t v; 1140 1141 KASSERT(tclk->type == TEGRA_CLK_DIV); 1142 1143 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1144 if (clk_parent == NULL) 1145 return EINVAL; 1146 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1147 1148 v = bus_space_read_4(bst, bsh, tdiv->reg); 1149 1150 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1151 1152 switch (tdiv->reg) { 1153 case CAR_CLKSRC_UARTA_REG: 1154 case CAR_CLKSRC_UARTB_REG: 1155 case CAR_CLKSRC_UARTC_REG: 1156 case CAR_CLKSRC_UARTD_REG: 1157 if (rate == parent_rate) { 1158 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1159 } else if (rate) { 1160 v |= CAR_CLKSRC_UART_DIV_ENB; 1161 raw_div = (parent_rate / rate) * 2 - 1; 1162 } 1163 break; 1164 case CAR_CLKSRC_I2C1_REG: 1165 case CAR_CLKSRC_I2C2_REG: 1166 case CAR_CLKSRC_I2C3_REG: 1167 case CAR_CLKSRC_I2C4_REG: 1168 case CAR_CLKSRC_I2C5_REG: 1169 case CAR_CLKSRC_I2C6_REG: 1170 if (rate) 1171 raw_div = (parent_rate / rate) - 1; 1172 break; 1173 case CAR_CLKSRC_SDMMC1_REG: 1174 case CAR_CLKSRC_SDMMC2_REG: 1175 case CAR_CLKSRC_SDMMC3_REG: 1176 case CAR_CLKSRC_SDMMC4_REG: 1177 if (rate) { 1178 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1179 u_int calc_rate = 1180 parent_rate / ((raw_div / 2) + 1); 1181 if (calc_rate <= rate) 1182 break; 1183 } 1184 if (raw_div == 0x100) 1185 return EINVAL; 1186 } 1187 break; 1188 default: 1189 if (rate) 1190 raw_div = (parent_rate / rate) * 2 - 1; 1191 break; 1192 } 1193 1194 v &= ~tdiv->bits; 1195 v |= __SHIFTIN(raw_div, tdiv->bits); 1196 1197 bus_space_write_4(bst, bsh, tdiv->reg, v); 1198 1199 return 0; 1200 } 1201 1202 static int 1203 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1204 struct tegra_clk *tclk, bool enable) 1205 { 1206 struct tegra_gate_clk *tgate = &tclk->u.gate; 1207 bus_space_tag_t bst = sc->sc_bst; 1208 bus_space_handle_t bsh = sc->sc_bsh; 1209 bus_size_t reg; 1210 1211 KASSERT(tclk->type == TEGRA_CLK_GATE); 1212 1213 if (tgate->set_reg == tgate->clr_reg) { 1214 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1215 if (enable) { 1216 v |= tgate->bits; 1217 } else { 1218 v &= ~tgate->bits; 1219 } 1220 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1221 } else { 1222 if (enable) { 1223 reg = tgate->set_reg; 1224 } else { 1225 reg = tgate->clr_reg; 1226 } 1227 bus_space_write_4(bst, bsh, reg, tgate->bits); 1228 } 1229 1230 return 0; 1231 } 1232 1233 static u_int 1234 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1235 { 1236 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1237 struct clk *clk_parent; 1238 1239 switch (tclk->type) { 1240 case TEGRA_CLK_FIXED: 1241 return tclk->u.fixed.rate; 1242 case TEGRA_CLK_PLL: 1243 return tegra210_car_clock_get_rate_pll(priv, tclk); 1244 case TEGRA_CLK_MUX: 1245 case TEGRA_CLK_GATE: 1246 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1247 if (clk_parent == NULL) 1248 return EINVAL; 1249 return tegra210_car_clock_get_rate(priv, clk_parent); 1250 case TEGRA_CLK_FIXED_DIV: 1251 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1252 case TEGRA_CLK_DIV: 1253 return tegra210_car_clock_get_rate_div(priv, tclk); 1254 default: 1255 panic("tegra210: unknown tclk type %d", tclk->type); 1256 } 1257 } 1258 1259 static int 1260 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1261 { 1262 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1263 struct clk *clk_parent; 1264 1265 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1266 1267 switch (tclk->type) { 1268 case TEGRA_CLK_FIXED: 1269 case TEGRA_CLK_MUX: 1270 return EIO; 1271 case TEGRA_CLK_FIXED_DIV: 1272 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1273 if (clk_parent == NULL) 1274 return EIO; 1275 return tegra210_car_clock_set_rate(priv, clk_parent, 1276 rate * tclk->u.fixed_div.div); 1277 case TEGRA_CLK_GATE: 1278 return EINVAL; 1279 case TEGRA_CLK_PLL: 1280 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1281 case TEGRA_CLK_DIV: 1282 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1283 default: 1284 panic("tegra210: unknown tclk type %d", tclk->type); 1285 } 1286 } 1287 1288 static int 1289 tegra210_car_clock_enable(void *priv, struct clk *clk) 1290 { 1291 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1292 struct clk *clk_parent; 1293 1294 if (tclk->type != TEGRA_CLK_GATE) { 1295 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1296 if (clk_parent == NULL) 1297 return 0; 1298 return tegra210_car_clock_enable(priv, clk_parent); 1299 } 1300 1301 return tegra210_car_clock_enable_gate(priv, tclk, true); 1302 } 1303 1304 static int 1305 tegra210_car_clock_disable(void *priv, struct clk *clk) 1306 { 1307 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1308 1309 if (tclk->type != TEGRA_CLK_GATE) 1310 return EINVAL; 1311 1312 return tegra210_car_clock_enable_gate(priv, tclk, false); 1313 } 1314 1315 static int 1316 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1317 struct clk *clk_parent) 1318 { 1319 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1320 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1321 struct clk *nclk_parent; 1322 1323 if (tclk->type != TEGRA_CLK_MUX) { 1324 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1325 if (nclk_parent == clk_parent || nclk_parent == NULL) 1326 return EINVAL; 1327 return tegra210_car_clock_set_parent(priv, nclk_parent, 1328 clk_parent); 1329 } 1330 1331 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1332 } 1333 1334 static struct clk * 1335 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1336 { 1337 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1338 struct tegra_clk *tclk_parent = NULL; 1339 1340 switch (tclk->type) { 1341 case TEGRA_CLK_FIXED: 1342 case TEGRA_CLK_PLL: 1343 case TEGRA_CLK_FIXED_DIV: 1344 case TEGRA_CLK_DIV: 1345 case TEGRA_CLK_GATE: 1346 if (tclk->parent) { 1347 tclk_parent = tegra210_car_clock_find(tclk->parent); 1348 } 1349 break; 1350 case TEGRA_CLK_MUX: 1351 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1352 break; 1353 } 1354 1355 if (tclk_parent == NULL) 1356 return NULL; 1357 1358 return TEGRA_CLK_BASE(tclk_parent); 1359 } 1360 1361 static void * 1362 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1363 { 1364 struct tegra210_car_softc * const sc = device_private(dev); 1365 struct tegra210_car_rst *rst; 1366 1367 if (len != sc->sc_reset_cells * 4) 1368 return NULL; 1369 1370 const u_int reset_id = be32dec(data); 1371 1372 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1373 return NULL; 1374 1375 const u_int reg = reset_id / 32; 1376 1377 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1378 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1379 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1380 rst->mask = __BIT(reset_id % 32); 1381 1382 return rst; 1383 } 1384 1385 static void 1386 tegra210_car_reset_release(device_t dev, void *priv) 1387 { 1388 struct tegra210_car_rst *rst = priv; 1389 1390 kmem_free(rst, sizeof(*rst)); 1391 } 1392 1393 static int 1394 tegra210_car_reset_assert(device_t dev, void *priv) 1395 { 1396 struct tegra210_car_softc * const sc = device_private(dev); 1397 struct tegra210_car_rst *rst = priv; 1398 1399 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1400 1401 return 0; 1402 } 1403 1404 static int 1405 tegra210_car_reset_deassert(device_t dev, void *priv) 1406 { 1407 struct tegra210_car_softc * const sc = device_private(dev); 1408 struct tegra210_car_rst *rst = priv; 1409 1410 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1411 1412 return 0; 1413 } 1414
Indexes created Tue Sep 30 20:09:53 GMT 2025