tegra210_car.c revision 1.22
1 /* $NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, int, const void *, 57 size_t); 58 59 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 60 .decode = tegra210_car_clock_decode 61 }; 62 63 /* DT clock ID to clock name mappings */ 64 static struct tegra210_car_clock_id { 65 const char *name; 66 u_int id; 67 } tegra210_car_clock_ids[] = { 68 { "ISPB", 3 }, 69 { "RTC", 4 }, 70 { "TIMER", 5 }, 71 { "UARTA", 6 }, 72 { "GPIO", 8 }, 73 { "SDMMC2", 9 }, 74 { "I2S1", 11 }, 75 { "I2C1", 12 }, 76 { "SDMMC1", 14 }, 77 { "SDMMC4", 15 }, 78 { "PWM", 17 }, 79 { "I2S2", 18 }, 80 { "USBD", 22 }, 81 { "ISP", 23 }, 82 { "DISP2", 26 }, 83 { "DISP1", 27 }, 84 { "HOST1X", 28 }, 85 { "I2S0", 30 }, 86 { "MC", 32 }, 87 { "AHBDMA", 33 }, 88 { "APBDMA", 34 }, 89 { "PMC", 38 }, 90 { "KFUSE", 40 }, 91 { "SBC1", 41 }, 92 { "SBC2", 44 }, 93 { "SBC3", 46 }, 94 { "I2C5", 47 }, 95 { "DSIA", 48 }, 96 { "CSI", 52 }, 97 { "I2C2", 54 }, 98 { "UARTC", 55 }, 99 { "MIPI_CAL", 56 }, 100 { "EMC", 57 }, 101 { "USB2", 58 }, 102 { "BSEV", 63 }, 103 { "UARTD", 65 }, 104 { "I2C3", 67 }, 105 { "SBC4", 68 }, 106 { "SDMMC3", 69 }, 107 { "PCIE", 70 }, 108 { "OWR", 71 }, 109 { "AFI", 72 }, 110 { "CSITE", 73 }, 111 { "SOC_THERM", 78 }, 112 { "DTV", 79 }, 113 { "I2CSLOW", 81 }, 114 { "DSIB", 82 }, 115 { "TSEC", 83 }, 116 { "XUSB_HOST", 89 }, 117 { "CSUS", 92 }, 118 { "MSELECT", 99 }, 119 { "TSENSOR", 100 }, 120 { "I2S3", 101 }, 121 { "I2S4", 102 }, 122 { "I2C4", 103 }, 123 { "D_AUDIO", 106 }, 124 { "APB2APE", 107 }, 125 { "HDA2CODEC_2X", 111 }, 126 { "SPDIF_2X", 118 }, 127 { "ACTMON", 119 }, 128 { "EXTERN1", 120 }, 129 { "EXTERN2", 121 }, 130 { "EXTERN3", 122 }, 131 { "SATA_OOB", 123 }, 132 { "SATA", 124 }, 133 { "HDA", 125 }, 134 { "HDA2HDMI", 128 }, 135 { "XUSB_GATE", 143 }, 136 { "CILAB", 144 }, 137 { "CILCD", 145 }, 138 { "CILE", 146 }, 139 { "DSIALP", 147 }, 140 { "DSIBLP", 148 }, 141 { "ENTROPY", 149 }, 142 { "XUSB_SS", 156 }, 143 { "DMIC1", 161 }, 144 { "DMIC2", 162 }, 145 { "I2C6", 166 }, 146 { "VIM2_CLK", 171 }, 147 { "MIPIBIF", 173 }, 148 { "CLK72MHZ", 177 }, 149 { "VIC03", 178 }, 150 { "DPAUX", 181 }, 151 { "SOR0", 182 }, 152 { "SOR1", 183 }, 153 { "GPU", 184 }, 154 { "DBGAPB", 185 }, 155 { "PLL_P_OUT_ADSP", 187 }, 156 { "PLL_G_REF", 189 }, 157 { "SDMMC_LEGACY", 193 }, 158 { "NVDEC", 194 }, 159 { "NVJPG", 195 }, 160 { "DMIC3", 197 }, 161 { "APE", 198 }, 162 { "MAUD", 202 }, 163 { "TSECB", 206 }, 164 { "DPAUX1", 207 }, 165 { "VI_I2C", 208 }, 166 { "HSIC_TRK", 209 }, 167 { "USB2_TRK", 210 }, 168 { "QSPI", 211 }, 169 { "UARTAPE", 212 }, 170 { "NVENC", 219 }, 171 { "SOR_SAFE", 222 }, 172 { "PLL_P_OUT_CPU", 223 }, 173 { "UARTB", 224 }, 174 { "VFIR", 225 }, 175 { "SPDIF_IN", 226 }, 176 { "SPDIF_OUT", 227 }, 177 { "VI", 228 }, 178 { "VI_SENSOR", 229 }, 179 { "FUSE", 230 }, 180 { "FUSE_BURN", 231 }, 181 { "CLK_32K", 232 }, 182 { "CLK_M", 233 }, 183 { "CLK_M_DIV2", 234 }, 184 { "CLK_M_DIV4", 235 }, 185 { "PLL_REF", 236 }, 186 { "PLL_C", 237 }, 187 { "PLL_C_OUT1", 238 }, 188 { "PLL_C2", 239 }, 189 { "PLL_C3", 240 }, 190 { "PLL_M", 241 }, 191 { "PLL_M_OUT1", 242 }, 192 { "PLL_P", 243 }, 193 { "PLL_P_OUT1", 244 }, 194 { "PLL_P_OUT2", 245 }, 195 { "PLL_P_OUT3", 246 }, 196 { "PLL_P_OUT4", 247 }, 197 { "PLL_A", 248 }, 198 { "PLL_A_OUT0", 249 }, 199 { "PLL_D", 250 }, 200 { "PLL_D_OUT0", 251 }, 201 { "PLL_D2", 252 }, 202 { "PLL_D2_OUT0", 253 }, 203 { "PLL_U", 254 }, 204 { "PLL_U_480M", 255 }, 205 { "PLL_U_60M", 256 }, 206 { "PLL_U_48M", 257 }, 207 { "PLL_X", 259 }, 208 { "PLL_X_OUT0", 260 }, 209 { "PLL_RE_VCO", 261 }, 210 { "PLL_RE_OUT", 262 }, 211 { "PLL_E", 263 }, 212 { "SPDIF_IN_SYNC", 264 }, 213 { "I2S0_SYNC", 265 }, 214 { "I2S1_SYNC", 266 }, 215 { "I2S2_SYNC", 267 }, 216 { "I2S3_SYNC", 268 }, 217 { "I2S4_SYNC", 269 }, 218 { "VIMCLK_SYNC", 270 }, 219 { "AUDIO0", 271 }, 220 { "AUDIO1", 272 }, 221 { "AUDIO2", 273 }, 222 { "AUDIO3", 274 }, 223 { "AUDIO4", 275 }, 224 { "SPDIF", 276 }, 225 { "CLK_OUT_1", 277 }, 226 { "CLK_OUT_2", 278 }, 227 { "CLK_OUT_3", 279 }, 228 { "BLINK", 280 }, 229 { "SOR1_SRC", 282 }, 230 { "XUSB_HOST_SRC", 284 }, 231 { "XUSB_FALCON_SRC", 285 }, 232 { "XUSB_FS_SRC", 286 }, 233 { "XUSB_SS_SRC", 287 }, 234 { "XUSB_DEV_SRC", 288 }, 235 { "XUSB_DEV", 289 }, 236 { "XUSB_HS_SRC", 290 }, 237 { "SCLK", 291 }, 238 { "HCLK", 292 }, 239 { "PCLK", 293 }, 240 { "CCLK_G", 294 }, 241 { "CCLK_LP", 295 }, 242 { "DFLL_REF", 296 }, 243 { "DFLL_SOC", 297 }, 244 { "VI_SENSOR2", 298 }, 245 { "PLL_P_OUT5", 299 }, 246 { "CML0", 300 }, 247 { "CML1", 301 }, 248 { "PLL_C4", 302 }, 249 { "PLL_DP", 303 }, 250 { "PLL_E_MUX", 304 }, 251 { "PLL_MB", 305 }, 252 { "PLL_A1", 306 }, 253 { "PLL_D_DSI_OUT", 307 }, 254 { "PLL_C4_OUT0", 308 }, 255 { "PLL_C4_OUT1", 309 }, 256 { "PLL_C4_OUT2", 310 }, 257 { "PLL_C4_OUT3", 311 }, 258 { "PLL_U_OUT", 312 }, 259 { "PLL_U_OUT1", 313 }, 260 { "PLL_U_OUT2", 314 }, 261 { "USB2_HSIC_TRK", 315 }, 262 { "PLL_P_OUT_HSIO", 316 }, 263 { "PLL_P_OUT_XUSB", 317 }, 264 { "XUSB_SSP_SRC", 318 }, 265 { "PLL_RE_OUT1", 319 }, 266 { "AUDIO0_MUX", 350 }, 267 { "AUDIO1_MUX", 351 }, 268 { "AUDIO2_MUX", 352 }, 269 { "AUDIO3_MUX", 353 }, 270 { "AUDIO4_MUX", 354 }, 271 { "SPDIF_MUX", 355 }, 272 { "CLK_OUT_1_MUX", 356 }, 273 { "CLK_OUT_2_MUX", 357 }, 274 { "CLK_OUT_3_MUX", 358 }, 275 { "DSIA_MUX", 359 }, 276 { "DSIB_MUX", 360 }, 277 { "SOR0_LVDS", 361 }, 278 { "XUSB_SS_DIV2", 362 }, 279 { "PLL_M_UD", 363 }, 280 { "PLL_C_UD", 364 }, 281 { "SCLK_MUX", 365 }, 282 }; 283 284 static struct clk *tegra210_car_clock_get(void *, const char *); 285 static void tegra210_car_clock_put(void *, struct clk *); 286 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 287 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 288 static int tegra210_car_clock_enable(void *, struct clk *); 289 static int tegra210_car_clock_disable(void *, struct clk *); 290 static int tegra210_car_clock_set_parent(void *, struct clk *, 291 struct clk *); 292 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 293 294 static const struct clk_funcs tegra210_car_clock_funcs = { 295 .get = tegra210_car_clock_get, 296 .put = tegra210_car_clock_put, 297 .get_rate = tegra210_car_clock_get_rate, 298 .set_rate = tegra210_car_clock_set_rate, 299 .enable = tegra210_car_clock_enable, 300 .disable = tegra210_car_clock_disable, 301 .set_parent = tegra210_car_clock_set_parent, 302 .get_parent = tegra210_car_clock_get_parent, 303 }; 304 305 #define CLK_FIXED(_name, _rate) { \ 306 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 307 .u = { .fixed = { .rate = (_rate) } } \ 308 } 309 310 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 311 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 312 .parent = (_parent), \ 313 .u = { \ 314 .pll = { \ 315 .base_reg = (_base), \ 316 .divm_mask = (_divm), \ 317 .divn_mask = (_divn), \ 318 .divp_mask = (_divp), \ 319 } \ 320 } \ 321 } 322 323 #define CLK_MUX(_name, _reg, _bits, _p) { \ 324 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 325 .u = { \ 326 .mux = { \ 327 .nparents = __arraycount(_p), \ 328 .parents = (_p), \ 329 .reg = (_reg), \ 330 .bits = (_bits) \ 331 } \ 332 } \ 333 } 334 335 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 336 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 337 .parent = (_parent), \ 338 .u = { \ 339 .fixed_div = { \ 340 .div = (_div) \ 341 } \ 342 } \ 343 } 344 345 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 346 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 347 .parent = (_parent), \ 348 .u = { \ 349 .div = { \ 350 .reg = (_reg), \ 351 .bits = (_bits) \ 352 } \ 353 } \ 354 } 355 356 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 357 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 358 .type = TEGRA_CLK_GATE, \ 359 .parent = (_parent), \ 360 .u = { \ 361 .gate = { \ 362 .set_reg = (_set), \ 363 .clr_reg = (_clr), \ 364 .bits = (_bits), \ 365 } \ 366 } \ 367 } 368 369 #define CLK_GATE_L(_name, _parent, _bits) \ 370 CLK_GATE(_name, _parent, \ 371 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 372 _bits) 373 374 #define CLK_GATE_H(_name, _parent, _bits) \ 375 CLK_GATE(_name, _parent, \ 376 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 377 _bits) 378 379 #define CLK_GATE_U(_name, _parent, _bits) \ 380 CLK_GATE(_name, _parent, \ 381 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 382 _bits) 383 384 #define CLK_GATE_V(_name, _parent, _bits) \ 385 CLK_GATE(_name, _parent, \ 386 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 387 _bits) 388 389 #define CLK_GATE_W(_name, _parent, _bits) \ 390 CLK_GATE(_name, _parent, \ 391 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 392 _bits) 393 394 #define CLK_GATE_X(_name, _parent, _bits) \ 395 CLK_GATE(_name, _parent, \ 396 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 397 _bits) 398 399 #define CLK_GATE_Y(_name, _parent, _bits) \ 400 CLK_GATE(_name, _parent, \ 401 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 402 _bits) 403 404 405 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 406 CLK_GATE(_name, _parent, _reg, _reg, _bits) 407 408 static const char *mux_uart_p[] = 409 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 410 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 411 412 static const char *mux_sdmmc1_p[] = 413 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 414 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 415 416 static const char *mux_sdmmc2_4_p[] = 417 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 418 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 419 420 static const char *mux_sdmmc3_p[] = 421 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 422 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 423 424 static const char *mux_i2c_p[] = 425 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 426 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 427 428 static const char *mux_xusb_host_p[] = 429 { "CLK_M", "PLL_P", NULL, NULL, 430 NULL, "PLL_REF", NULL, NULL }; 431 432 static const char *mux_xusb_fs_p[] = 433 { "CLK_M", NULL, "PLL_U_48M", NULL, 434 "PLL_P", NULL, "PLL_U_480M", NULL }; 435 436 static const char *mux_xusb_ss_p[] = 437 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 438 NULL, NULL, NULL, NULL }; 439 440 static const char *mux_mselect_p[] = 441 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT2", 442 "PLL_C4_OUT1", "CLK_S", "CLK_M", "PLL_C4_OUT0" }; 443 444 static const char *mux_tsensor_p[] = 445 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 446 "CLK_M", "PLL_C4_OUT1", "CLK_S", "PLL_C4_OUT2" }; 447 448 static const char *mux_soc_therm_p[] = 449 { "CLK_M", "PLL_C", "PLL_P", "PLL_A", 450 "PLL_C2", "PLL_C4_OUT0", "PLL_C4_OUT1", "PLL_C4_OUT2" }; 451 452 static const char *mux_hda2codec_2x_p[] = 453 { "PLL_P", "PLL_C2", "PLL_C4_OUT0", "PLL_A", 454 "PLL_A", "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 455 456 static const char *mux_hda_p[] = 457 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 458 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 459 460 static struct tegra_clk tegra210_car_clocks[] = { 461 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 462 463 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 464 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 465 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 466 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 467 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 468 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 469 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 470 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 471 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 472 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 473 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 474 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 475 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 476 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 477 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 478 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 479 480 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 481 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 482 483 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 484 mux_uart_p), 485 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 486 mux_uart_p), 487 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 488 mux_uart_p), 489 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 490 mux_uart_p), 491 492 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 493 mux_sdmmc1_p), 494 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 495 mux_sdmmc2_4_p), 496 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 497 mux_sdmmc3_p), 498 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 499 mux_sdmmc2_4_p), 500 501 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 502 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 503 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 504 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 505 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 506 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 507 508 CLK_MUX("MUX_XUSB_HOST", 509 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 510 mux_xusb_host_p), 511 CLK_MUX("MUX_XUSB_FALCON", 512 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 513 mux_xusb_host_p), 514 CLK_MUX("MUX_XUSB_SS", 515 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 516 mux_xusb_ss_p), 517 CLK_MUX("MUX_XUSB_FS", 518 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 519 mux_xusb_fs_p), 520 521 CLK_MUX("MUX_MSELECT", 522 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC, 523 mux_mselect_p), 524 525 CLK_MUX("MUX_TSENSOR", 526 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC, 527 mux_tsensor_p), 528 CLK_MUX("MUX_SOC_THERM", 529 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC, 530 mux_soc_therm_p), 531 532 CLK_MUX("MUX_HDA2CODEC_2X", 533 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC, 534 mux_hda2codec_2x_p), 535 CLK_MUX("MUX_HDA", 536 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, 537 mux_hda_p), 538 539 CLK_DIV("DIV_UARTA", "MUX_UARTA", 540 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 541 CLK_DIV("DIV_UARTB", "MUX_UARTB", 542 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 543 CLK_DIV("DIV_UARTC", "MUX_UARTC", 544 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 545 CLK_DIV("DIV_UARTD", "MUX_UARTD", 546 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 547 548 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 549 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 550 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 551 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 552 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 553 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 554 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 555 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 556 557 CLK_DIV("DIV_I2C1", "MUX_I2C1", 558 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 559 CLK_DIV("DIV_I2C2", "MUX_I2C2", 560 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 561 CLK_DIV("DIV_I2C3", "MUX_I2C3", 562 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 563 CLK_DIV("DIV_I2C4", "MUX_I2C4", 564 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 565 CLK_DIV("DIV_I2C5", "MUX_I2C5", 566 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 567 CLK_DIV("DIV_I2C6", "MUX_I2C6", 568 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 569 570 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 571 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 572 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 573 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 574 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 575 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 576 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 577 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 578 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 579 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 580 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U", 581 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO), 582 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U", 583 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO), 584 585 CLK_DIV("DIV_MSELECT", "MUX_MSELECT", 586 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV), 587 588 CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR", 589 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV), 590 CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM", 591 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV), 592 593 CLK_DIV("DIV_HDA2CODEC_2X", "MUX_HDA2CODEC_2X", 594 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV), 595 CLK_DIV("DIV_HDA", "MUX_HDA", 596 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV), 597 598 CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1", 599 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN), 600 CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2", 601 CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN), 602 603 CLK_GATE_SIMPLE("CML0", "PLL_E", 604 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN), 605 CLK_GATE_SIMPLE("CML1", "PLL_E", 606 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN), 607 608 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 609 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 610 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 611 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 612 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 613 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 614 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 615 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 616 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 617 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 618 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 619 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 620 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 621 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 622 CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB), 623 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 624 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 625 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 626 CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 627 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 628 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 629 CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD), 630 CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2), 631 CLK_GATE_V("MSELECT", "DIV_MSELECT", CAR_DEV_V_MSELECT), 632 CLK_GATE_U("PCIE", "CLK_M", CAR_DEV_U_PCIE), 633 CLK_GATE_U("AFI", "MSELECT", CAR_DEV_U_AFI), 634 CLK_GATE_V("TSENSOR", "DIV_TSENSOR", CAR_DEV_V_TSENSOR), 635 CLK_GATE_U("SOC_THERM", "DIV_SOC_THERM", CAR_DEV_U_SOC_THERM), 636 CLK_GATE_W("HDA2HDMI", "CLK_M", CAR_DEV_W_HDA2HDMICODEC), 637 CLK_GATE_V("HDA2CODEC_2X", "DIV_HDA2CODEC_2X", CAR_DEV_V_HDA2CODEC_2X), 638 CLK_GATE_V("HDA", "DIV_HDA", CAR_DEV_V_HDA), 639 }; 640 641 struct tegra210_init_parent { 642 const char *clock; 643 const char *parent; 644 u_int rate; 645 u_int enable; 646 } tegra210_init_parents[] = { 647 { "SDMMC1", "PLL_P", 0, 0 }, 648 { "SDMMC2", "PLL_P", 0, 0 }, 649 { "SDMMC3", "PLL_P", 0, 0 }, 650 { "SDMMC4", "PLL_P", 0, 0 }, 651 { "SOC_THERM", "PLL_P", 0, 0 }, 652 { "TSENSOR", "CLK_M", 0, 0 }, 653 { "XUSB_GATE", NULL, 0, 1 }, 654 { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 }, 655 { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 }, 656 { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 }, 657 { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 }, 658 { "PLL_U_OUT1", NULL, 48000000, 1 }, 659 { "PLL_U_OUT2", NULL, 60000000, 1 }, 660 { "CML0", NULL, 0, 1 }, 661 { "CML1", NULL, 0, 0 }, 662 { "AFI", NULL, 0, 1 }, 663 { "PCIE", NULL, 0, 1 }, 664 }; 665 666 struct tegra210_car_rst { 667 u_int set_reg; 668 u_int clr_reg; 669 u_int mask; 670 }; 671 672 static struct tegra210_car_reset_reg { 673 u_int set_reg; 674 u_int clr_reg; 675 } tegra210_car_reset_regs[] = { 676 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 677 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 678 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 679 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 680 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 681 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 682 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 683 }; 684 685 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 686 static void tegra210_car_reset_release(device_t, void *); 687 static int tegra210_car_reset_assert(device_t, void *); 688 static int tegra210_car_reset_deassert(device_t, void *); 689 690 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 691 .acquire = tegra210_car_reset_acquire, 692 .release = tegra210_car_reset_release, 693 .reset_assert = tegra210_car_reset_assert, 694 .reset_deassert = tegra210_car_reset_deassert, 695 }; 696 697 struct tegra210_car_softc { 698 device_t sc_dev; 699 bus_space_tag_t sc_bst; 700 bus_space_handle_t sc_bsh; 701 702 struct clk_domain sc_clkdom; 703 704 u_int sc_clock_cells; 705 u_int sc_reset_cells; 706 707 kmutex_t sc_rndlock; 708 krndsource_t sc_rndsource; 709 }; 710 711 static void tegra210_car_init(struct tegra210_car_softc *); 712 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 713 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 714 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 715 static void tegra210_car_parent_init(struct tegra210_car_softc *); 716 717 718 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 719 tegra210_car_match, tegra210_car_attach, NULL, NULL); 720 721 static int 722 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 723 { 724 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 725 struct fdt_attach_args * const faa = aux; 726 727 #if 0 728 return of_match_compatible(faa->faa_phandle, compatible); 729 #else 730 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 731 return 0; 732 733 return 999; 734 #endif 735 } 736 737 static void 738 tegra210_car_attach(device_t parent, device_t self, void *aux) 739 { 740 struct tegra210_car_softc * const sc = device_private(self); 741 struct fdt_attach_args * const faa = aux; 742 const int phandle = faa->faa_phandle; 743 bus_addr_t addr; 744 bus_size_t size; 745 int error, n; 746 747 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 748 aprint_error(": couldn't get registers\n"); 749 return; 750 } 751 752 sc->sc_dev = self; 753 sc->sc_bst = faa->faa_bst; 754 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 755 if (error) { 756 aprint_error(": couldn't map %#" PRIx64 ": %d", 757 (uint64_t)addr, error); 758 return; 759 } 760 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 761 sc->sc_clock_cells = 1; 762 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 763 sc->sc_reset_cells = 1; 764 765 aprint_naive("\n"); 766 aprint_normal(": CAR\n"); 767 768 sc->sc_clkdom.name = device_xname(self); 769 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 770 sc->sc_clkdom.priv = sc; 771 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 772 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 773 clk_attach(&tegra210_car_clocks[n].base); 774 } 775 776 fdtbus_register_clock_controller(self, phandle, 777 &tegra210_car_fdtclock_funcs); 778 fdtbus_register_reset_controller(self, phandle, 779 &tegra210_car_fdtreset_funcs); 780 781 tegra210_car_init(sc); 782 783 #ifdef TEGRA210_CAR_DEBUG 784 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 785 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 786 struct clk *clk_parent = clk_get_parent(clk); 787 device_printf(self, "clk %s (parent %s): ", clk->name, 788 clk_parent ? clk_parent->name : "none"); 789 printf("%u Hz\n", clk_get_rate(clk)); 790 } 791 #endif 792 } 793 794 static void 795 tegra210_car_init(struct tegra210_car_softc *sc) 796 { 797 tegra210_car_parent_init(sc); 798 tegra210_car_utmip_init(sc); 799 tegra210_car_xusb_init(sc); 800 tegra210_car_watchdog_init(sc); 801 } 802 803 static void 804 tegra210_car_parent_init(struct tegra210_car_softc *sc) 805 { 806 struct clk *clk, *clk_parent; 807 int error; 808 u_int n; 809 810 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 811 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 812 KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock); 813 814 if (tegra210_init_parents[n].parent != NULL) { 815 clk_parent = clk_get(&sc->sc_clkdom, 816 tegra210_init_parents[n].parent); 817 KASSERT(clk_parent != NULL); 818 819 error = clk_set_parent(clk, clk_parent); 820 if (error) { 821 aprint_error_dev(sc->sc_dev, 822 "couldn't set '%s' parent to '%s': %d\n", 823 clk->name, clk_parent->name, error); 824 } 825 clk_put(clk_parent); 826 } 827 if (tegra210_init_parents[n].rate != 0) { 828 error = clk_set_rate(clk, tegra210_init_parents[n].rate); 829 if (error) { 830 aprint_error_dev(sc->sc_dev, 831 "couldn't set '%s' rate to %u Hz: %d\n", 832 clk->name, tegra210_init_parents[n].rate, 833 error); 834 } 835 } 836 if (tegra210_init_parents[n].enable) { 837 error = clk_enable(clk); 838 if (error) { 839 aprint_error_dev(sc->sc_dev, 840 "couldn't enable '%s': %d\n", clk->name, 841 error); 842 } 843 } 844 clk_put(clk); 845 } 846 } 847 848 static void 849 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 850 { 851 bus_space_tag_t bst = sc->sc_bst; 852 bus_space_handle_t bsh = sc->sc_bsh; 853 854 /* 855 * Set up the UTMI PLL. 856 */ 857 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 858 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 859 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 860 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 861 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 862 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 863 delay(10); 864 /* TODO UTMIP_PLL_CFG0 */ 865 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 866 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 867 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 868 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 869 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 870 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 871 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 872 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 873 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 874 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 875 876 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI); 877 bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE); 878 879 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD); 880 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2); 881 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 882 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI); 883 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE); 884 bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK); 885 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 886 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 887 888 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 889 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 890 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 891 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 892 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 893 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 894 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 895 896 /* 897 * Set up UTMI PLL under hardware control 898 */ 899 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 900 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 901 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 902 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 903 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 904 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 905 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 906 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 907 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 908 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 909 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 910 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 911 delay(1); 912 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 913 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 914 } 915 916 static void 917 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 918 { 919 const bus_space_tag_t bst = sc->sc_bst; 920 const bus_space_handle_t bsh = sc->sc_bsh; 921 uint32_t val; 922 923 /* 924 * Set up the PLLU. 925 */ 926 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 927 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 928 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 929 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 930 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 931 delay(5); 932 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 933 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 934 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 935 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 936 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 937 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 938 do { 939 delay(2); 940 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 941 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 942 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 943 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 944 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 945 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 946 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 947 delay(2); 948 949 /* 950 * Now switch PLLU to hw controlled mode. 951 */ 952 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE); 953 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 954 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 955 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 956 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET, 957 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 958 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 959 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0, 960 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY); 961 delay(1); 962 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG, 963 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 964 delay(1); 965 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB); 966 967 /* 968 * Set up PLLREFE 969 */ 970 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 971 0, CAR_PLLREFE_MISC_IDDQ); 972 delay(5); 973 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 974 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 975 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 976 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 977 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 978 CAR_PLLREFE_BASE_DIVM | 979 CAR_PLLREFE_BASE_DIVN | 980 CAR_PLLREFE_BASE_DIVP | 981 CAR_PLLREFE_BASE_KCP); 982 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 983 CAR_PLLREFE_BASE_ENABLE, 0); 984 do { 985 delay(2); 986 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 987 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 988 989 /* 990 * Set up the PLLE. 991 */ 992 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 993 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 994 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 995 delay(5); 996 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 997 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 998 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 999 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 1000 CAR_PLLE_BASE_DIVP_CML | 1001 CAR_PLLE_BASE_DIVN | 1002 CAR_PLLE_BASE_DIVM); 1003 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 1004 CAR_PLLE_MISC_PTS, 1005 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 1006 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 1007 do { 1008 delay(2); 1009 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 1010 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 1011 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 1012 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 1013 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 1014 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 1015 CAR_PLLE_SS_CNTL_SSCINC | 1016 CAR_PLLE_SS_CNTL_SSCINCINTRV | 1017 CAR_PLLE_SS_CNTL_SSCMAX | 1018 CAR_PLLE_SS_CNTL_SSCINVERT | 1019 CAR_PLLE_SS_CNTL_SSCCENTER | 1020 CAR_PLLE_SS_CNTL_BYPASS_SS | 1021 CAR_PLLE_SS_CNTL_SSCBYP); 1022 delay(1); 1023 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 1024 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 1025 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 1026 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 1027 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 1028 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 1029 delay(1); 1030 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 1031 1032 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 1033 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 1034 } 1035 1036 static void 1037 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 1038 { 1039 const bus_space_tag_t bst = sc->sc_bst; 1040 const bus_space_handle_t bsh = sc->sc_bsh; 1041 1042 /* Enable watchdog timer reset for system */ 1043 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 1044 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 1045 } 1046 1047 static struct tegra_clk * 1048 tegra210_car_clock_find(const char *name) 1049 { 1050 u_int n; 1051 1052 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 1053 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 1054 return &tegra210_car_clocks[n]; 1055 } 1056 } 1057 1058 return NULL; 1059 } 1060 1061 static struct tegra_clk * 1062 tegra210_car_clock_find_by_id(u_int clock_id) 1063 { 1064 u_int n; 1065 1066 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 1067 if (tegra210_car_clock_ids[n].id == clock_id) { 1068 const char *name = tegra210_car_clock_ids[n].name; 1069 return tegra210_car_clock_find(name); 1070 } 1071 } 1072 1073 return NULL; 1074 } 1075 1076 static struct clk * 1077 tegra210_car_clock_decode(device_t dev, int cc_phandle, const void *data, 1078 size_t len) 1079 { 1080 struct tegra210_car_softc * const sc = device_private(dev); 1081 struct tegra_clk *tclk; 1082 1083 if (len != sc->sc_clock_cells * 4) { 1084 return NULL; 1085 } 1086 1087 const u_int clock_id = be32dec(data); 1088 1089 tclk = tegra210_car_clock_find_by_id(clock_id); 1090 if (tclk) 1091 return TEGRA_CLK_BASE(tclk); 1092 1093 return NULL; 1094 } 1095 1096 static struct clk * 1097 tegra210_car_clock_get(void *priv, const char *name) 1098 { 1099 struct tegra_clk *tclk; 1100 1101 tclk = tegra210_car_clock_find(name); 1102 if (tclk == NULL) 1103 return NULL; 1104 1105 atomic_inc_uint(&tclk->refcnt); 1106 1107 return TEGRA_CLK_BASE(tclk); 1108 } 1109 1110 static void 1111 tegra210_car_clock_put(void *priv, struct clk *clk) 1112 { 1113 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1114 1115 KASSERT(tclk->refcnt > 0); 1116 1117 atomic_dec_uint(&tclk->refcnt); 1118 } 1119 1120 static u_int 1121 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 1122 struct tegra_clk *tclk) 1123 { 1124 struct tegra_pll_clk *tpll = &tclk->u.pll; 1125 struct tegra_clk *tclk_parent; 1126 bus_space_tag_t bst = sc->sc_bst; 1127 bus_space_handle_t bsh = sc->sc_bsh; 1128 u_int divm, divn, divp; 1129 uint64_t rate; 1130 1131 KASSERT(tclk->type == TEGRA_CLK_PLL); 1132 1133 tclk_parent = tegra210_car_clock_find(tclk->parent); 1134 KASSERT(tclk_parent != NULL); 1135 1136 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 1137 TEGRA_CLK_BASE(tclk_parent)); 1138 1139 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1140 divm = __SHIFTOUT(base, tpll->divm_mask); 1141 divn = __SHIFTOUT(base, tpll->divn_mask); 1142 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1143 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1144 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1145 /* XXX divp is not applied to PLLP's primary output */ 1146 divp = 0; 1147 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1148 divp = 0; 1149 divm *= __SHIFTOUT(base, tpll->divp_mask); 1150 } else { 1151 divp = __SHIFTOUT(base, tpll->divp_mask); 1152 } 1153 1154 rate = (uint64_t)rate_parent * divn; 1155 return rate / (divm << divp); 1156 } 1157 1158 static int 1159 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1160 struct tegra_clk *tclk, u_int rate) 1161 { 1162 struct tegra_pll_clk *tpll = &tclk->u.pll; 1163 bus_space_tag_t bst = sc->sc_bst; 1164 bus_space_handle_t bsh = sc->sc_bsh; 1165 struct clk *clk_parent; 1166 uint32_t bp, base; 1167 1168 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1169 if (clk_parent == NULL) 1170 return EIO; 1171 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1172 if (rate_parent == 0) 1173 return EIO; 1174 1175 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1176 const u_int divm = 1; 1177 const u_int divn = rate / rate_parent; 1178 const u_int divp = 0; 1179 1180 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1181 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1182 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1183 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1184 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1185 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1186 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1187 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1188 1189 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1190 base &= ~CAR_PLLX_BASE_DIVM; 1191 base &= ~CAR_PLLX_BASE_DIVN; 1192 base &= ~CAR_PLLX_BASE_DIVP; 1193 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1194 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1195 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1196 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1197 1198 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1199 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1200 do { 1201 delay(2); 1202 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1203 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1204 delay(100); 1205 1206 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1207 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1208 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1209 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1210 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1211 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1212 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1213 1214 return 0; 1215 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1216 const u_int divm = 1; 1217 const u_int pldiv = 1; 1218 const u_int divn = (rate << pldiv) / rate_parent; 1219 1220 /* Set frequency */ 1221 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1222 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1223 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1224 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1225 CAR_PLLD2_BASE_REF_SRC_SEL | 1226 CAR_PLLD2_BASE_DIVM | 1227 CAR_PLLD2_BASE_DIVN | 1228 CAR_PLLD2_BASE_DIVP); 1229 1230 return 0; 1231 } else { 1232 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1233 tclk->base.name, rate); 1234 /* TODO */ 1235 return EOPNOTSUPP; 1236 } 1237 } 1238 1239 static int 1240 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1241 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1242 { 1243 struct tegra_mux_clk *tmux = &tclk->u.mux; 1244 bus_space_tag_t bst = sc->sc_bst; 1245 bus_space_handle_t bsh = sc->sc_bsh; 1246 uint32_t v; 1247 u_int src; 1248 1249 KASSERT(tclk->type == TEGRA_CLK_MUX); 1250 1251 for (src = 0; src < tmux->nparents; src++) { 1252 if (tmux->parents[src] == NULL) { 1253 continue; 1254 } 1255 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1256 break; 1257 } 1258 } 1259 if (src == tmux->nparents) { 1260 return EINVAL; 1261 } 1262 1263 v = bus_space_read_4(bst, bsh, tmux->reg); 1264 v &= ~tmux->bits; 1265 v |= __SHIFTIN(src, tmux->bits); 1266 bus_space_write_4(bst, bsh, tmux->reg, v); 1267 1268 return 0; 1269 } 1270 1271 static struct tegra_clk * 1272 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1273 struct tegra_clk *tclk) 1274 { 1275 struct tegra_mux_clk *tmux = &tclk->u.mux; 1276 bus_space_tag_t bst = sc->sc_bst; 1277 bus_space_handle_t bsh = sc->sc_bsh; 1278 1279 KASSERT(tclk->type == TEGRA_CLK_MUX); 1280 1281 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1282 const u_int src = __SHIFTOUT(v, tmux->bits); 1283 1284 KASSERT(src < tmux->nparents); 1285 1286 if (tmux->parents[src] == NULL) { 1287 return NULL; 1288 } 1289 1290 return tegra210_car_clock_find(tmux->parents[src]); 1291 } 1292 1293 static u_int 1294 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1295 struct tegra_clk *tclk) 1296 { 1297 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1298 struct clk *clk_parent; 1299 1300 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1301 if (clk_parent == NULL) 1302 return 0; 1303 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1304 1305 return parent_rate / tfixed_div->div; 1306 } 1307 1308 static u_int 1309 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1310 struct tegra_clk *tclk) 1311 { 1312 struct tegra_div_clk *tdiv = &tclk->u.div; 1313 bus_space_tag_t bst = sc->sc_bst; 1314 bus_space_handle_t bsh = sc->sc_bsh; 1315 struct clk *clk_parent; 1316 u_int rate; 1317 1318 KASSERT(tclk->type == TEGRA_CLK_DIV); 1319 1320 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1321 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1322 1323 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1324 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1325 1326 switch (tdiv->reg) { 1327 case CAR_CLKSRC_I2C1_REG: 1328 case CAR_CLKSRC_I2C2_REG: 1329 case CAR_CLKSRC_I2C3_REG: 1330 case CAR_CLKSRC_I2C4_REG: 1331 case CAR_CLKSRC_I2C5_REG: 1332 case CAR_CLKSRC_I2C6_REG: 1333 rate = parent_rate / (raw_div + 1); 1334 break; 1335 case CAR_CLKSRC_UARTA_REG: 1336 case CAR_CLKSRC_UARTB_REG: 1337 case CAR_CLKSRC_UARTC_REG: 1338 case CAR_CLKSRC_UARTD_REG: 1339 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1340 rate = parent_rate / ((raw_div / 2) + 1); 1341 } else { 1342 rate = parent_rate; 1343 } 1344 break; 1345 case CAR_CLKSRC_SDMMC2_REG: 1346 case CAR_CLKSRC_SDMMC4_REG: 1347 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1348 case 1: 1349 case 2: 1350 case 5: 1351 raw_div = 0; /* ignore divisor for _LJ options */ 1352 break; 1353 } 1354 /* FALLTHROUGH */ 1355 default: 1356 rate = parent_rate / ((raw_div / 2) + 1); 1357 break; 1358 } 1359 1360 return rate; 1361 } 1362 1363 static int 1364 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1365 struct tegra_clk *tclk, u_int rate) 1366 { 1367 struct tegra_div_clk *tdiv = &tclk->u.div; 1368 bus_space_tag_t bst = sc->sc_bst; 1369 bus_space_handle_t bsh = sc->sc_bsh; 1370 struct clk *clk_parent; 1371 u_int raw_div; 1372 uint32_t v; 1373 1374 KASSERT(tclk->type == TEGRA_CLK_DIV); 1375 1376 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1377 if (clk_parent == NULL) 1378 return EINVAL; 1379 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1380 1381 v = bus_space_read_4(bst, bsh, tdiv->reg); 1382 1383 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1384 1385 switch (tdiv->reg) { 1386 case CAR_CLKSRC_UARTA_REG: 1387 case CAR_CLKSRC_UARTB_REG: 1388 case CAR_CLKSRC_UARTC_REG: 1389 case CAR_CLKSRC_UARTD_REG: 1390 if (rate == parent_rate) { 1391 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1392 } else if (rate) { 1393 v |= CAR_CLKSRC_UART_DIV_ENB; 1394 raw_div = (parent_rate / rate) * 2; 1395 if (raw_div >= 2) 1396 raw_div -= 2; 1397 } 1398 break; 1399 case CAR_CLKSRC_I2C1_REG: 1400 case CAR_CLKSRC_I2C2_REG: 1401 case CAR_CLKSRC_I2C3_REG: 1402 case CAR_CLKSRC_I2C4_REG: 1403 case CAR_CLKSRC_I2C5_REG: 1404 case CAR_CLKSRC_I2C6_REG: 1405 if (rate) 1406 raw_div = (parent_rate / rate) - 1; 1407 break; 1408 case CAR_CLKSRC_SDMMC1_REG: 1409 case CAR_CLKSRC_SDMMC2_REG: 1410 case CAR_CLKSRC_SDMMC3_REG: 1411 case CAR_CLKSRC_SDMMC4_REG: 1412 if (rate) { 1413 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1414 u_int calc_rate = 1415 parent_rate / ((raw_div / 2) + 1); 1416 if (calc_rate <= rate) 1417 break; 1418 } 1419 if (raw_div == 0x100) 1420 return EINVAL; 1421 } 1422 break; 1423 default: 1424 if (rate) { 1425 raw_div = (parent_rate / rate) * 2; 1426 if (raw_div >= 2) 1427 raw_div -= 2; 1428 } 1429 break; 1430 } 1431 1432 v &= ~tdiv->bits; 1433 v |= __SHIFTIN(raw_div, tdiv->bits); 1434 1435 bus_space_write_4(bst, bsh, tdiv->reg, v); 1436 1437 return 0; 1438 } 1439 1440 static int 1441 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1442 struct tegra_clk *tclk, bool enable) 1443 { 1444 struct tegra_gate_clk *tgate = &tclk->u.gate; 1445 bus_space_tag_t bst = sc->sc_bst; 1446 bus_space_handle_t bsh = sc->sc_bsh; 1447 bus_size_t reg; 1448 1449 KASSERT(tclk->type == TEGRA_CLK_GATE); 1450 1451 if (tgate->set_reg == tgate->clr_reg) { 1452 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1453 if (enable) { 1454 v |= tgate->bits; 1455 } else { 1456 v &= ~tgate->bits; 1457 } 1458 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1459 } else { 1460 if (enable) { 1461 reg = tgate->set_reg; 1462 } else { 1463 reg = tgate->clr_reg; 1464 } 1465 bus_space_write_4(bst, bsh, reg, tgate->bits); 1466 } 1467 1468 return 0; 1469 } 1470 1471 static u_int 1472 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1473 { 1474 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1475 struct clk *clk_parent; 1476 1477 switch (tclk->type) { 1478 case TEGRA_CLK_FIXED: 1479 return tclk->u.fixed.rate; 1480 case TEGRA_CLK_PLL: 1481 return tegra210_car_clock_get_rate_pll(priv, tclk); 1482 case TEGRA_CLK_MUX: 1483 case TEGRA_CLK_GATE: 1484 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1485 if (clk_parent == NULL) 1486 return EINVAL; 1487 return tegra210_car_clock_get_rate(priv, clk_parent); 1488 case TEGRA_CLK_FIXED_DIV: 1489 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1490 case TEGRA_CLK_DIV: 1491 return tegra210_car_clock_get_rate_div(priv, tclk); 1492 default: 1493 panic("tegra210: unknown tclk type %d", tclk->type); 1494 } 1495 } 1496 1497 static int 1498 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1499 { 1500 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1501 struct clk *clk_parent; 1502 1503 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1504 1505 switch (tclk->type) { 1506 case TEGRA_CLK_FIXED: 1507 case TEGRA_CLK_MUX: 1508 return EIO; 1509 case TEGRA_CLK_FIXED_DIV: 1510 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1511 if (clk_parent == NULL) 1512 return EIO; 1513 return tegra210_car_clock_set_rate(priv, clk_parent, 1514 rate * tclk->u.fixed_div.div); 1515 case TEGRA_CLK_GATE: 1516 return EINVAL; 1517 case TEGRA_CLK_PLL: 1518 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1519 case TEGRA_CLK_DIV: 1520 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1521 default: 1522 panic("tegra210: unknown tclk type %d", tclk->type); 1523 } 1524 } 1525 1526 static int 1527 tegra210_car_clock_enable(void *priv, struct clk *clk) 1528 { 1529 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1530 struct clk *clk_parent; 1531 1532 if (tclk->type != TEGRA_CLK_GATE) { 1533 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1534 if (clk_parent == NULL) 1535 return 0; 1536 return tegra210_car_clock_enable(priv, clk_parent); 1537 } 1538 1539 return tegra210_car_clock_enable_gate(priv, tclk, true); 1540 } 1541 1542 static int 1543 tegra210_car_clock_disable(void *priv, struct clk *clk) 1544 { 1545 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1546 1547 if (tclk->type != TEGRA_CLK_GATE) 1548 return EINVAL; 1549 1550 return tegra210_car_clock_enable_gate(priv, tclk, false); 1551 } 1552 1553 static int 1554 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1555 struct clk *clk_parent) 1556 { 1557 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1558 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1559 struct clk *nclk_parent; 1560 1561 if (tclk->type != TEGRA_CLK_MUX) { 1562 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1563 if (nclk_parent == clk_parent || nclk_parent == NULL) 1564 return EINVAL; 1565 return tegra210_car_clock_set_parent(priv, nclk_parent, 1566 clk_parent); 1567 } 1568 1569 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1570 } 1571 1572 static struct clk * 1573 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1574 { 1575 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1576 struct tegra_clk *tclk_parent = NULL; 1577 1578 switch (tclk->type) { 1579 case TEGRA_CLK_FIXED: 1580 case TEGRA_CLK_PLL: 1581 case TEGRA_CLK_FIXED_DIV: 1582 case TEGRA_CLK_DIV: 1583 case TEGRA_CLK_GATE: 1584 if (tclk->parent) { 1585 tclk_parent = tegra210_car_clock_find(tclk->parent); 1586 } 1587 break; 1588 case TEGRA_CLK_MUX: 1589 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1590 break; 1591 } 1592 1593 if (tclk_parent == NULL) 1594 return NULL; 1595 1596 return TEGRA_CLK_BASE(tclk_parent); 1597 } 1598 1599 static void * 1600 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1601 { 1602 struct tegra210_car_softc * const sc = device_private(dev); 1603 struct tegra210_car_rst *rst; 1604 1605 if (len != sc->sc_reset_cells * 4) 1606 return NULL; 1607 1608 const u_int reset_id = be32dec(data); 1609 1610 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1611 return NULL; 1612 1613 const u_int reg = reset_id / 32; 1614 1615 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1616 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1617 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1618 rst->mask = __BIT(reset_id % 32); 1619 1620 return rst; 1621 } 1622 1623 static void 1624 tegra210_car_reset_release(device_t dev, void *priv) 1625 { 1626 struct tegra210_car_rst *rst = priv; 1627 1628 kmem_free(rst, sizeof(*rst)); 1629 } 1630 1631 static int 1632 tegra210_car_reset_assert(device_t dev, void *priv) 1633 { 1634 struct tegra210_car_softc * const sc = device_private(dev); 1635 struct tegra210_car_rst *rst = priv; 1636 1637 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1638 1639 return 0; 1640 } 1641 1642 static int 1643 tegra210_car_reset_deassert(device_t dev, void *priv) 1644 { 1645 struct tegra210_car_softc * const sc = device_private(dev); 1646 struct tegra210_car_rst *rst = priv; 1647 1648 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1649 1650 return 0; 1651 } 1652 1653 void 1654 tegra210_car_xusbio_enable_hw_control(void) 1655 { 1656 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1657 KASSERT(dev != NULL); 1658 struct tegra210_car_softc * const sc = device_private(dev); 1659 bus_space_tag_t bst = sc->sc_bst; 1660 bus_space_handle_t bsh = sc->sc_bsh; 1661 1662 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1663 0, 1664 CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1665 CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1666 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1667 CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ | 1668 CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET, 1669 0); 1670 } 1671 1672 void 1673 tegra210_car_xusbio_enable_hw_seq(void) 1674 { 1675 device_t dev = device_find_by_driver_unit("tegra210car", 0); 1676 KASSERT(dev != NULL); 1677 struct tegra210_car_softc * const sc = device_private(dev); 1678 bus_space_tag_t bst = sc->sc_bst; 1679 bus_space_handle_t bsh = sc->sc_bsh; 1680 1681 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG, 1682 CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0); 1683 } 1684
Indexes created Tue Sep 30 17:09:57 GMT 2025