tegra210_car.c revision 1.8
1 /* $NetBSD: tegra210_car.c,v 1.8 2017/09/23 23:58:04 jmcneill Exp $ */ 2 #define TEGRA210_CAR_DEBUG 3 4 /*- 5 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.8 2017/09/23 23:58:04 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/rndpool.h> 40 #include <sys/rndsource.h> 41 #include <sys/atomic.h> 42 #include <sys/kmem.h> 43 44 #include <dev/clk/clk_backend.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra210_carreg.h> 48 #include <arm/nvidia/tegra_clock.h> 49 #include <arm/nvidia/tegra_pmcreg.h> 50 #include <arm/nvidia/tegra_var.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 static int tegra210_car_match(device_t, cfdata_t, void *); 55 static void tegra210_car_attach(device_t, device_t, void *); 56 57 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 58 59 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 60 .decode = tegra210_car_clock_decode 61 }; 62 63 /* DT clock ID to clock name mappings */ 64 static struct tegra210_car_clock_id { 65 const char *name; 66 u_int id; 67 } tegra210_car_clock_ids[] = { 68 { "ISPB", 3 }, 69 { "RTC", 4 }, 70 { "TIMER", 5 }, 71 { "UARTA", 6 }, 72 { "GPIO", 8 }, 73 { "SDMMC2", 9 }, 74 { "I2S1", 11 }, 75 { "I2C1", 12 }, 76 { "SDMMC1", 14 }, 77 { "SDMMC4", 15 }, 78 { "PWM", 17 }, 79 { "I2S2", 18 }, 80 { "USBD", 22 }, 81 { "ISP", 23 }, 82 { "DISP2", 26 }, 83 { "DISP1", 27 }, 84 { "HOST1X", 28 }, 85 { "I2S0", 30 }, 86 { "MC", 32 }, 87 { "AHBDMA", 33 }, 88 { "APBDMA", 34 }, 89 { "PMC", 38 }, 90 { "KFUSE", 40 }, 91 { "SBC1", 41 }, 92 { "SBC2", 44 }, 93 { "SBC3", 46 }, 94 { "I2C5", 47 }, 95 { "DSIA", 48 }, 96 { "CSI", 52 }, 97 { "I2C2", 54 }, 98 { "UARTC", 55 }, 99 { "MIPI_CAL", 56 }, 100 { "EMC", 57 }, 101 { "USB2", 58 }, 102 { "BSEV", 63 }, 103 { "UARTD", 65 }, 104 { "I2C3", 67 }, 105 { "SBC4", 68 }, 106 { "SDMMC3", 69 }, 107 { "PCIE", 70 }, 108 { "OWR", 71 }, 109 { "AFI", 72 }, 110 { "CSITE", 73 }, 111 { "SOC_THERM", 78 }, 112 { "DTV", 79 }, 113 { "I2CSLOW", 81 }, 114 { "DSIB", 82 }, 115 { "TSEC", 83 }, 116 { "XUSB_HOST", 89 }, 117 { "CSUS", 92 }, 118 { "MSELECT", 99 }, 119 { "TSENSOR", 100 }, 120 { "I2S3", 101 }, 121 { "I2S4", 102 }, 122 { "I2C4", 103 }, 123 { "D_AUDIO", 106 }, 124 { "APB2APE", 107 }, 125 { "HDA2CODEC_2X", 111 }, 126 { "SPDIF_2X", 118 }, 127 { "ACTMON", 119 }, 128 { "EXTERN1", 120 }, 129 { "EXTERN2", 121 }, 130 { "EXTERN3", 122 }, 131 { "SATA_OOB", 123 }, 132 { "SATA", 124 }, 133 { "HDA", 125 }, 134 { "HDA2HDMI", 128 }, 135 { "XUSB_GATE", 143 }, 136 { "CILAB", 144 }, 137 { "CILCD", 145 }, 138 { "CILE", 146 }, 139 { "DSIALP", 147 }, 140 { "DSIBLP", 148 }, 141 { "ENTROPY", 149 }, 142 { "XUSB_SS", 156 }, 143 { "DMIC1", 161 }, 144 { "DMIC2", 162 }, 145 { "I2C6", 166 }, 146 { "VIM2_CLK", 171 }, 147 { "MIPIBIF", 173 }, 148 { "CLK72MHZ", 177 }, 149 { "VIC03", 178 }, 150 { "DPAUX", 181 }, 151 { "SOR0", 182 }, 152 { "SOR1", 183 }, 153 { "GPU", 184 }, 154 { "DBGAPB", 185 }, 155 { "PLL_P_OUT_ADSP", 187 }, 156 { "PLL_G_REF", 189 }, 157 { "SDMMC_LEGACY", 193 }, 158 { "NVDEC", 194 }, 159 { "NVJPG", 195 }, 160 { "DMIC3", 197 }, 161 { "APE", 198 }, 162 { "MAUD", 202 }, 163 { "TSECB", 206 }, 164 { "DPAUX1", 207 }, 165 { "VI_I2C", 208 }, 166 { "HSIC_TRK", 209 }, 167 { "USB2_TRK", 210 }, 168 { "QSPI", 211 }, 169 { "UARTAPE", 212 }, 170 { "NVENC", 219 }, 171 { "SOR_SAFE", 222 }, 172 { "PLL_P_OUT_CPU", 223 }, 173 { "UARTB", 224 }, 174 { "VFIR", 225 }, 175 { "SPDIF_IN", 226 }, 176 { "SPDIF_OUT", 227 }, 177 { "VI", 228 }, 178 { "VI_SENSOR", 229 }, 179 { "FUSE", 230 }, 180 { "FUSE_BURN", 231 }, 181 { "CLK_32K", 232 }, 182 { "CLK_M", 233 }, 183 { "CLK_M_DIV2", 234 }, 184 { "CLK_M_DIV4", 235 }, 185 { "PLL_REF", 236 }, 186 { "PLL_C", 237 }, 187 { "PLL_C_OUT1", 238 }, 188 { "PLL_C2", 239 }, 189 { "PLL_C3", 240 }, 190 { "PLL_M", 241 }, 191 { "PLL_M_OUT1", 242 }, 192 { "PLL_P", 243 }, 193 { "PLL_P_OUT1", 244 }, 194 { "PLL_P_OUT2", 245 }, 195 { "PLL_P_OUT3", 246 }, 196 { "PLL_P_OUT4", 247 }, 197 { "PLL_A", 248 }, 198 { "PLL_A_OUT0", 249 }, 199 { "PLL_D", 250 }, 200 { "PLL_D_OUT0", 251 }, 201 { "PLL_D2", 252 }, 202 { "PLL_D2_OUT0", 253 }, 203 { "PLL_U", 254 }, 204 { "PLL_U_480M", 255 }, 205 { "PLL_U_60M", 256 }, 206 { "PLL_U_48M", 257 }, 207 { "PLL_X", 259 }, 208 { "PLL_X_OUT0", 260 }, 209 { "PLL_RE_VCO", 261 }, 210 { "PLL_RE_OUT", 262 }, 211 { "PLL_E", 263 }, 212 { "SPDIF_IN_SYNC", 264 }, 213 { "I2S0_SYNC", 265 }, 214 { "I2S1_SYNC", 266 }, 215 { "I2S2_SYNC", 267 }, 216 { "I2S3_SYNC", 268 }, 217 { "I2S4_SYNC", 269 }, 218 { "VIMCLK_SYNC", 270 }, 219 { "AUDIO0", 271 }, 220 { "AUDIO1", 272 }, 221 { "AUDIO2", 273 }, 222 { "AUDIO3", 274 }, 223 { "AUDIO4", 275 }, 224 { "SPDIF", 276 }, 225 { "CLK_OUT_1", 277 }, 226 { "CLK_OUT_2", 278 }, 227 { "CLK_OUT_3", 279 }, 228 { "BLINK", 280 }, 229 { "SOR1_SRC", 282 }, 230 { "XUSB_HOST_SRC", 284 }, 231 { "XUSB_FALCON_SRC", 285 }, 232 { "XUSB_FS_SRC", 286 }, 233 { "XUSB_SS_SRC", 287 }, 234 { "XUSB_DEV_SRC", 288 }, 235 { "XUSB_DEV", 289 }, 236 { "XUSB_HS_SRC", 290 }, 237 { "SCLK", 291 }, 238 { "HCLK", 292 }, 239 { "PCLK", 293 }, 240 { "CCLK_G", 294 }, 241 { "CCLK_LP", 295 }, 242 { "DFLL_REF", 296 }, 243 { "DFLL_SOC", 297 }, 244 { "VI_SENSOR2", 298 }, 245 { "PLL_P_OUT5", 299 }, 246 { "CML0", 300 }, 247 { "CML1", 301 }, 248 { "PLL_C4", 302 }, 249 { "PLL_DP", 303 }, 250 { "PLL_E_MUX", 304 }, 251 { "PLL_MB", 305 }, 252 { "PLL_A1", 306 }, 253 { "PLL_D_DSI_OUT", 307 }, 254 { "PLL_C4_OUT0", 308 }, 255 { "PLL_C4_OUT1", 309 }, 256 { "PLL_C4_OUT2", 310 }, 257 { "PLL_C4_OUT3", 311 }, 258 { "PLL_U_OUT", 312 }, 259 { "PLL_U_OUT1", 313 }, 260 { "PLL_U_OUT2", 314 }, 261 { "USB2_HSIC_TRK", 315 }, 262 { "PLL_P_OUT_HSIO", 316 }, 263 { "PLL_P_OUT_XUSB", 317 }, 264 { "XUSB_SSP_SRC", 318 }, 265 { "PLL_RE_OUT1", 319 }, 266 { "AUDIO0_MUX", 350 }, 267 { "AUDIO1_MUX", 351 }, 268 { "AUDIO2_MUX", 352 }, 269 { "AUDIO3_MUX", 353 }, 270 { "AUDIO4_MUX", 354 }, 271 { "SPDIF_MUX", 355 }, 272 { "CLK_OUT_1_MUX", 356 }, 273 { "CLK_OUT_2_MUX", 357 }, 274 { "CLK_OUT_3_MUX", 358 }, 275 { "DSIA_MUX", 359 }, 276 { "DSIB_MUX", 360 }, 277 { "SOR0_LVDS", 361 }, 278 { "XUSB_SS_DIV2", 362 }, 279 { "PLL_M_UD", 363 }, 280 { "PLL_C_UD", 364 }, 281 { "SCLK_MUX", 365 }, 282 }; 283 284 static struct clk *tegra210_car_clock_get(void *, const char *); 285 static void tegra210_car_clock_put(void *, struct clk *); 286 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 287 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 288 static int tegra210_car_clock_enable(void *, struct clk *); 289 static int tegra210_car_clock_disable(void *, struct clk *); 290 static int tegra210_car_clock_set_parent(void *, struct clk *, 291 struct clk *); 292 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 293 294 static const struct clk_funcs tegra210_car_clock_funcs = { 295 .get = tegra210_car_clock_get, 296 .put = tegra210_car_clock_put, 297 .get_rate = tegra210_car_clock_get_rate, 298 .set_rate = tegra210_car_clock_set_rate, 299 .enable = tegra210_car_clock_enable, 300 .disable = tegra210_car_clock_disable, 301 .set_parent = tegra210_car_clock_set_parent, 302 .get_parent = tegra210_car_clock_get_parent, 303 }; 304 305 #define CLK_FIXED(_name, _rate) { \ 306 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 307 .u = { .fixed = { .rate = (_rate) } } \ 308 } 309 310 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 311 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 312 .parent = (_parent), \ 313 .u = { \ 314 .pll = { \ 315 .base_reg = (_base), \ 316 .divm_mask = (_divm), \ 317 .divn_mask = (_divn), \ 318 .divp_mask = (_divp), \ 319 } \ 320 } \ 321 } 322 323 #define CLK_MUX(_name, _reg, _bits, _p) { \ 324 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 325 .u = { \ 326 .mux = { \ 327 .nparents = __arraycount(_p), \ 328 .parents = (_p), \ 329 .reg = (_reg), \ 330 .bits = (_bits) \ 331 } \ 332 } \ 333 } 334 335 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 336 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 337 .parent = (_parent), \ 338 .u = { \ 339 .fixed_div = { \ 340 .div = (_div) \ 341 } \ 342 } \ 343 } 344 345 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 346 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 347 .parent = (_parent), \ 348 .u = { \ 349 .div = { \ 350 .reg = (_reg), \ 351 .bits = (_bits) \ 352 } \ 353 } \ 354 } 355 356 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 357 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 358 .type = TEGRA_CLK_GATE, \ 359 .parent = (_parent), \ 360 .u = { \ 361 .gate = { \ 362 .set_reg = (_set), \ 363 .clr_reg = (_clr), \ 364 .bits = (_bits), \ 365 } \ 366 } \ 367 } 368 369 #define CLK_GATE_L(_name, _parent, _bits) \ 370 CLK_GATE(_name, _parent, \ 371 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 372 _bits) 373 374 #define CLK_GATE_H(_name, _parent, _bits) \ 375 CLK_GATE(_name, _parent, \ 376 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 377 _bits) 378 379 #define CLK_GATE_U(_name, _parent, _bits) \ 380 CLK_GATE(_name, _parent, \ 381 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 382 _bits) 383 384 #define CLK_GATE_V(_name, _parent, _bits) \ 385 CLK_GATE(_name, _parent, \ 386 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 387 _bits) 388 389 #define CLK_GATE_W(_name, _parent, _bits) \ 390 CLK_GATE(_name, _parent, \ 391 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 392 _bits) 393 394 #define CLK_GATE_X(_name, _parent, _bits) \ 395 CLK_GATE(_name, _parent, \ 396 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 397 _bits) 398 399 #define CLK_GATE_Y(_name, _parent, _bits) \ 400 CLK_GATE(_name, _parent, \ 401 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 402 _bits) 403 404 405 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 406 CLK_GATE(_name, _parent, _reg, _reg, _bits) 407 408 static const char *mux_uart_p[] = 409 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 410 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 411 412 static const char *mux_sdmmc1_p[] = 413 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 414 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 415 416 static const char *mux_sdmmc2_4_p[] = 417 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 418 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 419 420 static const char *mux_sdmmc3_p[] = 421 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 422 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 423 424 static const char *mux_i2c_p[] = 425 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 426 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 427 428 static const char *mux_xusb_host_p[] = 429 { "CLK_M", "PLL_P", NULL, NULL, 430 NULL, "PLL_REF", NULL, NULL }; 431 432 static const char *mux_xusb_fs_p[] = 433 { "CLK_M", NULL, "PLL_U_48M", NULL, 434 "PLL_P", NULL, "PLL_U_480M", NULL }; 435 436 static const char *mux_xusb_ss_p[] = 437 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 438 NULL, NULL, NULL, NULL }; 439 440 static struct tegra_clk tegra210_car_clocks[] = { 441 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 442 443 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 444 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 445 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 446 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 447 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 448 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 449 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 450 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 451 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 452 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 453 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 454 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 455 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 456 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 457 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 458 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 459 460 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 461 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 462 463 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 464 mux_uart_p), 465 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 466 mux_uart_p), 467 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 468 mux_uart_p), 469 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 470 mux_uart_p), 471 472 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 473 mux_sdmmc1_p), 474 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 475 mux_sdmmc2_4_p), 476 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 477 mux_sdmmc3_p), 478 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 479 mux_sdmmc2_4_p), 480 481 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 487 488 CLK_MUX("MUX_XUSB_HOST", 489 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 490 mux_xusb_host_p), 491 CLK_MUX("MUX_XUSB_FALCON", 492 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 493 mux_xusb_host_p), 494 CLK_MUX("MUX_XUSB_SS", 495 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 496 mux_xusb_ss_p), 497 CLK_MUX("MUX_XUSB_FS", 498 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 499 mux_xusb_fs_p), 500 501 CLK_DIV("DIV_UARTA", "MUX_UARTA", 502 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 503 CLK_DIV("DIV_UARTB", "MUX_UARTB", 504 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 505 CLK_DIV("DIV_UARTC", "MUX_UARTC", 506 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 507 CLK_DIV("DIV_UARTD", "MUX_UARTD", 508 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 509 510 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 511 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 512 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 513 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 514 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 515 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 516 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 517 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 518 519 CLK_DIV("DIV_I2C1", "MUX_I2C1", 520 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 521 CLK_DIV("DIV_I2C2", "MUX_I2C2", 522 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 523 CLK_DIV("DIV_I2C3", "MUX_I2C3", 524 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 525 CLK_DIV("DIV_I2C4", "MUX_I2C4", 526 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 527 CLK_DIV("DIV_I2C5", "MUX_I2C5", 528 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 529 CLK_DIV("DIV_I2C6", "MUX_I2C6", 530 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 531 532 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 533 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 534 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 535 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 536 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 537 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 538 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 539 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 540 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 541 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 542 543 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 544 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 545 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 546 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 547 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 548 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 549 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 550 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 551 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 552 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 553 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 554 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 555 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 556 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 557 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 558 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 559 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 560 CLK_GATE_Y("USB2_TRK", "UBS2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 561 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 562 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 563 }; 564 565 struct tegra210_init_parent { 566 const char *clock; 567 const char *parent; 568 } tegra210_init_parents[] = { 569 { "SDMMC1", "PLL_P" }, 570 { "SDMMC2", "PLL_P" }, 571 { "SDMMC3", "PLL_P" }, 572 { "SDMMC4", "PLL_P" }, 573 { "XUSB_HOST_SRC", "PLL_P" }, 574 { "XUSB_FALCON_SRC", "PLL_P" }, 575 { "XUSB_SS_SRC", "PLL_U_480M" }, 576 { "XUSB_FS_SRC", "PLL_U_48M" }, 577 }; 578 579 struct tegra210_car_rst { 580 u_int set_reg; 581 u_int clr_reg; 582 u_int mask; 583 }; 584 585 static struct tegra210_car_reset_reg { 586 u_int set_reg; 587 u_int clr_reg; 588 } tegra210_car_reset_regs[] = { 589 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 590 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 591 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 592 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 593 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 594 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 595 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 596 }; 597 598 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 599 static void tegra210_car_reset_release(device_t, void *); 600 static int tegra210_car_reset_assert(device_t, void *); 601 static int tegra210_car_reset_deassert(device_t, void *); 602 603 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 604 .acquire = tegra210_car_reset_acquire, 605 .release = tegra210_car_reset_release, 606 .reset_assert = tegra210_car_reset_assert, 607 .reset_deassert = tegra210_car_reset_deassert, 608 }; 609 610 struct tegra210_car_softc { 611 device_t sc_dev; 612 bus_space_tag_t sc_bst; 613 bus_space_handle_t sc_bsh; 614 615 struct clk_domain sc_clkdom; 616 617 u_int sc_clock_cells; 618 u_int sc_reset_cells; 619 620 kmutex_t sc_rndlock; 621 krndsource_t sc_rndsource; 622 }; 623 624 static void tegra210_car_init(struct tegra210_car_softc *); 625 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 626 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 627 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 628 static void tegra210_car_parent_init(struct tegra210_car_softc *); 629 630 631 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 632 tegra210_car_match, tegra210_car_attach, NULL, NULL); 633 634 static int 635 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 636 { 637 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 638 struct fdt_attach_args * const faa = aux; 639 640 #if 0 641 return of_match_compatible(faa->faa_phandle, compatible); 642 #else 643 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 644 return 0; 645 646 return 999; 647 #endif 648 } 649 650 static void 651 tegra210_car_attach(device_t parent, device_t self, void *aux) 652 { 653 struct tegra210_car_softc * const sc = device_private(self); 654 struct fdt_attach_args * const faa = aux; 655 const int phandle = faa->faa_phandle; 656 bus_addr_t addr; 657 bus_size_t size; 658 int error, n; 659 660 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 661 aprint_error(": couldn't get registers\n"); 662 return; 663 } 664 665 sc->sc_dev = self; 666 sc->sc_bst = faa->faa_bst; 667 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 668 if (error) { 669 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 670 return; 671 } 672 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 673 sc->sc_clock_cells = 1; 674 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 675 sc->sc_reset_cells = 1; 676 677 aprint_naive("\n"); 678 aprint_normal(": CAR\n"); 679 680 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 681 sc->sc_clkdom.priv = sc; 682 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 683 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 684 685 fdtbus_register_clock_controller(self, phandle, 686 &tegra210_car_fdtclock_funcs); 687 fdtbus_register_reset_controller(self, phandle, 688 &tegra210_car_fdtreset_funcs); 689 690 tegra210_car_init(sc); 691 692 #ifdef TEGRA210_CAR_DEBUG 693 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 694 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 695 struct clk *clk_parent = clk_get_parent(clk); 696 device_printf(self, "clk %s (parent %s): ", clk->name, 697 clk_parent ? clk_parent->name : "none"); 698 printf("%u Hz\n", clk_get_rate(clk)); 699 } 700 #endif 701 } 702 703 static void 704 tegra210_car_init(struct tegra210_car_softc *sc) 705 { 706 tegra210_car_parent_init(sc); 707 tegra210_car_utmip_init(sc); 708 tegra210_car_xusb_init(sc); 709 tegra210_car_watchdog_init(sc); 710 } 711 712 static void 713 tegra210_car_parent_init(struct tegra210_car_softc *sc) 714 { 715 struct clk *clk, *clk_parent; 716 int error; 717 u_int n; 718 719 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 720 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 721 KASSERT(clk != NULL); 722 clk_parent = clk_get(&sc->sc_clkdom, 723 tegra210_init_parents[n].parent); 724 KASSERT(clk_parent != NULL); 725 726 error = clk_set_parent(clk, clk_parent); 727 if (error) { 728 aprint_error_dev(sc->sc_dev, 729 "couldn't set '%s' parent to '%s': %d\n", 730 clk->name, clk_parent->name, error); 731 } 732 clk_put(clk_parent); 733 clk_put(clk); 734 } 735 } 736 737 static void 738 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 739 { 740 bus_space_tag_t bst = sc->sc_bst; 741 bus_space_handle_t bsh = sc->sc_bsh; 742 743 /* 744 * Set up the UTMI PLL. 745 */ 746 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 747 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 748 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 749 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 750 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 751 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 752 delay(10); 753 /* TODO UTMIP_PLL_CFG0 */ 754 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 755 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 756 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 757 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 758 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 759 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 760 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 761 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 762 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 763 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 764 765 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 766 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 767 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 768 769 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 770 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 771 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 772 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 773 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 774 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 775 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 776 777 /* 778 * Set up UTMI PLL under hardware control 779 */ 780 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 781 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 782 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 783 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 784 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 785 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 786 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 787 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 788 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 789 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 790 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 791 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 792 delay(1); 793 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 794 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 795 } 796 797 static void 798 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 799 { 800 const bus_space_tag_t bst = sc->sc_bst; 801 const bus_space_handle_t bsh = sc->sc_bsh; 802 uint32_t val; 803 804 /* 805 * Set up the PLLU. 806 */ 807 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 808 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 809 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 810 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 811 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 812 delay(5); 813 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 814 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 815 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 816 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 817 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 818 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 819 do { 820 delay(2); 821 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 822 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 823 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 824 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 825 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 826 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 827 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 828 delay(2); 829 830 /* 831 * Set up PLLREFE 832 */ 833 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 834 0, CAR_PLLREFE_MISC_IDDQ); 835 delay(5); 836 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 837 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 838 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 839 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 840 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 841 CAR_PLLREFE_BASE_DIVM | 842 CAR_PLLREFE_BASE_DIVN | 843 CAR_PLLREFE_BASE_DIVP | 844 CAR_PLLREFE_BASE_KCP); 845 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 846 CAR_PLLREFE_BASE_ENABLE, 0); 847 do { 848 delay(2); 849 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 850 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 851 852 /* 853 * Set up the PLLE. 854 */ 855 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 856 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 857 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 858 delay(5); 859 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 860 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 861 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 862 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 863 CAR_PLLE_BASE_DIVP_CML | 864 CAR_PLLE_BASE_DIVN | 865 CAR_PLLE_BASE_DIVM); 866 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 867 CAR_PLLE_MISC_PTS, 868 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 869 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 870 do { 871 delay(2); 872 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 873 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 874 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 875 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 876 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 877 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 878 CAR_PLLE_SS_CNTL_SSCINC | 879 CAR_PLLE_SS_CNTL_SSCINCINTRV | 880 CAR_PLLE_SS_CNTL_SSCMAX | 881 CAR_PLLE_SS_CNTL_SSCINVERT | 882 CAR_PLLE_SS_CNTL_SSCCENTER | 883 CAR_PLLE_SS_CNTL_BYPASS_SS | 884 CAR_PLLE_SS_CNTL_SSCBYP); 885 delay(1); 886 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 887 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 888 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 889 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 890 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 891 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 892 delay(1); 893 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 894 895 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 896 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 897 } 898 899 static void 900 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 901 { 902 const bus_space_tag_t bst = sc->sc_bst; 903 const bus_space_handle_t bsh = sc->sc_bsh; 904 905 /* Enable watchdog timer reset for system */ 906 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 907 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 908 } 909 910 static struct tegra_clk * 911 tegra210_car_clock_find(const char *name) 912 { 913 u_int n; 914 915 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 916 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 917 return &tegra210_car_clocks[n]; 918 } 919 } 920 921 return NULL; 922 } 923 924 static struct tegra_clk * 925 tegra210_car_clock_find_by_id(u_int clock_id) 926 { 927 u_int n; 928 929 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 930 if (tegra210_car_clock_ids[n].id == clock_id) { 931 const char *name = tegra210_car_clock_ids[n].name; 932 return tegra210_car_clock_find(name); 933 } 934 } 935 936 return NULL; 937 } 938 939 static struct clk * 940 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 941 { 942 struct tegra210_car_softc * const sc = device_private(dev); 943 struct tegra_clk *tclk; 944 945 if (len != sc->sc_clock_cells * 4) { 946 return NULL; 947 } 948 949 const u_int clock_id = be32dec(data); 950 951 tclk = tegra210_car_clock_find_by_id(clock_id); 952 if (tclk) 953 return TEGRA_CLK_BASE(tclk); 954 955 return NULL; 956 } 957 958 static struct clk * 959 tegra210_car_clock_get(void *priv, const char *name) 960 { 961 struct tegra_clk *tclk; 962 963 tclk = tegra210_car_clock_find(name); 964 if (tclk == NULL) 965 return NULL; 966 967 atomic_inc_uint(&tclk->refcnt); 968 969 return TEGRA_CLK_BASE(tclk); 970 } 971 972 static void 973 tegra210_car_clock_put(void *priv, struct clk *clk) 974 { 975 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 976 977 KASSERT(tclk->refcnt > 0); 978 979 atomic_dec_uint(&tclk->refcnt); 980 } 981 982 static u_int 983 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 984 struct tegra_clk *tclk) 985 { 986 struct tegra_pll_clk *tpll = &tclk->u.pll; 987 struct tegra_clk *tclk_parent; 988 bus_space_tag_t bst = sc->sc_bst; 989 bus_space_handle_t bsh = sc->sc_bsh; 990 u_int divm, divn, divp; 991 uint64_t rate; 992 993 KASSERT(tclk->type == TEGRA_CLK_PLL); 994 995 tclk_parent = tegra210_car_clock_find(tclk->parent); 996 KASSERT(tclk_parent != NULL); 997 998 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 999 TEGRA_CLK_BASE(tclk_parent)); 1000 1001 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1002 divm = __SHIFTOUT(base, tpll->divm_mask); 1003 divn = __SHIFTOUT(base, tpll->divn_mask); 1004 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1005 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1006 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1007 /* XXX divp is not applied to PLLP's primary output */ 1008 divp = 0; 1009 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1010 divp = 0; 1011 divm *= __SHIFTOUT(base, tpll->divp_mask); 1012 } else { 1013 divp = __SHIFTOUT(base, tpll->divp_mask); 1014 } 1015 1016 rate = (uint64_t)rate_parent * divn; 1017 return rate / (divm << divp); 1018 } 1019 1020 static int 1021 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1022 struct tegra_clk *tclk, u_int rate) 1023 { 1024 struct tegra_pll_clk *tpll = &tclk->u.pll; 1025 bus_space_tag_t bst = sc->sc_bst; 1026 bus_space_handle_t bsh = sc->sc_bsh; 1027 struct clk *clk_parent; 1028 uint32_t bp, base; 1029 1030 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1031 if (clk_parent == NULL) 1032 return EIO; 1033 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1034 if (rate_parent == 0) 1035 return EIO; 1036 1037 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1038 const u_int divm = 1; 1039 const u_int divn = rate / rate_parent; 1040 const u_int divp = 0; 1041 1042 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1043 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1044 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1045 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1046 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1047 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1048 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1049 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1050 1051 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1052 base &= ~CAR_PLLX_BASE_DIVM; 1053 base &= ~CAR_PLLX_BASE_DIVN; 1054 base &= ~CAR_PLLX_BASE_DIVP; 1055 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1056 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1057 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1058 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1059 1060 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1061 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1062 do { 1063 delay(2); 1064 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1065 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1066 delay(100); 1067 1068 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1069 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1070 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1071 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1072 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1073 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1074 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1075 1076 return 0; 1077 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1078 const u_int divm = 1; 1079 const u_int pldiv = 1; 1080 const u_int divn = (rate << pldiv) / rate_parent; 1081 1082 /* Set frequency */ 1083 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1084 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1085 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1086 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1087 CAR_PLLD2_BASE_REF_SRC_SEL | 1088 CAR_PLLD2_BASE_DIVM | 1089 CAR_PLLD2_BASE_DIVN | 1090 CAR_PLLD2_BASE_DIVP); 1091 1092 return 0; 1093 } else { 1094 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1095 tclk->base.name, rate); 1096 /* TODO */ 1097 return EOPNOTSUPP; 1098 } 1099 } 1100 1101 static int 1102 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1103 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1104 { 1105 struct tegra_mux_clk *tmux = &tclk->u.mux; 1106 bus_space_tag_t bst = sc->sc_bst; 1107 bus_space_handle_t bsh = sc->sc_bsh; 1108 uint32_t v; 1109 u_int src; 1110 1111 KASSERT(tclk->type == TEGRA_CLK_MUX); 1112 1113 for (src = 0; src < tmux->nparents; src++) { 1114 if (tmux->parents[src] == NULL) { 1115 continue; 1116 } 1117 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1118 break; 1119 } 1120 } 1121 if (src == tmux->nparents) { 1122 return EINVAL; 1123 } 1124 1125 v = bus_space_read_4(bst, bsh, tmux->reg); 1126 v &= ~tmux->bits; 1127 v |= __SHIFTIN(src, tmux->bits); 1128 bus_space_write_4(bst, bsh, tmux->reg, v); 1129 1130 return 0; 1131 } 1132 1133 static struct tegra_clk * 1134 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1135 struct tegra_clk *tclk) 1136 { 1137 struct tegra_mux_clk *tmux = &tclk->u.mux; 1138 bus_space_tag_t bst = sc->sc_bst; 1139 bus_space_handle_t bsh = sc->sc_bsh; 1140 1141 KASSERT(tclk->type == TEGRA_CLK_MUX); 1142 1143 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1144 const u_int src = __SHIFTOUT(v, tmux->bits); 1145 1146 KASSERT(src < tmux->nparents); 1147 1148 if (tmux->parents[src] == NULL) { 1149 return NULL; 1150 } 1151 1152 return tegra210_car_clock_find(tmux->parents[src]); 1153 } 1154 1155 static u_int 1156 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1157 struct tegra_clk *tclk) 1158 { 1159 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1160 struct clk *clk_parent; 1161 1162 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1163 if (clk_parent == NULL) 1164 return 0; 1165 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1166 1167 return parent_rate / tfixed_div->div; 1168 } 1169 1170 static u_int 1171 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1172 struct tegra_clk *tclk) 1173 { 1174 struct tegra_div_clk *tdiv = &tclk->u.div; 1175 bus_space_tag_t bst = sc->sc_bst; 1176 bus_space_handle_t bsh = sc->sc_bsh; 1177 struct clk *clk_parent; 1178 u_int rate; 1179 1180 KASSERT(tclk->type == TEGRA_CLK_DIV); 1181 1182 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1183 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1184 1185 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1186 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1187 1188 switch (tdiv->reg) { 1189 case CAR_CLKSRC_I2C1_REG: 1190 case CAR_CLKSRC_I2C2_REG: 1191 case CAR_CLKSRC_I2C3_REG: 1192 case CAR_CLKSRC_I2C4_REG: 1193 case CAR_CLKSRC_I2C5_REG: 1194 case CAR_CLKSRC_I2C6_REG: 1195 rate = parent_rate / (raw_div + 1); 1196 break; 1197 case CAR_CLKSRC_UARTA_REG: 1198 case CAR_CLKSRC_UARTB_REG: 1199 case CAR_CLKSRC_UARTC_REG: 1200 case CAR_CLKSRC_UARTD_REG: 1201 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1202 rate = parent_rate / ((raw_div / 2) + 1); 1203 } else { 1204 rate = parent_rate; 1205 } 1206 break; 1207 case CAR_CLKSRC_SDMMC2_REG: 1208 case CAR_CLKSRC_SDMMC4_REG: 1209 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1210 case 1: 1211 case 2: 1212 case 5: 1213 raw_div = 0; /* ignore divisor for _LJ options */ 1214 break; 1215 } 1216 /* FALLTHROUGH */ 1217 default: 1218 rate = parent_rate / ((raw_div / 2) + 1); 1219 break; 1220 } 1221 1222 return rate; 1223 } 1224 1225 static int 1226 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1227 struct tegra_clk *tclk, u_int rate) 1228 { 1229 struct tegra_div_clk *tdiv = &tclk->u.div; 1230 bus_space_tag_t bst = sc->sc_bst; 1231 bus_space_handle_t bsh = sc->sc_bsh; 1232 struct clk *clk_parent; 1233 u_int raw_div; 1234 uint32_t v; 1235 1236 KASSERT(tclk->type == TEGRA_CLK_DIV); 1237 1238 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1239 if (clk_parent == NULL) 1240 return EINVAL; 1241 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1242 1243 v = bus_space_read_4(bst, bsh, tdiv->reg); 1244 1245 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1246 1247 switch (tdiv->reg) { 1248 case CAR_CLKSRC_UARTA_REG: 1249 case CAR_CLKSRC_UARTB_REG: 1250 case CAR_CLKSRC_UARTC_REG: 1251 case CAR_CLKSRC_UARTD_REG: 1252 if (rate == parent_rate) { 1253 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1254 } else if (rate) { 1255 v |= CAR_CLKSRC_UART_DIV_ENB; 1256 raw_div = (parent_rate / rate) * 2; 1257 if (raw_div >= 2) 1258 raw_div -= 2; 1259 } 1260 break; 1261 case CAR_CLKSRC_I2C1_REG: 1262 case CAR_CLKSRC_I2C2_REG: 1263 case CAR_CLKSRC_I2C3_REG: 1264 case CAR_CLKSRC_I2C4_REG: 1265 case CAR_CLKSRC_I2C5_REG: 1266 case CAR_CLKSRC_I2C6_REG: 1267 if (rate) 1268 raw_div = (parent_rate / rate) - 1; 1269 break; 1270 case CAR_CLKSRC_SDMMC1_REG: 1271 case CAR_CLKSRC_SDMMC2_REG: 1272 case CAR_CLKSRC_SDMMC3_REG: 1273 case CAR_CLKSRC_SDMMC4_REG: 1274 if (rate) { 1275 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1276 u_int calc_rate = 1277 parent_rate / ((raw_div / 2) + 1); 1278 if (calc_rate <= rate) 1279 break; 1280 } 1281 if (raw_div == 0x100) 1282 return EINVAL; 1283 } 1284 break; 1285 default: 1286 if (rate) { 1287 raw_div = (parent_rate / rate) * 2; 1288 if (raw_div >= 2) 1289 raw_div -= 2; 1290 } 1291 break; 1292 } 1293 1294 v &= ~tdiv->bits; 1295 v |= __SHIFTIN(raw_div, tdiv->bits); 1296 1297 bus_space_write_4(bst, bsh, tdiv->reg, v); 1298 1299 return 0; 1300 } 1301 1302 static int 1303 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1304 struct tegra_clk *tclk, bool enable) 1305 { 1306 struct tegra_gate_clk *tgate = &tclk->u.gate; 1307 bus_space_tag_t bst = sc->sc_bst; 1308 bus_space_handle_t bsh = sc->sc_bsh; 1309 bus_size_t reg; 1310 1311 KASSERT(tclk->type == TEGRA_CLK_GATE); 1312 1313 if (tgate->set_reg == tgate->clr_reg) { 1314 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1315 if (enable) { 1316 v |= tgate->bits; 1317 } else { 1318 v &= ~tgate->bits; 1319 } 1320 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1321 } else { 1322 if (enable) { 1323 reg = tgate->set_reg; 1324 } else { 1325 reg = tgate->clr_reg; 1326 } 1327 bus_space_write_4(bst, bsh, reg, tgate->bits); 1328 } 1329 1330 return 0; 1331 } 1332 1333 static u_int 1334 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1335 { 1336 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1337 struct clk *clk_parent; 1338 1339 switch (tclk->type) { 1340 case TEGRA_CLK_FIXED: 1341 return tclk->u.fixed.rate; 1342 case TEGRA_CLK_PLL: 1343 return tegra210_car_clock_get_rate_pll(priv, tclk); 1344 case TEGRA_CLK_MUX: 1345 case TEGRA_CLK_GATE: 1346 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1347 if (clk_parent == NULL) 1348 return EINVAL; 1349 return tegra210_car_clock_get_rate(priv, clk_parent); 1350 case TEGRA_CLK_FIXED_DIV: 1351 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1352 case TEGRA_CLK_DIV: 1353 return tegra210_car_clock_get_rate_div(priv, tclk); 1354 default: 1355 panic("tegra210: unknown tclk type %d", tclk->type); 1356 } 1357 } 1358 1359 static int 1360 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1361 { 1362 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1363 struct clk *clk_parent; 1364 1365 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1366 1367 switch (tclk->type) { 1368 case TEGRA_CLK_FIXED: 1369 case TEGRA_CLK_MUX: 1370 return EIO; 1371 case TEGRA_CLK_FIXED_DIV: 1372 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1373 if (clk_parent == NULL) 1374 return EIO; 1375 return tegra210_car_clock_set_rate(priv, clk_parent, 1376 rate * tclk->u.fixed_div.div); 1377 case TEGRA_CLK_GATE: 1378 return EINVAL; 1379 case TEGRA_CLK_PLL: 1380 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1381 case TEGRA_CLK_DIV: 1382 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1383 default: 1384 panic("tegra210: unknown tclk type %d", tclk->type); 1385 } 1386 } 1387 1388 static int 1389 tegra210_car_clock_enable(void *priv, struct clk *clk) 1390 { 1391 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1392 struct clk *clk_parent; 1393 1394 if (tclk->type != TEGRA_CLK_GATE) { 1395 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1396 if (clk_parent == NULL) 1397 return 0; 1398 return tegra210_car_clock_enable(priv, clk_parent); 1399 } 1400 1401 return tegra210_car_clock_enable_gate(priv, tclk, true); 1402 } 1403 1404 static int 1405 tegra210_car_clock_disable(void *priv, struct clk *clk) 1406 { 1407 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1408 1409 if (tclk->type != TEGRA_CLK_GATE) 1410 return EINVAL; 1411 1412 return tegra210_car_clock_enable_gate(priv, tclk, false); 1413 } 1414 1415 static int 1416 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1417 struct clk *clk_parent) 1418 { 1419 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1420 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1421 struct clk *nclk_parent; 1422 1423 if (tclk->type != TEGRA_CLK_MUX) { 1424 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1425 if (nclk_parent == clk_parent || nclk_parent == NULL) 1426 return EINVAL; 1427 return tegra210_car_clock_set_parent(priv, nclk_parent, 1428 clk_parent); 1429 } 1430 1431 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1432 } 1433 1434 static struct clk * 1435 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1436 { 1437 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1438 struct tegra_clk *tclk_parent = NULL; 1439 1440 switch (tclk->type) { 1441 case TEGRA_CLK_FIXED: 1442 case TEGRA_CLK_PLL: 1443 case TEGRA_CLK_FIXED_DIV: 1444 case TEGRA_CLK_DIV: 1445 case TEGRA_CLK_GATE: 1446 if (tclk->parent) { 1447 tclk_parent = tegra210_car_clock_find(tclk->parent); 1448 } 1449 break; 1450 case TEGRA_CLK_MUX: 1451 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1452 break; 1453 } 1454 1455 if (tclk_parent == NULL) 1456 return NULL; 1457 1458 return TEGRA_CLK_BASE(tclk_parent); 1459 } 1460 1461 static void * 1462 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1463 { 1464 struct tegra210_car_softc * const sc = device_private(dev); 1465 struct tegra210_car_rst *rst; 1466 1467 if (len != sc->sc_reset_cells * 4) 1468 return NULL; 1469 1470 const u_int reset_id = be32dec(data); 1471 1472 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1473 return NULL; 1474 1475 const u_int reg = reset_id / 32; 1476 1477 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1478 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1479 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1480 rst->mask = __BIT(reset_id % 32); 1481 1482 return rst; 1483 } 1484 1485 static void 1486 tegra210_car_reset_release(device_t dev, void *priv) 1487 { 1488 struct tegra210_car_rst *rst = priv; 1489 1490 kmem_free(rst, sizeof(*rst)); 1491 } 1492 1493 static int 1494 tegra210_car_reset_assert(device_t dev, void *priv) 1495 { 1496 struct tegra210_car_softc * const sc = device_private(dev); 1497 struct tegra210_car_rst *rst = priv; 1498 1499 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1500 1501 return 0; 1502 } 1503 1504 static int 1505 tegra210_car_reset_deassert(device_t dev, void *priv) 1506 { 1507 struct tegra210_car_softc * const sc = device_private(dev); 1508 struct tegra210_car_rst *rst = priv; 1509 1510 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1511 1512 return 0; 1513 } 1514
Indexes created Tue Sep 30 17:09:57 GMT 2025