tegra210_car.c revision 1.9
1 /* $NetBSD: tegra210_car.c,v 1.9 2017/09/23 23:58:31 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.9 2017/09/23 23:58:31 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/rndpool.h> 39 #include <sys/rndsource.h> 40 #include <sys/atomic.h> 41 #include <sys/kmem.h> 42 43 #include <dev/clk/clk_backend.h> 44 45 #include <arm/nvidia/tegra_reg.h> 46 #include <arm/nvidia/tegra210_carreg.h> 47 #include <arm/nvidia/tegra_clock.h> 48 #include <arm/nvidia/tegra_pmcreg.h> 49 #include <arm/nvidia/tegra_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 static int tegra210_car_match(device_t, cfdata_t, void *); 54 static void tegra210_car_attach(device_t, device_t, void *); 55 56 static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t); 57 58 static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = { 59 .decode = tegra210_car_clock_decode 60 }; 61 62 /* DT clock ID to clock name mappings */ 63 static struct tegra210_car_clock_id { 64 const char *name; 65 u_int id; 66 } tegra210_car_clock_ids[] = { 67 { "ISPB", 3 }, 68 { "RTC", 4 }, 69 { "TIMER", 5 }, 70 { "UARTA", 6 }, 71 { "GPIO", 8 }, 72 { "SDMMC2", 9 }, 73 { "I2S1", 11 }, 74 { "I2C1", 12 }, 75 { "SDMMC1", 14 }, 76 { "SDMMC4", 15 }, 77 { "PWM", 17 }, 78 { "I2S2", 18 }, 79 { "USBD", 22 }, 80 { "ISP", 23 }, 81 { "DISP2", 26 }, 82 { "DISP1", 27 }, 83 { "HOST1X", 28 }, 84 { "I2S0", 30 }, 85 { "MC", 32 }, 86 { "AHBDMA", 33 }, 87 { "APBDMA", 34 }, 88 { "PMC", 38 }, 89 { "KFUSE", 40 }, 90 { "SBC1", 41 }, 91 { "SBC2", 44 }, 92 { "SBC3", 46 }, 93 { "I2C5", 47 }, 94 { "DSIA", 48 }, 95 { "CSI", 52 }, 96 { "I2C2", 54 }, 97 { "UARTC", 55 }, 98 { "MIPI_CAL", 56 }, 99 { "EMC", 57 }, 100 { "USB2", 58 }, 101 { "BSEV", 63 }, 102 { "UARTD", 65 }, 103 { "I2C3", 67 }, 104 { "SBC4", 68 }, 105 { "SDMMC3", 69 }, 106 { "PCIE", 70 }, 107 { "OWR", 71 }, 108 { "AFI", 72 }, 109 { "CSITE", 73 }, 110 { "SOC_THERM", 78 }, 111 { "DTV", 79 }, 112 { "I2CSLOW", 81 }, 113 { "DSIB", 82 }, 114 { "TSEC", 83 }, 115 { "XUSB_HOST", 89 }, 116 { "CSUS", 92 }, 117 { "MSELECT", 99 }, 118 { "TSENSOR", 100 }, 119 { "I2S3", 101 }, 120 { "I2S4", 102 }, 121 { "I2C4", 103 }, 122 { "D_AUDIO", 106 }, 123 { "APB2APE", 107 }, 124 { "HDA2CODEC_2X", 111 }, 125 { "SPDIF_2X", 118 }, 126 { "ACTMON", 119 }, 127 { "EXTERN1", 120 }, 128 { "EXTERN2", 121 }, 129 { "EXTERN3", 122 }, 130 { "SATA_OOB", 123 }, 131 { "SATA", 124 }, 132 { "HDA", 125 }, 133 { "HDA2HDMI", 128 }, 134 { "XUSB_GATE", 143 }, 135 { "CILAB", 144 }, 136 { "CILCD", 145 }, 137 { "CILE", 146 }, 138 { "DSIALP", 147 }, 139 { "DSIBLP", 148 }, 140 { "ENTROPY", 149 }, 141 { "XUSB_SS", 156 }, 142 { "DMIC1", 161 }, 143 { "DMIC2", 162 }, 144 { "I2C6", 166 }, 145 { "VIM2_CLK", 171 }, 146 { "MIPIBIF", 173 }, 147 { "CLK72MHZ", 177 }, 148 { "VIC03", 178 }, 149 { "DPAUX", 181 }, 150 { "SOR0", 182 }, 151 { "SOR1", 183 }, 152 { "GPU", 184 }, 153 { "DBGAPB", 185 }, 154 { "PLL_P_OUT_ADSP", 187 }, 155 { "PLL_G_REF", 189 }, 156 { "SDMMC_LEGACY", 193 }, 157 { "NVDEC", 194 }, 158 { "NVJPG", 195 }, 159 { "DMIC3", 197 }, 160 { "APE", 198 }, 161 { "MAUD", 202 }, 162 { "TSECB", 206 }, 163 { "DPAUX1", 207 }, 164 { "VI_I2C", 208 }, 165 { "HSIC_TRK", 209 }, 166 { "USB2_TRK", 210 }, 167 { "QSPI", 211 }, 168 { "UARTAPE", 212 }, 169 { "NVENC", 219 }, 170 { "SOR_SAFE", 222 }, 171 { "PLL_P_OUT_CPU", 223 }, 172 { "UARTB", 224 }, 173 { "VFIR", 225 }, 174 { "SPDIF_IN", 226 }, 175 { "SPDIF_OUT", 227 }, 176 { "VI", 228 }, 177 { "VI_SENSOR", 229 }, 178 { "FUSE", 230 }, 179 { "FUSE_BURN", 231 }, 180 { "CLK_32K", 232 }, 181 { "CLK_M", 233 }, 182 { "CLK_M_DIV2", 234 }, 183 { "CLK_M_DIV4", 235 }, 184 { "PLL_REF", 236 }, 185 { "PLL_C", 237 }, 186 { "PLL_C_OUT1", 238 }, 187 { "PLL_C2", 239 }, 188 { "PLL_C3", 240 }, 189 { "PLL_M", 241 }, 190 { "PLL_M_OUT1", 242 }, 191 { "PLL_P", 243 }, 192 { "PLL_P_OUT1", 244 }, 193 { "PLL_P_OUT2", 245 }, 194 { "PLL_P_OUT3", 246 }, 195 { "PLL_P_OUT4", 247 }, 196 { "PLL_A", 248 }, 197 { "PLL_A_OUT0", 249 }, 198 { "PLL_D", 250 }, 199 { "PLL_D_OUT0", 251 }, 200 { "PLL_D2", 252 }, 201 { "PLL_D2_OUT0", 253 }, 202 { "PLL_U", 254 }, 203 { "PLL_U_480M", 255 }, 204 { "PLL_U_60M", 256 }, 205 { "PLL_U_48M", 257 }, 206 { "PLL_X", 259 }, 207 { "PLL_X_OUT0", 260 }, 208 { "PLL_RE_VCO", 261 }, 209 { "PLL_RE_OUT", 262 }, 210 { "PLL_E", 263 }, 211 { "SPDIF_IN_SYNC", 264 }, 212 { "I2S0_SYNC", 265 }, 213 { "I2S1_SYNC", 266 }, 214 { "I2S2_SYNC", 267 }, 215 { "I2S3_SYNC", 268 }, 216 { "I2S4_SYNC", 269 }, 217 { "VIMCLK_SYNC", 270 }, 218 { "AUDIO0", 271 }, 219 { "AUDIO1", 272 }, 220 { "AUDIO2", 273 }, 221 { "AUDIO3", 274 }, 222 { "AUDIO4", 275 }, 223 { "SPDIF", 276 }, 224 { "CLK_OUT_1", 277 }, 225 { "CLK_OUT_2", 278 }, 226 { "CLK_OUT_3", 279 }, 227 { "BLINK", 280 }, 228 { "SOR1_SRC", 282 }, 229 { "XUSB_HOST_SRC", 284 }, 230 { "XUSB_FALCON_SRC", 285 }, 231 { "XUSB_FS_SRC", 286 }, 232 { "XUSB_SS_SRC", 287 }, 233 { "XUSB_DEV_SRC", 288 }, 234 { "XUSB_DEV", 289 }, 235 { "XUSB_HS_SRC", 290 }, 236 { "SCLK", 291 }, 237 { "HCLK", 292 }, 238 { "PCLK", 293 }, 239 { "CCLK_G", 294 }, 240 { "CCLK_LP", 295 }, 241 { "DFLL_REF", 296 }, 242 { "DFLL_SOC", 297 }, 243 { "VI_SENSOR2", 298 }, 244 { "PLL_P_OUT5", 299 }, 245 { "CML0", 300 }, 246 { "CML1", 301 }, 247 { "PLL_C4", 302 }, 248 { "PLL_DP", 303 }, 249 { "PLL_E_MUX", 304 }, 250 { "PLL_MB", 305 }, 251 { "PLL_A1", 306 }, 252 { "PLL_D_DSI_OUT", 307 }, 253 { "PLL_C4_OUT0", 308 }, 254 { "PLL_C4_OUT1", 309 }, 255 { "PLL_C4_OUT2", 310 }, 256 { "PLL_C4_OUT3", 311 }, 257 { "PLL_U_OUT", 312 }, 258 { "PLL_U_OUT1", 313 }, 259 { "PLL_U_OUT2", 314 }, 260 { "USB2_HSIC_TRK", 315 }, 261 { "PLL_P_OUT_HSIO", 316 }, 262 { "PLL_P_OUT_XUSB", 317 }, 263 { "XUSB_SSP_SRC", 318 }, 264 { "PLL_RE_OUT1", 319 }, 265 { "AUDIO0_MUX", 350 }, 266 { "AUDIO1_MUX", 351 }, 267 { "AUDIO2_MUX", 352 }, 268 { "AUDIO3_MUX", 353 }, 269 { "AUDIO4_MUX", 354 }, 270 { "SPDIF_MUX", 355 }, 271 { "CLK_OUT_1_MUX", 356 }, 272 { "CLK_OUT_2_MUX", 357 }, 273 { "CLK_OUT_3_MUX", 358 }, 274 { "DSIA_MUX", 359 }, 275 { "DSIB_MUX", 360 }, 276 { "SOR0_LVDS", 361 }, 277 { "XUSB_SS_DIV2", 362 }, 278 { "PLL_M_UD", 363 }, 279 { "PLL_C_UD", 364 }, 280 { "SCLK_MUX", 365 }, 281 }; 282 283 static struct clk *tegra210_car_clock_get(void *, const char *); 284 static void tegra210_car_clock_put(void *, struct clk *); 285 static u_int tegra210_car_clock_get_rate(void *, struct clk *); 286 static int tegra210_car_clock_set_rate(void *, struct clk *, u_int); 287 static int tegra210_car_clock_enable(void *, struct clk *); 288 static int tegra210_car_clock_disable(void *, struct clk *); 289 static int tegra210_car_clock_set_parent(void *, struct clk *, 290 struct clk *); 291 static struct clk *tegra210_car_clock_get_parent(void *, struct clk *); 292 293 static const struct clk_funcs tegra210_car_clock_funcs = { 294 .get = tegra210_car_clock_get, 295 .put = tegra210_car_clock_put, 296 .get_rate = tegra210_car_clock_get_rate, 297 .set_rate = tegra210_car_clock_set_rate, 298 .enable = tegra210_car_clock_enable, 299 .disable = tegra210_car_clock_disable, 300 .set_parent = tegra210_car_clock_set_parent, 301 .get_parent = tegra210_car_clock_get_parent, 302 }; 303 304 #define CLK_FIXED(_name, _rate) { \ 305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \ 306 .u = { .fixed = { .rate = (_rate) } } \ 307 } 308 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \ 310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \ 311 .parent = (_parent), \ 312 .u = { \ 313 .pll = { \ 314 .base_reg = (_base), \ 315 .divm_mask = (_divm), \ 316 .divn_mask = (_divn), \ 317 .divp_mask = (_divp), \ 318 } \ 319 } \ 320 } 321 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ 323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \ 324 .u = { \ 325 .mux = { \ 326 .nparents = __arraycount(_p), \ 327 .parents = (_p), \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define CLK_FIXED_DIV(_name, _parent, _div) { \ 335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \ 336 .parent = (_parent), \ 337 .u = { \ 338 .fixed_div = { \ 339 .div = (_div) \ 340 } \ 341 } \ 342 } 343 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \ 346 .parent = (_parent), \ 347 .u = { \ 348 .div = { \ 349 .reg = (_reg), \ 350 .bits = (_bits) \ 351 } \ 352 } \ 353 } 354 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 357 .type = TEGRA_CLK_GATE, \ 358 .parent = (_parent), \ 359 .u = { \ 360 .gate = { \ 361 .set_reg = (_set), \ 362 .clr_reg = (_clr), \ 363 .bits = (_bits), \ 364 } \ 365 } \ 366 } 367 368 #define CLK_GATE_L(_name, _parent, _bits) \ 369 CLK_GATE(_name, _parent, \ 370 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \ 371 _bits) 372 373 #define CLK_GATE_H(_name, _parent, _bits) \ 374 CLK_GATE(_name, _parent, \ 375 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \ 376 _bits) 377 378 #define CLK_GATE_U(_name, _parent, _bits) \ 379 CLK_GATE(_name, _parent, \ 380 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \ 381 _bits) 382 383 #define CLK_GATE_V(_name, _parent, _bits) \ 384 CLK_GATE(_name, _parent, \ 385 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \ 386 _bits) 387 388 #define CLK_GATE_W(_name, _parent, _bits) \ 389 CLK_GATE(_name, _parent, \ 390 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \ 391 _bits) 392 393 #define CLK_GATE_X(_name, _parent, _bits) \ 394 CLK_GATE(_name, _parent, \ 395 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \ 396 _bits) 397 398 #define CLK_GATE_Y(_name, _parent, _bits) \ 399 CLK_GATE(_name, _parent, \ 400 CAR_CLK_ENB_Y_SET_REG, CAR_CLK_ENB_Y_CLR_REG, \ 401 _bits) 402 403 404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ 405 CLK_GATE(_name, _parent, _reg, _reg, _bits) 406 407 static const char *mux_uart_p[] = 408 { "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0", 409 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 410 411 static const char *mux_sdmmc1_p[] = 412 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT0", 413 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 414 415 static const char *mux_sdmmc2_4_p[] = 416 { "PLL_P", "PLL_C4_OUT2"/*LJ*/, "PLL_C4_OUT0"/*LJ*/, "PLL_C4_OUT2", 417 "PLL_M", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 418 419 static const char *mux_sdmmc3_p[] = 420 { "PLL_P", "PLL_A", "PLL_C", "PLL_C4_OUT2", 421 "PLL_C4_OUT1", "PLL_E", "CLK_M", "PLL_C4_OUT0" }; 422 423 static const char *mux_i2c_p[] = 424 { "PLL_P", "PLL_C2_OUT0", "PLL_C", "PLL_C4_OUT0", 425 NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" }; 426 427 static const char *mux_xusb_host_p[] = 428 { "CLK_M", "PLL_P", NULL, NULL, 429 NULL, "PLL_REF", NULL, NULL }; 430 431 static const char *mux_xusb_fs_p[] = 432 { "CLK_M", NULL, "PLL_U_48M", NULL, 433 "PLL_P", NULL, "PLL_U_480M", NULL }; 434 435 static const char *mux_xusb_ss_p[] = 436 { "CLK_M", "PLL_REF", "CLK_32K", "PLL_U_480M", 437 NULL, NULL, NULL, NULL }; 438 439 static struct tegra_clk tegra210_car_clocks[] = { 440 CLK_FIXED("CLK_M", TEGRA210_REF_FREQ), 441 442 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG, 443 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP), 444 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG, 445 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP), 446 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG, 447 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_DIVP), 448 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG, 449 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP), 450 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG, 451 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML), 452 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG, 453 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP), 454 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG, 455 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP), 456 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG, 457 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP), 458 459 CLK_FIXED_DIV("PLL_U_480M", "PLL_U", 1), 460 CLK_FIXED_DIV("PLL_U_48M", "PLL_U", 10), 461 462 CLK_MUX("MUX_UARTA", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC, 463 mux_uart_p), 464 CLK_MUX("MUX_UARTB", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC, 465 mux_uart_p), 466 CLK_MUX("MUX_UARTC", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC, 467 mux_uart_p), 468 CLK_MUX("MUX_UARTD", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC, 469 mux_uart_p), 470 471 CLK_MUX("MUX_SDMMC1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC, 472 mux_sdmmc1_p), 473 CLK_MUX("MUX_SDMMC2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC, 474 mux_sdmmc2_4_p), 475 CLK_MUX("MUX_SDMMC3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC, 476 mux_sdmmc3_p), 477 CLK_MUX("MUX_SDMMC4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC, 478 mux_sdmmc2_4_p), 479 480 CLK_MUX("MUX_I2C1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 481 CLK_MUX("MUX_I2C2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 482 CLK_MUX("MUX_I2C3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 483 CLK_MUX("MUX_I2C4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 484 CLK_MUX("MUX_I2C5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 485 CLK_MUX("MUX_I2C6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p), 486 487 CLK_MUX("MUX_XUSB_HOST", 488 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC, 489 mux_xusb_host_p), 490 CLK_MUX("MUX_XUSB_FALCON", 491 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC, 492 mux_xusb_host_p), 493 CLK_MUX("MUX_XUSB_SS", 494 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC, 495 mux_xusb_ss_p), 496 CLK_MUX("MUX_XUSB_FS", 497 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC, 498 mux_xusb_fs_p), 499 500 CLK_DIV("DIV_UARTA", "MUX_UARTA", 501 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV), 502 CLK_DIV("DIV_UARTB", "MUX_UARTB", 503 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV), 504 CLK_DIV("DIV_UARTC", "MUX_UARTC", 505 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV), 506 CLK_DIV("DIV_UARTD", "MUX_UARTD", 507 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV), 508 509 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1", 510 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV), 511 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2", 512 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV), 513 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3", 514 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV), 515 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4", 516 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV), 517 518 CLK_DIV("DIV_I2C1", "MUX_I2C1", 519 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV), 520 CLK_DIV("DIV_I2C2", "MUX_I2C2", 521 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV), 522 CLK_DIV("DIV_I2C3", "MUX_I2C3", 523 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV), 524 CLK_DIV("DIV_I2C4", "MUX_I2C4", 525 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV), 526 CLK_DIV("DIV_I2C5", "MUX_I2C5", 527 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV), 528 CLK_DIV("DIV_I2C6", "MUX_I2C6", 529 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV), 530 531 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST", 532 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV), 533 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS", 534 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV), 535 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS", 536 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV), 537 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON", 538 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV), 539 CLK_DIV("USB2_HSIC_TRK", "CLK_M", 540 CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV), 541 542 CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA), 543 CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB), 544 CLK_GATE_H("UARTC", "DIV_UARTC", CAR_DEV_H_UARTC), 545 CLK_GATE_U("UARTD", "DIV_UARTD", CAR_DEV_U_UARTD), 546 CLK_GATE_L("SDMMC1", "DIV_SDMMC1", CAR_DEV_L_SDMMC1), 547 CLK_GATE_L("SDMMC2", "DIV_SDMMC2", CAR_DEV_L_SDMMC2), 548 CLK_GATE_U("SDMMC3", "DIV_SDMMC3", CAR_DEV_U_SDMMC3), 549 CLK_GATE_L("SDMMC4", "DIV_SDMMC4", CAR_DEV_L_SDMMC4), 550 CLK_GATE_L("I2C1", "DIV_I2C1", CAR_DEV_L_I2C1), 551 CLK_GATE_H("I2C2", "DIV_I2C2", CAR_DEV_H_I2C2), 552 CLK_GATE_U("I2C3", "DIV_I2C3", CAR_DEV_U_I2C3), 553 CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4), 554 CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5), 555 CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6), 556 CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST), 557 CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS), 558 CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE), 559 CLK_GATE_Y("USB2_TRK", "UBS2_HSIC_TRK", CAR_DEV_Y_USB2_TRK), 560 CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK), 561 CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA), 562 }; 563 564 struct tegra210_init_parent { 565 const char *clock; 566 const char *parent; 567 } tegra210_init_parents[] = { 568 { "SDMMC1", "PLL_P" }, 569 { "SDMMC2", "PLL_P" }, 570 { "SDMMC3", "PLL_P" }, 571 { "SDMMC4", "PLL_P" }, 572 { "XUSB_HOST_SRC", "PLL_P" }, 573 { "XUSB_FALCON_SRC", "PLL_P" }, 574 { "XUSB_SS_SRC", "PLL_U_480M" }, 575 { "XUSB_FS_SRC", "PLL_U_48M" }, 576 }; 577 578 struct tegra210_car_rst { 579 u_int set_reg; 580 u_int clr_reg; 581 u_int mask; 582 }; 583 584 static struct tegra210_car_reset_reg { 585 u_int set_reg; 586 u_int clr_reg; 587 } tegra210_car_reset_regs[] = { 588 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG }, 589 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG }, 590 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG }, 591 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG }, 592 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG }, 593 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG }, 594 { CAR_RST_DEV_Y_SET_REG, CAR_RST_DEV_Y_CLR_REG }, 595 }; 596 597 static void * tegra210_car_reset_acquire(device_t, const void *, size_t); 598 static void tegra210_car_reset_release(device_t, void *); 599 static int tegra210_car_reset_assert(device_t, void *); 600 static int tegra210_car_reset_deassert(device_t, void *); 601 602 static const struct fdtbus_reset_controller_func tegra210_car_fdtreset_funcs = { 603 .acquire = tegra210_car_reset_acquire, 604 .release = tegra210_car_reset_release, 605 .reset_assert = tegra210_car_reset_assert, 606 .reset_deassert = tegra210_car_reset_deassert, 607 }; 608 609 struct tegra210_car_softc { 610 device_t sc_dev; 611 bus_space_tag_t sc_bst; 612 bus_space_handle_t sc_bsh; 613 614 struct clk_domain sc_clkdom; 615 616 u_int sc_clock_cells; 617 u_int sc_reset_cells; 618 619 kmutex_t sc_rndlock; 620 krndsource_t sc_rndsource; 621 }; 622 623 static void tegra210_car_init(struct tegra210_car_softc *); 624 static void tegra210_car_utmip_init(struct tegra210_car_softc *); 625 static void tegra210_car_xusb_init(struct tegra210_car_softc *); 626 static void tegra210_car_watchdog_init(struct tegra210_car_softc *); 627 static void tegra210_car_parent_init(struct tegra210_car_softc *); 628 629 630 CFATTACH_DECL_NEW(tegra210_car, sizeof(struct tegra210_car_softc), 631 tegra210_car_match, tegra210_car_attach, NULL, NULL); 632 633 static int 634 tegra210_car_match(device_t parent, cfdata_t cf, void *aux) 635 { 636 const char * const compatible[] = { "nvidia,tegra210-car", NULL }; 637 struct fdt_attach_args * const faa = aux; 638 639 #if 0 640 return of_match_compatible(faa->faa_phandle, compatible); 641 #else 642 if (of_match_compatible(faa->faa_phandle, compatible) == 0) 643 return 0; 644 645 return 999; 646 #endif 647 } 648 649 static void 650 tegra210_car_attach(device_t parent, device_t self, void *aux) 651 { 652 struct tegra210_car_softc * const sc = device_private(self); 653 struct fdt_attach_args * const faa = aux; 654 const int phandle = faa->faa_phandle; 655 bus_addr_t addr; 656 bus_size_t size; 657 int error, n; 658 659 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 660 aprint_error(": couldn't get registers\n"); 661 return; 662 } 663 664 sc->sc_dev = self; 665 sc->sc_bst = faa->faa_bst; 666 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 667 if (error) { 668 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 669 return; 670 } 671 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells)) 672 sc->sc_clock_cells = 1; 673 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells)) 674 sc->sc_reset_cells = 1; 675 676 aprint_naive("\n"); 677 aprint_normal(": CAR\n"); 678 679 sc->sc_clkdom.funcs = &tegra210_car_clock_funcs; 680 sc->sc_clkdom.priv = sc; 681 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) 682 tegra210_car_clocks[n].base.domain = &sc->sc_clkdom; 683 684 fdtbus_register_clock_controller(self, phandle, 685 &tegra210_car_fdtclock_funcs); 686 fdtbus_register_reset_controller(self, phandle, 687 &tegra210_car_fdtreset_funcs); 688 689 tegra210_car_init(sc); 690 691 #ifdef TEGRA210_CAR_DEBUG 692 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 693 struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]); 694 struct clk *clk_parent = clk_get_parent(clk); 695 device_printf(self, "clk %s (parent %s): ", clk->name, 696 clk_parent ? clk_parent->name : "none"); 697 printf("%u Hz\n", clk_get_rate(clk)); 698 } 699 #endif 700 } 701 702 static void 703 tegra210_car_init(struct tegra210_car_softc *sc) 704 { 705 tegra210_car_parent_init(sc); 706 tegra210_car_utmip_init(sc); 707 tegra210_car_xusb_init(sc); 708 tegra210_car_watchdog_init(sc); 709 } 710 711 static void 712 tegra210_car_parent_init(struct tegra210_car_softc *sc) 713 { 714 struct clk *clk, *clk_parent; 715 int error; 716 u_int n; 717 718 for (n = 0; n < __arraycount(tegra210_init_parents); n++) { 719 clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock); 720 KASSERT(clk != NULL); 721 clk_parent = clk_get(&sc->sc_clkdom, 722 tegra210_init_parents[n].parent); 723 KASSERT(clk_parent != NULL); 724 725 error = clk_set_parent(clk, clk_parent); 726 if (error) { 727 aprint_error_dev(sc->sc_dev, 728 "couldn't set '%s' parent to '%s': %d\n", 729 clk->name, clk_parent->name, error); 730 } 731 clk_put(clk_parent); 732 clk_put(clk); 733 } 734 } 735 736 static void 737 tegra210_car_utmip_init(struct tegra210_car_softc *sc) 738 { 739 bus_space_tag_t bst = sc->sc_bst; 740 bus_space_handle_t bsh = sc->sc_bsh; 741 742 /* 743 * Set up the UTMI PLL. 744 */ 745 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 746 0, CAR_UTMIP_PLL_CFG3_REF_SRC_SEL); 747 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG, 748 0, CAR_UTMIP_PLL_CFG3_REF_DIS); 749 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 750 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE); 751 delay(10); 752 /* TODO UTMIP_PLL_CFG0 */ 753 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 754 CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN, 0); 755 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 756 0, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); /* Don't care */ 757 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 758 0, CAR_UTMIP_PLL_CFG2_STABLE_COUNT); 759 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 760 0, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT); 761 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 762 0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 763 764 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB); 765 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY); 766 bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY); 767 768 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 769 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP | 770 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP | 771 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP, 772 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN | 773 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN | 774 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN); 775 776 /* 777 * Set up UTMI PLL under hardware control 778 */ 779 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0, 780 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP | CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 781 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 782 0, CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL); 783 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 784 CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE, 0); 785 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 786 0, CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL); 787 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 788 CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET, 0); 789 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 790 0, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY); 791 delay(1); 792 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG, 793 CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE, 0); 794 } 795 796 static void 797 tegra210_car_xusb_init(struct tegra210_car_softc *sc) 798 { 799 const bus_space_tag_t bst = sc->sc_bst; 800 const bus_space_handle_t bsh = sc->sc_bsh; 801 uint32_t val; 802 803 /* 804 * Set up the PLLU. 805 */ 806 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0); 807 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0); 808 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ); 809 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN); 810 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN); 811 delay(5); 812 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 813 __SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) | 814 __SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) | 815 __SHIFTIN(0x1, CAR_PLLU_BASE_DIVP), 816 CAR_PLLU_BASE_DIVN | CAR_PLLU_BASE_DIVM | CAR_PLLU_BASE_DIVP); 817 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0); 818 do { 819 delay(2); 820 val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 821 } while ((val & CAR_PLLU_BASE_LOCK) == 0); 822 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0); 823 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0); 824 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0); 825 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0); 826 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0); 827 delay(2); 828 829 /* 830 * Set up PLLREFE 831 */ 832 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG, 833 0, CAR_PLLREFE_MISC_IDDQ); 834 delay(5); 835 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 836 __SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) | 837 __SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) | 838 __SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) | 839 __SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP), 840 CAR_PLLREFE_BASE_DIVM | 841 CAR_PLLREFE_BASE_DIVN | 842 CAR_PLLREFE_BASE_DIVP | 843 CAR_PLLREFE_BASE_KCP); 844 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG, 845 CAR_PLLREFE_BASE_ENABLE, 0); 846 do { 847 delay(2); 848 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG); 849 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0); 850 851 /* 852 * Set up the PLLE. 853 */ 854 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE); 855 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC); 856 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE); 857 delay(5); 858 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, 859 __SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) | 860 __SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) | 861 __SHIFTIN(0x2, CAR_PLLE_BASE_DIVM), 862 CAR_PLLE_BASE_DIVP_CML | 863 CAR_PLLE_BASE_DIVN | 864 CAR_PLLE_BASE_DIVM); 865 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 866 CAR_PLLE_MISC_PTS, 867 CAR_PLLE_MISC_KCP | CAR_PLLE_MISC_VREG_CTRL | CAR_PLLE_MISC_KVCO); 868 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG, CAR_PLLE_BASE_ENABLE, 0); 869 do { 870 delay(2); 871 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG); 872 } while ((val & CAR_PLLE_MISC_LOCK) == 0); 873 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 874 __SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) | 875 __SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) | 876 __SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX), 877 CAR_PLLE_SS_CNTL_SSCINC | 878 CAR_PLLE_SS_CNTL_SSCINCINTRV | 879 CAR_PLLE_SS_CNTL_SSCMAX | 880 CAR_PLLE_SS_CNTL_SSCINVERT | 881 CAR_PLLE_SS_CNTL_SSCCENTER | 882 CAR_PLLE_SS_CNTL_BYPASS_SS | 883 CAR_PLLE_SS_CNTL_SSCBYP); 884 delay(1); 885 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET); 886 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL); 887 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL); 888 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL); 889 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0); 890 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0); 891 delay(1); 892 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0); 893 894 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB); 895 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB_PADCTL); 896 } 897 898 static void 899 tegra210_car_watchdog_init(struct tegra210_car_softc *sc) 900 { 901 const bus_space_tag_t bst = sc->sc_bst; 902 const bus_space_handle_t bsh = sc->sc_bsh; 903 904 /* Enable watchdog timer reset for system */ 905 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 906 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0); 907 } 908 909 static struct tegra_clk * 910 tegra210_car_clock_find(const char *name) 911 { 912 u_int n; 913 914 for (n = 0; n < __arraycount(tegra210_car_clocks); n++) { 915 if (strcmp(tegra210_car_clocks[n].base.name, name) == 0) { 916 return &tegra210_car_clocks[n]; 917 } 918 } 919 920 return NULL; 921 } 922 923 static struct tegra_clk * 924 tegra210_car_clock_find_by_id(u_int clock_id) 925 { 926 u_int n; 927 928 for (n = 0; n < __arraycount(tegra210_car_clock_ids); n++) { 929 if (tegra210_car_clock_ids[n].id == clock_id) { 930 const char *name = tegra210_car_clock_ids[n].name; 931 return tegra210_car_clock_find(name); 932 } 933 } 934 935 return NULL; 936 } 937 938 static struct clk * 939 tegra210_car_clock_decode(device_t dev, const void *data, size_t len) 940 { 941 struct tegra210_car_softc * const sc = device_private(dev); 942 struct tegra_clk *tclk; 943 944 if (len != sc->sc_clock_cells * 4) { 945 return NULL; 946 } 947 948 const u_int clock_id = be32dec(data); 949 950 tclk = tegra210_car_clock_find_by_id(clock_id); 951 if (tclk) 952 return TEGRA_CLK_BASE(tclk); 953 954 return NULL; 955 } 956 957 static struct clk * 958 tegra210_car_clock_get(void *priv, const char *name) 959 { 960 struct tegra_clk *tclk; 961 962 tclk = tegra210_car_clock_find(name); 963 if (tclk == NULL) 964 return NULL; 965 966 atomic_inc_uint(&tclk->refcnt); 967 968 return TEGRA_CLK_BASE(tclk); 969 } 970 971 static void 972 tegra210_car_clock_put(void *priv, struct clk *clk) 973 { 974 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 975 976 KASSERT(tclk->refcnt > 0); 977 978 atomic_dec_uint(&tclk->refcnt); 979 } 980 981 static u_int 982 tegra210_car_clock_get_rate_pll(struct tegra210_car_softc *sc, 983 struct tegra_clk *tclk) 984 { 985 struct tegra_pll_clk *tpll = &tclk->u.pll; 986 struct tegra_clk *tclk_parent; 987 bus_space_tag_t bst = sc->sc_bst; 988 bus_space_handle_t bsh = sc->sc_bsh; 989 u_int divm, divn, divp; 990 uint64_t rate; 991 992 KASSERT(tclk->type == TEGRA_CLK_PLL); 993 994 tclk_parent = tegra210_car_clock_find(tclk->parent); 995 KASSERT(tclk_parent != NULL); 996 997 const u_int rate_parent = tegra210_car_clock_get_rate(sc, 998 TEGRA_CLK_BASE(tclk_parent)); 999 1000 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg); 1001 divm = __SHIFTOUT(base, tpll->divm_mask); 1002 divn = __SHIFTOUT(base, tpll->divn_mask); 1003 if (tpll->base_reg == CAR_PLLU_BASE_REG) { 1004 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1; 1005 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) { 1006 /* XXX divp is not applied to PLLP's primary output */ 1007 divp = 0; 1008 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) { 1009 divp = 0; 1010 divm *= __SHIFTOUT(base, tpll->divp_mask); 1011 } else { 1012 divp = __SHIFTOUT(base, tpll->divp_mask); 1013 } 1014 1015 rate = (uint64_t)rate_parent * divn; 1016 return rate / (divm << divp); 1017 } 1018 1019 static int 1020 tegra210_car_clock_set_rate_pll(struct tegra210_car_softc *sc, 1021 struct tegra_clk *tclk, u_int rate) 1022 { 1023 struct tegra_pll_clk *tpll = &tclk->u.pll; 1024 bus_space_tag_t bst = sc->sc_bst; 1025 bus_space_handle_t bsh = sc->sc_bsh; 1026 struct clk *clk_parent; 1027 uint32_t bp, base; 1028 1029 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1030 if (clk_parent == NULL) 1031 return EIO; 1032 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); 1033 if (rate_parent == 0) 1034 return EIO; 1035 1036 if (tpll->base_reg == CAR_PLLX_BASE_REG) { 1037 const u_int divm = 1; 1038 const u_int divn = rate / rate_parent; 1039 const u_int divp = 0; 1040 1041 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 1042 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1043 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 1044 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1045 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1046 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 1047 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1048 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1049 1050 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 1051 base &= ~CAR_PLLX_BASE_DIVM; 1052 base &= ~CAR_PLLX_BASE_DIVN; 1053 base &= ~CAR_PLLX_BASE_DIVP; 1054 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 1055 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 1056 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 1057 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 1058 1059 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 1060 CAR_PLLX_MISC_LOCK_ENABLE, 0); 1061 do { 1062 delay(2); 1063 base = bus_space_read_4(bst, bsh, tpll->base_reg); 1064 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 1065 delay(100); 1066 1067 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 1068 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 1069 CAR_CCLKG_BURST_POLICY_CPU_STATE); 1070 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 1071 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 1072 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 1073 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 1074 1075 return 0; 1076 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) { 1077 const u_int divm = 1; 1078 const u_int pldiv = 1; 1079 const u_int divn = (rate << pldiv) / rate_parent; 1080 1081 /* Set frequency */ 1082 tegra_reg_set_clear(bst, bsh, tpll->base_reg, 1083 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) | 1084 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) | 1085 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP), 1086 CAR_PLLD2_BASE_REF_SRC_SEL | 1087 CAR_PLLD2_BASE_DIVM | 1088 CAR_PLLD2_BASE_DIVN | 1089 CAR_PLLD2_BASE_DIVP); 1090 1091 return 0; 1092 } else { 1093 aprint_error_dev(sc->sc_dev, "failed to set %s rate to %u\n", 1094 tclk->base.name, rate); 1095 /* TODO */ 1096 return EOPNOTSUPP; 1097 } 1098 } 1099 1100 static int 1101 tegra210_car_clock_set_parent_mux(struct tegra210_car_softc *sc, 1102 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) 1103 { 1104 struct tegra_mux_clk *tmux = &tclk->u.mux; 1105 bus_space_tag_t bst = sc->sc_bst; 1106 bus_space_handle_t bsh = sc->sc_bsh; 1107 uint32_t v; 1108 u_int src; 1109 1110 KASSERT(tclk->type == TEGRA_CLK_MUX); 1111 1112 for (src = 0; src < tmux->nparents; src++) { 1113 if (tmux->parents[src] == NULL) { 1114 continue; 1115 } 1116 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) { 1117 break; 1118 } 1119 } 1120 if (src == tmux->nparents) { 1121 return EINVAL; 1122 } 1123 1124 v = bus_space_read_4(bst, bsh, tmux->reg); 1125 v &= ~tmux->bits; 1126 v |= __SHIFTIN(src, tmux->bits); 1127 bus_space_write_4(bst, bsh, tmux->reg, v); 1128 1129 return 0; 1130 } 1131 1132 static struct tegra_clk * 1133 tegra210_car_clock_get_parent_mux(struct tegra210_car_softc *sc, 1134 struct tegra_clk *tclk) 1135 { 1136 struct tegra_mux_clk *tmux = &tclk->u.mux; 1137 bus_space_tag_t bst = sc->sc_bst; 1138 bus_space_handle_t bsh = sc->sc_bsh; 1139 1140 KASSERT(tclk->type == TEGRA_CLK_MUX); 1141 1142 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg); 1143 const u_int src = __SHIFTOUT(v, tmux->bits); 1144 1145 KASSERT(src < tmux->nparents); 1146 1147 if (tmux->parents[src] == NULL) { 1148 return NULL; 1149 } 1150 1151 return tegra210_car_clock_find(tmux->parents[src]); 1152 } 1153 1154 static u_int 1155 tegra210_car_clock_get_rate_fixed_div(struct tegra210_car_softc *sc, 1156 struct tegra_clk *tclk) 1157 { 1158 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; 1159 struct clk *clk_parent; 1160 1161 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1162 if (clk_parent == NULL) 1163 return 0; 1164 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1165 1166 return parent_rate / tfixed_div->div; 1167 } 1168 1169 static u_int 1170 tegra210_car_clock_get_rate_div(struct tegra210_car_softc *sc, 1171 struct tegra_clk *tclk) 1172 { 1173 struct tegra_div_clk *tdiv = &tclk->u.div; 1174 bus_space_tag_t bst = sc->sc_bst; 1175 bus_space_handle_t bsh = sc->sc_bsh; 1176 struct clk *clk_parent; 1177 u_int rate; 1178 1179 KASSERT(tclk->type == TEGRA_CLK_DIV); 1180 1181 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1182 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1183 1184 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg); 1185 u_int raw_div = __SHIFTOUT(v, tdiv->bits); 1186 1187 switch (tdiv->reg) { 1188 case CAR_CLKSRC_I2C1_REG: 1189 case CAR_CLKSRC_I2C2_REG: 1190 case CAR_CLKSRC_I2C3_REG: 1191 case CAR_CLKSRC_I2C4_REG: 1192 case CAR_CLKSRC_I2C5_REG: 1193 case CAR_CLKSRC_I2C6_REG: 1194 rate = parent_rate / (raw_div + 1); 1195 break; 1196 case CAR_CLKSRC_UARTA_REG: 1197 case CAR_CLKSRC_UARTB_REG: 1198 case CAR_CLKSRC_UARTC_REG: 1199 case CAR_CLKSRC_UARTD_REG: 1200 if (v & CAR_CLKSRC_UART_DIV_ENB) { 1201 rate = parent_rate / ((raw_div / 2) + 1); 1202 } else { 1203 rate = parent_rate; 1204 } 1205 break; 1206 case CAR_CLKSRC_SDMMC2_REG: 1207 case CAR_CLKSRC_SDMMC4_REG: 1208 switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) { 1209 case 1: 1210 case 2: 1211 case 5: 1212 raw_div = 0; /* ignore divisor for _LJ options */ 1213 break; 1214 } 1215 /* FALLTHROUGH */ 1216 default: 1217 rate = parent_rate / ((raw_div / 2) + 1); 1218 break; 1219 } 1220 1221 return rate; 1222 } 1223 1224 static int 1225 tegra210_car_clock_set_rate_div(struct tegra210_car_softc *sc, 1226 struct tegra_clk *tclk, u_int rate) 1227 { 1228 struct tegra_div_clk *tdiv = &tclk->u.div; 1229 bus_space_tag_t bst = sc->sc_bst; 1230 bus_space_handle_t bsh = sc->sc_bsh; 1231 struct clk *clk_parent; 1232 u_int raw_div; 1233 uint32_t v; 1234 1235 KASSERT(tclk->type == TEGRA_CLK_DIV); 1236 1237 clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); 1238 if (clk_parent == NULL) 1239 return EINVAL; 1240 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); 1241 1242 v = bus_space_read_4(bst, bsh, tdiv->reg); 1243 1244 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits); 1245 1246 switch (tdiv->reg) { 1247 case CAR_CLKSRC_UARTA_REG: 1248 case CAR_CLKSRC_UARTB_REG: 1249 case CAR_CLKSRC_UARTC_REG: 1250 case CAR_CLKSRC_UARTD_REG: 1251 if (rate == parent_rate) { 1252 v &= ~CAR_CLKSRC_UART_DIV_ENB; 1253 } else if (rate) { 1254 v |= CAR_CLKSRC_UART_DIV_ENB; 1255 raw_div = (parent_rate / rate) * 2; 1256 if (raw_div >= 2) 1257 raw_div -= 2; 1258 } 1259 break; 1260 case CAR_CLKSRC_I2C1_REG: 1261 case CAR_CLKSRC_I2C2_REG: 1262 case CAR_CLKSRC_I2C3_REG: 1263 case CAR_CLKSRC_I2C4_REG: 1264 case CAR_CLKSRC_I2C5_REG: 1265 case CAR_CLKSRC_I2C6_REG: 1266 if (rate) 1267 raw_div = (parent_rate / rate) - 1; 1268 break; 1269 case CAR_CLKSRC_SDMMC1_REG: 1270 case CAR_CLKSRC_SDMMC2_REG: 1271 case CAR_CLKSRC_SDMMC3_REG: 1272 case CAR_CLKSRC_SDMMC4_REG: 1273 if (rate) { 1274 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) { 1275 u_int calc_rate = 1276 parent_rate / ((raw_div / 2) + 1); 1277 if (calc_rate <= rate) 1278 break; 1279 } 1280 if (raw_div == 0x100) 1281 return EINVAL; 1282 } 1283 break; 1284 default: 1285 if (rate) { 1286 raw_div = (parent_rate / rate) * 2; 1287 if (raw_div >= 2) 1288 raw_div -= 2; 1289 } 1290 break; 1291 } 1292 1293 v &= ~tdiv->bits; 1294 v |= __SHIFTIN(raw_div, tdiv->bits); 1295 1296 bus_space_write_4(bst, bsh, tdiv->reg, v); 1297 1298 return 0; 1299 } 1300 1301 static int 1302 tegra210_car_clock_enable_gate(struct tegra210_car_softc *sc, 1303 struct tegra_clk *tclk, bool enable) 1304 { 1305 struct tegra_gate_clk *tgate = &tclk->u.gate; 1306 bus_space_tag_t bst = sc->sc_bst; 1307 bus_space_handle_t bsh = sc->sc_bsh; 1308 bus_size_t reg; 1309 1310 KASSERT(tclk->type == TEGRA_CLK_GATE); 1311 1312 if (tgate->set_reg == tgate->clr_reg) { 1313 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); 1314 if (enable) { 1315 v |= tgate->bits; 1316 } else { 1317 v &= ~tgate->bits; 1318 } 1319 bus_space_write_4(bst, bsh, tgate->set_reg, v); 1320 } else { 1321 if (enable) { 1322 reg = tgate->set_reg; 1323 } else { 1324 reg = tgate->clr_reg; 1325 } 1326 bus_space_write_4(bst, bsh, reg, tgate->bits); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static u_int 1333 tegra210_car_clock_get_rate(void *priv, struct clk *clk) 1334 { 1335 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1336 struct clk *clk_parent; 1337 1338 switch (tclk->type) { 1339 case TEGRA_CLK_FIXED: 1340 return tclk->u.fixed.rate; 1341 case TEGRA_CLK_PLL: 1342 return tegra210_car_clock_get_rate_pll(priv, tclk); 1343 case TEGRA_CLK_MUX: 1344 case TEGRA_CLK_GATE: 1345 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1346 if (clk_parent == NULL) 1347 return EINVAL; 1348 return tegra210_car_clock_get_rate(priv, clk_parent); 1349 case TEGRA_CLK_FIXED_DIV: 1350 return tegra210_car_clock_get_rate_fixed_div(priv, tclk); 1351 case TEGRA_CLK_DIV: 1352 return tegra210_car_clock_get_rate_div(priv, tclk); 1353 default: 1354 panic("tegra210: unknown tclk type %d", tclk->type); 1355 } 1356 } 1357 1358 static int 1359 tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate) 1360 { 1361 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1362 struct clk *clk_parent; 1363 1364 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 1365 1366 switch (tclk->type) { 1367 case TEGRA_CLK_FIXED: 1368 case TEGRA_CLK_MUX: 1369 return EIO; 1370 case TEGRA_CLK_FIXED_DIV: 1371 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1372 if (clk_parent == NULL) 1373 return EIO; 1374 return tegra210_car_clock_set_rate(priv, clk_parent, 1375 rate * tclk->u.fixed_div.div); 1376 case TEGRA_CLK_GATE: 1377 return EINVAL; 1378 case TEGRA_CLK_PLL: 1379 return tegra210_car_clock_set_rate_pll(priv, tclk, rate); 1380 case TEGRA_CLK_DIV: 1381 return tegra210_car_clock_set_rate_div(priv, tclk, rate); 1382 default: 1383 panic("tegra210: unknown tclk type %d", tclk->type); 1384 } 1385 } 1386 1387 static int 1388 tegra210_car_clock_enable(void *priv, struct clk *clk) 1389 { 1390 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1391 struct clk *clk_parent; 1392 1393 if (tclk->type != TEGRA_CLK_GATE) { 1394 clk_parent = tegra210_car_clock_get_parent(priv, clk); 1395 if (clk_parent == NULL) 1396 return 0; 1397 return tegra210_car_clock_enable(priv, clk_parent); 1398 } 1399 1400 return tegra210_car_clock_enable_gate(priv, tclk, true); 1401 } 1402 1403 static int 1404 tegra210_car_clock_disable(void *priv, struct clk *clk) 1405 { 1406 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1407 1408 if (tclk->type != TEGRA_CLK_GATE) 1409 return EINVAL; 1410 1411 return tegra210_car_clock_enable_gate(priv, tclk, false); 1412 } 1413 1414 static int 1415 tegra210_car_clock_set_parent(void *priv, struct clk *clk, 1416 struct clk *clk_parent) 1417 { 1418 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1419 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent); 1420 struct clk *nclk_parent; 1421 1422 if (tclk->type != TEGRA_CLK_MUX) { 1423 nclk_parent = tegra210_car_clock_get_parent(priv, clk); 1424 if (nclk_parent == clk_parent || nclk_parent == NULL) 1425 return EINVAL; 1426 return tegra210_car_clock_set_parent(priv, nclk_parent, 1427 clk_parent); 1428 } 1429 1430 return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent); 1431 } 1432 1433 static struct clk * 1434 tegra210_car_clock_get_parent(void *priv, struct clk *clk) 1435 { 1436 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); 1437 struct tegra_clk *tclk_parent = NULL; 1438 1439 switch (tclk->type) { 1440 case TEGRA_CLK_FIXED: 1441 case TEGRA_CLK_PLL: 1442 case TEGRA_CLK_FIXED_DIV: 1443 case TEGRA_CLK_DIV: 1444 case TEGRA_CLK_GATE: 1445 if (tclk->parent) { 1446 tclk_parent = tegra210_car_clock_find(tclk->parent); 1447 } 1448 break; 1449 case TEGRA_CLK_MUX: 1450 tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk); 1451 break; 1452 } 1453 1454 if (tclk_parent == NULL) 1455 return NULL; 1456 1457 return TEGRA_CLK_BASE(tclk_parent); 1458 } 1459 1460 static void * 1461 tegra210_car_reset_acquire(device_t dev, const void *data, size_t len) 1462 { 1463 struct tegra210_car_softc * const sc = device_private(dev); 1464 struct tegra210_car_rst *rst; 1465 1466 if (len != sc->sc_reset_cells * 4) 1467 return NULL; 1468 1469 const u_int reset_id = be32dec(data); 1470 1471 if (reset_id >= __arraycount(tegra210_car_reset_regs) * 32) 1472 return NULL; 1473 1474 const u_int reg = reset_id / 32; 1475 1476 rst = kmem_alloc(sizeof(*rst), KM_SLEEP); 1477 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; 1478 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1479 rst->mask = __BIT(reset_id % 32); 1480 1481 return rst; 1482 } 1483 1484 static void 1485 tegra210_car_reset_release(device_t dev, void *priv) 1486 { 1487 struct tegra210_car_rst *rst = priv; 1488 1489 kmem_free(rst, sizeof(*rst)); 1490 } 1491 1492 static int 1493 tegra210_car_reset_assert(device_t dev, void *priv) 1494 { 1495 struct tegra210_car_softc * const sc = device_private(dev); 1496 struct tegra210_car_rst *rst = priv; 1497 1498 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); 1499 1500 return 0; 1501 } 1502 1503 static int 1504 tegra210_car_reset_deassert(device_t dev, void *priv) 1505 { 1506 struct tegra210_car_softc * const sc = device_private(dev); 1507 struct tegra210_car_rst *rst = priv; 1508 1509 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); 1510 1511 return 0; 1512 } 1513
Indexes created Mon Oct 27 08:10:08 GMT 2025